DESIGN AND SIMULATION OF 1 BIT ARITHMETIC LOGIC UNIT … · 2018-09-29 · Logic (PTL) describes...

DESIGN AND SIMULATION OF 1BIT ARITHMETIC LOGIC UNIT

DESIGN USINGPASS-TRANSISTORLOGIC FAMILIES

V. Venkata Rao1, T.Indira2,Ch. Krishna Priya3, P. Vasanthi4

1Professor and Head of the Department of ECE2,3,4Assistant Professor,

Narasaraopeta Engineering CollegeNarasaraopet, Guntur (Dist.), A.P. India

[email protected]

June 21, 2018

Abstract

In this paper a 1 bit Arithmetic Logic Unit has beendesigned and implemented with a combinational logiccircuits containing a number of functional components fordifferent arithmetic and logic operationsusingTransmission Gate Logic (TGL) andDual Value Logic(DVL). The performance of developed Arithmetic LogicUnit Design has been analyzed and compared in terms ofarea and power usingTSMCCMOS 90nm, 70nm and 50nmtechnology. The schematic circuit of 1 bit ArithmeticLogic Unit has been designed using DSCH tool and itsequivalent layout has been created using Microwind tool.It can be observed from simulation results that 90nm,70nm and 50nm technology based Arithmetic Logic UnitDesignusingDual Value Logichas shown reduced transistorcount, area and Power compare to the Arithmetic LogicUnit Design using CPL,DPL & TGL.

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International Journal of Pure and Applied MathematicsVolume 120 No. 6 2018, 4163-4178ISSN: 1314-3395 (on-line version)url: http://www.acadpubl.eu/hub/Special Issue http://www.acadpubl.eu/hub/

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Keywords:Arithmetic Logic Unit, Transmission GateLogic, Dual Value Logic.

1 INTRODUCTION

Digital circuits design combinational circuits that implements afunction of its inputs based on either arithmetic or logic functionsconsists of logic gates implemented in the Complementary MetalOxide Semiconductor (CMOS) technology. In Digital circuitsdesign mainlythree parameters power, delayand area areconsidered.The dynamic power is consumed only when thecircuitperforms a function and signals change zero to one and oneto zero. The circuitLeakage or static power is consumed all thetime, i.e., even when the circuit is idle. The dynamic powercannot be eliminated completely because it is caused by thecomputing activity. It can, however, be reduced by circuit designtechniques. Whenever a logic gate changes state, power isconsumed. The solution is then realized at the transistor leveldesigns. In this work, a 1-bit ALU is designed at transistor levelfor low power and minimum area. The rest of the paper isorganized as follows; Section II will discuss about thePass-Transistor Logic Families. Section III will discuss on the overview ofArithmetic Logic Unit. Section IV will discuss onArithmetic Logic Unit Using TGL and DVL. Section V conductsa comparative simulation study among the Arithmetic Logic UnitUsing TGL and DVL, with a detailed discussion on the derivedresults. Section VI provides the summary and final conclusions ofthe work presented.

2 PASS-TRANSISTOR LOGIC

FAMILIES

In Digital electronics circuits design using the Pass TransistorLogic (PTL) describes several logic families used in the design ofintegrated circuits. By usingPass Transistor Logic designthetransistorscount can be reducedcomparedto different logicgates,byeliminating redundant transistors.There are mainly two

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design types ofpass-transistor circuit styles: One is thepass-transistor circuits design which uses only NMOSpass-transistorcalled Complementary Pass-transistor Logic (CPL)and second one is pass-transistor circuits design which uses bothNMOS and PMOS transistors whichcan be used as DoublePass-transistor Logic(DPL),Transmission Gate Logic (TGL)andDual value logic(DVL).

A. Complementary pass-transistor logicComplementary pass-transistor logic circuit (CPL)[1] consistsofcomplementary inputs/outputs, a NMOS pass-transistornetwork, and it can be used to connectinverter on output sideusing CMOS as shown in Fig 2.1(a). The circuit function isimplemented as a tree consisting of pull-down and pull-upbranches. Since the threshold voltage drop of NMOS transistordegrades the high level of pass-transistor output nodes, the outputsignals are restored by CMOS inverters.CPL has traditionallybeen applied to the arithmetic building blocks and has beenshown to result in high-speed operation due to its low inputcapacitance and reduced transistor count. Design of two inputAND/NAND logic using CPL and OR/ NOR logic using CPL asshown in Fig 2.1(b) and (c).

Figure 2.1: (a) Complementary pass-transistor logic circuit.(b)AND/NAND logic using CPL (c) OR/ NOR logic using CPL

B. Double pass-transistor logicTo avoid problems of reduced noise margins in CPL, twin PMOStransistor branches are added to N-tree in DPL [2].This additionresults in increased input capacitances.However its symmetricalarrangement and double-transmission characteristics compensate

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for the speed degradation arising from increased loading. The fullswing operation improves circuit performance at reduced supplyvoltage with limited threshold voltage scaling.Design of two inputAND & NAND logic using DPL as shown in Fig 2.2(a) and (b).

Figure 2.2: (a) AND logic using DPL. (b)NAND logic using CPL

C.Transmission Gate LogicThe Transmission Gate Logic design [3] using CMOS gate toappreciate advanced logic functions employing a PMOS andNMOS that is called complementary transistors. Transmissiongate has a switch with low resistance and capacitance having ratioless logic. Also, DC characteristic of this gate is independent ofinput levels. It is designed by NMOS and PMOS transistorsconnecting the source to source and drain to drain terminals.Because the NMOS transistor is switching strong signal 1 andPMOS transistors switching strong signal 0 each transistor isflipped on-off by the enable signals, then input pass towards theoutput, the symbolas shown in Fig 2.3(a) and truth table ofTransmission Gate Logic as shown in Truth Table 1.The belowTransmission Gate Logic voltage is applied on X node is a HIGH,the complementary Logic zero is applied to LOW on . The twotransistors (NMOS and PMOS) conduct and pass the signal fromINPUT to OUTPUT. The AND gate and OR gate using TGL areshown in Fig. 2.3(b) and (c).The 2-input TGL AND/OR gatesare full-swinging, but not restoring for all input combinations.

D. Dual value logicThe main drawback of DPL is its redundancy, i.e. itrequires moretransistors than actually needed for the realization of a function.To overcome the problem of redundancy, a new logic family, DVL[4], is derived from DPL. It preserves the full swing operation ofDPL with reduced transistor count. As introduced in DVL circuit

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Figure 2.3: (a) Transmission Gate (b) TGL AND gate (c) TGL ORgate

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can be derived from DPL and TGL circuits in three steps,consisting of:Elimination of redundant branches,Signalrearrangement (resize),Selection of the faster halves.

The AND gate and OR gate using DVL as shown in Fig. 2.4(a)and (b).The 2-input DVL AND/OR gates are full- swinging butnon-restoring, as well. The style we consider in this work is DVL,which preserves the full swing operation of DPL and TGL withreduced transistor count.

Figure 2.4: (a) DVL AND gate. (b) DVL OR gate.

3 OVER VIEW OF ARITHMETIC

LOGIC UNIT

An arithmetic-logic unit (ALU) is the part of a computerprocessor (CPU) that carries out arithmetic and logic operationson the operands in computer instruction words. In someprocessors, the ALU is divided into two units, an arithmetic unit(AU) and a logic unit (LU). Inan arithmetic-logic unit (ALU)design different blockssuch as decoder, full adder, logical circuitsand summing circuit are combined as shown in Fig.3.1.In thearithmetic unit, multiplication and division are done by a series ofadding or subtracting and shifting operations..In the logicunit,OR, AND, XOR and XNOR operations are designed.

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Figure 3.1: Block diagram of 1 bit Arithmetic Logic Unit.

4 1 Bit ARITHMETIC LOGIC UNIT

using TGL and DVL

A. 1 Bit Arithmetic Logic Unit using Transmission gate logicIn this method 1 bit Arithmetic-Logic Unitis designed usingTransmission Gate Logic as shown in Fig.4.1.

B. Arithmetic Logic Unit using Dual value logicIn this method 1 bit Arithmetic-Logic Unitis designed using Dualvalue logic as shown in Fig.4.2.

1 Bit Arithmetic Logic Unit using Transmission Gate LogicandDual Value Logicthat generates output depending on threecontrol inputs are F0 , F1 & F2 and 2 input variables A and B &carry in . Its operation is summarized in Table II.

• If control inputs are F0, F1 & F2 is “000” condition ,WhenA & B inputs receive binary numbers and Cin is zero, thenOR logic operation is performed.

• If control inputs are F0, F1 & F2 is “001” condition ,WhenA & B inputs receive binary numbers and Cin is zero ,then B

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Figure 4.1: 1 Bit Arithmetic Logic Unit using Transmission gatelogic.

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Figure 4.2: 1 Bit Arithmetic Logic Unit using Dual value logic

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input are complemented operation is performed.

• If control inputs are F0, F1 & F2 is “010” condition ,WhenA & B inputs receive binary numbers and Cin is zero, thenmultiplication operation is performed.

• If control inputs are F0, F1 & F2 is “011” condition ,WhenA & B inputs receive binary numbers and Cin is zero, anaddition with carry operation is performed.

• If control inputs are F0, F1 & F2 is “100” condition ,WhenA & B inputs receive binary numbers and Cin is zero, thenXOR logic operation is performed.

• If control inputs are F0, F1 & F2 is “101” condition ,WhenA & B inputs receive binary numbers and Cin is zero, thenXNOR logic operation is performed.

• If control inputs are F0 ,F1 & F2 is “110” condition ,WhenA & B inputs receive binary numbers and Cin is zero, thenLogic ’0’ operation is performed.

• If control inputs are F0 ,F1 & F2 is “111” condition ,WhenA & B inputs receive binary numbers and Cin is zero, thenLogic ’1’ operation is performed.

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5 RESULTS AND DISCUSSIONS

In this paper, the 1 Bit ALU design using TGL and DVLschematic circuits are drawn and simulated output waveforms aregenerated. The power results of 1 Bit ALU design using TGL andDVL are tabulated. We perform the simulations using Microwindtoolin 90nm, 70nm & 50nm technology and observed that in 1 BitALU design using DVL circuit the power and area are reducedcompared to the 1 Bit ALU design using TGL in differenttechnologies. The corresponding waveforms are shown below.

Figure 5.1: Output wave form of 1 Bit ALU using TGL using 90nm CMOS Technology.

6 CONCLUSIONS

As per the analysis the power consumption is minimum with thechannel length of50 nm for the TSMCmodel compared to that ofTSMC model with channel length 90 nm and 70nm. 1 Bit ALUdesign using DVL circuit reduced the power and area compared tothe 1 Bit ALU design using TGL in different technologies.

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Figure 5.4: Output wave form of 1 Bit ALU using DVL using 90nm CMOS Technology.


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References

[1] K. Yano et al., “A 3.8-ns CMOS 16 16-b multiplier usingcomplementary pass-transistor logic”, IEEE J. Solid-StateCircuits, vol. 25, no. 2, pp. 388393, Apr.1990.

[2] M. Suzuki et al., “A 1.5 ns 32b CMOS ALU in double pass-transistor logic”,in Proc. IEEE Int. Solid-State Circuits Conf.,1993, pp.9091.

[3] X. Wu, “Theory of transmission switches and its application todesign of CMOS digital circuits”, Int. J. Circuit Theory Appl.,vol. 20, no. 4, pp. 349356,1992.

[4] V. G. Oklobdzija and B.Duchene, “Pass-transistordualvaluelogic for low-power CMOS”, inProc.Int. Symp. VLSI Technol., 1995, pp. 341344.

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