LOGIC GATESDigital Signals A digital signal has two discrete levels or values. Two representations of digital

signals are as shown below.

In each case there are two discrete levels and the levels can be represented using the

terms LOW and HIGH. Fig (a), the lower of the two levels has been designated as LOW and higher level as HIGH level. In Fig. (b), the designation has been reversed.

Digital systems using the representation in Fig. (a) are said to employ positive logic system and those using the other representation of Fig. (b) are said to employ negative logic system.

Truth Tables A truth table is means of describing how a logic circuit’s output depends on the logic

levels present at the circuit’s inputs e.g. Inputs Outputs

A B X0 0 00 1 11 0 11 1 0

Truth table for three or four inputs can also been drawn depending on the inputs present at circuit.

Boolean Expression It’s a simple mathematical tool allows the description of the relationship between logic

circuit output (s) and its inputs as an algebraic equation e.g.

BASIC LOGIC GATES Logic gates are the basic building blocks for forming digital electronic circuitry. It

has one output terminal and one or more input terminals. Some of these gates include:-

a) INVERTER (or NOT gate)b) AND gatec) OR gated) NAND gate

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e) NOR gatef) Exclusive-OR gate (EXOR)g) Exclusive-NOR gate

The INVERTER, AND and OR gate are the basic gates. The NAND, NOR, Exclusive-OR and Exclusive-NOR gates are derived gates.

(i) The INVERTER or NOT gate Its gate that performs inversion (or complementation) operation. It has one input

(A) and one output (B). Its logic symbols are as shown.

The truth table of a NOT gate is

Input Output

A Y0 11 0

The operation of a NOT gate can be expressed in the Boolean expression as It states that the output X is complement or opposite of the input A i.e. X = 0 if A = 1, and X = 1 if A = 0. AN electronic implementation this gate is as shown.

When is low (0 V) transistor is cut off and is unable to conduct, thus full

voltage of is available at the output. Whereas when is high (+5 V), it will

make the transistor to conduct and thus giving a low

(ii) The AND gate It’s composed of 2 or more inputs and a single output. Its logic symbol for 2-

input AND gate is as shown.

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The truth table of a 2-input AND gate is

Inputs outputsA B Y0 0 00 1 01 0 01 1 1

Logic operation: An AND gate produces a HIGH (1) output only when all of the inputs are HIGH (1) else the output is LOW (1).Example 1 Determine the total number of possible input combinations of a 3-input AND gate. Sketch a logic symbol and develop a truth table for this logic gate.SolutionA 3-input AND gate has eight possible combination i.e. . The symbol and truth table of a 3-input AND gate is as shown.

Inputs Outputs

A B C Y0 0 0 00 0 1 00 1 0 00 1 1 01 0 0 01 0 1 01 1 0 01 1 1 1

Exercise: Determine the total number of possible input combinations of a 4-input AND gate. Sketch a logic symbol and develop a truth table for this logic gate.

Pulse operation of an AND gate Example 2 Consider the two waveforms below:-

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Hence, applying the rules of AND gate as shown in the truth table, the output

Y as shown in obtained. Example 3 The Fig. below shows two input waveforms, A and B applied to an AND gate.

Boolean Expression for an AND gate

The operation of an AND gate can be expressed in the Boolean expression

The AND operation can be extended to more than two variables. For example, the

three and four input AND operation Boolean expressions are expressed as:-

and The electronic implementation this gate is as shown below.

When inputs A and B are low, both diodes are connected to +5 V and thus they

are forward biased and conduct pulling down the output to low value. If one input is low, the diode with low input conducts pulling down the output to low. If both inputs are high, both diodes being reversed biased get cut-off and supply voltage, high appears at the output, hence it’s through table.

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(iii) The OR gate OR gate is also basic logic gate from which all logic functions are constructed. It

composed of two or more input and one output. The symbol of a 2-input OR gate and its truth table is shown.

The truth table of a 2-input OR gate is

Inputs outputsA B Y0 0 00 1 11 0 11 1 1

Logic operation: An OR gate produces a HIGH (1) output when any of the inputs are HIGH (1) else the output is LOW (1). Example 4 Determine the total number of possible input combinations of a 3- input OR gate. Also draw a logic symbol and develop a truth table for this logic gate. Solution A 3-input OR gate has eight possible combination i.e. . The symbol and

truth table of a 3-input OR gate is as shown.

Inputs OutputsA B C Y0 0 0 00 0 1 10 1 0 10 1 1 11 0 0 11 0 1 11 1 0 11 1 1 1

Exercise: Determine the total number of possible input combinations of a 4-input OR gate. Sketch a logic symbol and develop a truth table for this logic gate

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Pulse operation of an OR gateExample 5

Example 6 The Fig. below shows the two input waveforms A and B applied to an OR gate. The resulting output is as shown in waveform Y.

Exercise: The Fig. below shows the three input waveforms, A, B, and C applied to an OR gate. Sketch the resulting output waveform at Y.

Boolean expression for an OR Gate OR gate operate on the Boolean expression For a three or four input OR gates, the Boolean expressions becomes

and The electronic implementation this gate is as shown below

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If both inputs are low (0), then both diodes do not conduct, giving low (0) output at Y.If any input is is high, the diode with that high input conducts, giving high (1) output. If both inputs are high, both diodes conduct, giving high (1) output.

UNIVERSAL LOGIC GATES They are referred to as universal logic gates because they can be used to realize

any logic expression. They are derived from the basic logic gates. These are NAND and NOR gates.

The NAND gate

The term NAND is a contraction of NOT-AND. It implies an AND function with a complemented (or inverted) output. The standard logic symbol for a 2-input NAND gate is as shown.

The small circle (or a bubble) on its output denotes the inversion operation. Thus a NAND gate operates like an AND gate followed by a NOT as show below.

It truth table a 2-input NAND is

Inputs outputsA B Y0 0 10 1 11 0 11 1 0

Logical operation of the NAND gate

NAND gate produces a LOW (0) output only when all the inputs are HIGH (1). When any of the inputs is LOW (0), the output will be HIGH (1).

Pulsed Operation of a NAND Gate

In order to determine the output level of an NAND gate, we look at the inputs with respect to each other with reference to the truth table. Some examples are given below

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Example 7

Example 8 The figure below shows the two waveforms applied to the NAND gate inputs. Determine the resulting output waveform.

Exercise Sketch the output waveform for the 3-input NAND gate shown in the figure below showing its proper time relationships to the inputs

Boolean Expression for the NAND Gate The Boolean expression representing NAND function is This expression means that the two input variables, A and B are first ANDed and

then inverted (or complemented) as indicated by the bar over the AND expression.

For a three and four input OR gates, the Boolean expressions becomes and

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The NOR gate

The term NOR is a contraction of NOT-OR. It implies an OR function with a complemented (or inverted) output. The standard logic symbol for a 2-input NOR gate is as shown.

The small circle (or a bubble) on its output denotes the inversion operation. Thus

a NOR gate operates like an OR gate followed by a NOT as show below.

It truth table a 2-input NOR is

Inputs outputsA B Y0 0 10 1 01 0 01 1 0

Logical operation of the NAND gate

The NOR gate produces a LOW (0) output when any of the inputs is HIGH (1). The output is HIGH (1) only when all of the inputs are LOW (0).

Pulsed Operation of a NOR Gate

Example 10 Consider waveforms A and B applied at the inputs of a 2-input NOR gate as shown.

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Exercise Sketch the output waveform for a 3-input NOR gate shown below, showing the proper time relationships to the inputs.

Boolean Expression for a NOR gate The Boolean expression representing NAND function is This expression means that the two input variables, A and B are first ORed and

then inverted (or complemented) as indicated by the bar over the OR expression. For a three and four input OR gates, the Boolean expressions becomes and

The Exclusive-OR and Exclusive-NOR gates

Both these gates are formed by combination of the basic gates i.e. Inverter, AND and OR gates. But because of their fundamental importance in many applications, they are treated as basic logic gates with their unique symbols.

The Exclusive- OR (XOR) gate Unlike other gates, this gate has only two inputs and one output. Its logic symbol

is as shown.

The truth table of a 2-input XOR gate is

Inputs output

A B Y0 0 00 1 11 0 11 1 0

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Logic Operation The output is HIGH (1) only when the two inputs are at opposite logic levels. The

output is LOW (0) when the two inputs are at the same logic levels.

Pulsed Operation of a XOR Gate

Example 11 Consider the two waveforms, A and B being the inputs of an XOR gate shown. The output waveform is as shown in Y.

Exercise Sketch the output waveform for an XOR gate with the input waveforms as shown in the figure below.

Boolean Expression for a XOR gate The Boolean expression representing XOR function is

The Exclusive-NOR (XNOR) gate

It has only two inputs and one output. Its logic symbol is as shown.

The truth table of a 2-input XNOR gate is

Inputs output

A B Y0 0 1

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0 1 01 0 01 1 1

Logic Operation The output of this gate is HIGH (1) only when the two inputs are at the same logic

level. The output is LOW (0) when the two inputs are at opposite logic levels.

Pulsed Operation of a XNOR Gate

To determine the output waveform, we look at the inputs with respect to each other with reference to the truth table. Some examples are given below:-

Example 12 Consider the two waveforms, A and B being the inputs of an XOR gate shown. The output waveform is as shown in Y.

Exercise Sketch an output waveform for an exclusive-NOR gate with the input waveforms as shown below.

Boolean Expression for a XNOR gate

The Boolean expression for an XNOR gate is given by the equation

ASSINGMENT 21. Realize the following logic operations using only NOR gates

a) NAND (b) XOR (c) XNOR [9 marks]2. Realize the following logic operations using only NAND gates [9 marks]

NAND (b) XOR (c) XNOR

Determination of Boolean Expression for a Logic Circuit

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Irrespective of how complex a logic circuit is, it can completely be described using the Boolean expressions.

Consider the circuit below

Also consider the circuit below

Example 13 Write the Boolean expression for output Y for logic circuit shown the figure below.

Example 14 Write the Boolean expression for output Y for logic circuit shown the figure below.

Thus, the Boolean expression for the final output is

Exercise Determine the Boolean expression for the output X for the logic circuit shown in the figure below.

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Evaluating the Boolean Expression for the Logic Circuit Output After obtaining the Boolean expression as shown above, the output logic can be

determine for any set of input levels. The following general rules are followed.(i) First, perform all inversions of single terms; i.e. (ii) Then perform all operations within parentheses.(iii) Perform an AND operation before an OR operation unless parentheses indicates

otherwise(iv) If an expression has a bar over it, perform the operation of the expression first

then invert the result.

Example 15 Suppose we want to know the logic level Y for the circuit below for the case where and .

Substituting the values of the variables A, B, and C into the output expression have

Determination of a Truth table for a Logic Circuit

Once the Boolean expression for all the possible combination of the inputs variables have evaluated as shown above, the result can be summarized in a truth table.

To illustrate this concept, consider the circuit below.

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We can then evaluate all the possible combination of the input variables and

determine the logic level of the final output. The results are as shown in the table below.

Inputs output

A B C Y0 0 0 00 0 1 00 1 0 10 1 1 11 0 0 11 0 1 01 1 0 11 1 1 1

Implementing Logic Circuits from Boolean Expression

A logic circuit can be implemented directly from Boolean expression. For example, a circuit defined by , can be implemented using a 3-input AND gate. If on the other hand a circuit is defined by , then a two-input OR with an NOT gate on one of the input terminal is used to implement it. This can be extended to more complex logic circuits.

Example 16 Construct a circuit whose output is Solution

The expression has three terms which are ORed together. Hence it shows that a 3-input OR gate is required with inputs equal to

, respectively i.e.

Since each OR gate input is an AND product term, then it means that an AND

gate with appropriate inputs can be used to generate each of these terms i.e.

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Example 17 Sketch the logic circuit for the Boolean expressions:a) b)

Solution

Exercise Construct the logic circuits that can implement the Boolean expressions:

a) b) c) d)

The Universality of NAND and NOR Gates

These gates can be used to implement the basic gates as well as each other.

The NAND gate as a universal logic gate An INVERTER can be made from a NAND gate by connecting all of its inputs

together i.e.

It can be used as an AND gate as

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It can also be implemented as an OR gate as

The NOR gate as a universal logic gate

Like NAND, NOR gate can be used to implement the INVERTER i.e.

An OR can be performed by connecting a 2-input gates as shown

An AND gate operation can be performed by connecting 3 NOR gates as show.

COMBINATIONAL LOGIC DESIGNIntroduction

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Boolean algebra theorems are used for the manipulations of logic expressions. It has been shown that a logical expression can be realized using the logic gates. The number of gates and the number of input terminals for the gates required for the realization of a logical expression, in general, get reduced considerably if the expression can be simplified.

Thus, simplification of logical expression is very important as is saves the hardware required to design a specific system.

Basically, digital circuits are divided into two broad categories:(i) Combinational circuits, and (ii) Sequential circuits

In combinational circuits, the outputs at any instant of time depend upon the inputs present at that instant of time. Thus, these circuits have no memory.

There are other types of circuits in which the outputs at any instant of time depend upon the present inputs as well as the past inputs/outputs. This implies that they have memory. Such circuits are known as sequential circuits.

The design requirements of combinational circuits may be specified in any of the following ways:(i) A set of statements(ii) Boolean expression, and (iii) Truth table

There are two approaches to the design of combinational circuits. One is the traditional method, where the given Boolean expression or the truth table is simplified by using standard methods and the simplified expression is realized using logic gates. The other method does not require any simplification of the logical expression or truth table; instead the complex logic functions available in medium scale integrated circuits (MSI) can be directly used. Computer-aided design (CAD) tools are used for the design using Programmable logic devices (PLDs).

Boolean algebra and logic simplification

Boolean algebra is a convenient and systematic way of expressing and analyzing the operation of logic circuits. It’s named after George Boole who invented it.

Laws and rules of Boolean algebra The main laws which are necessary for manipulating different Boolean

expressions. 1) OR Rules

(i) (ii) (iii) (iv)

2) AND Rules(i)(ii)(iii)(iv)

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3) Laws of Complementation(i)(ii)(iii) If then (iv) If then (v)

4) Commutative laws These laws allow changes of position of variables in OR and AND expressions

(i)(ii)

5) Associative laws These laws allow removal of brackets from logic expressions and regrouping of

variables.(i)(ii)(iii)

6) Distributive laws These laws permit factoring or multiplying out of an expression

(i)(ii)(iii)

7) Absorptive laws These laws are used in reduction of a complex expression to a simpler form by

absorbing some of the terms into existing terms (i)(ii)(iii)

Example 1: Prove the following Boolean identity Solution

(But )Then

Example 2 Prove that the following Boolean identity Solution Let

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Example 3 Prove the following Boolean identity Solution Let Example 4 Using the truth table, show that the Boolean expression

A B AB A+AB0 0 0 00 1 0 01 0 0 11 1 1 1

Hence, from the table, the columns of A and A+AB are the same and hence

Example 5 Using the truth table, show that the Boolean,

A B A+B0 0 1 0 0 00 1 1 1 1 11 0 0 0 1 11 1 0 0 1 1

An inspection of the fifth and sixth columns indicates that they are the same. This verifies that

Example 6 Using the truth table, show that the Boolean expression,

A B C A+B A+C (A+B)(A+C) BC A+BC0 0 0 0 0 0 0 00 0 1 0 1 0 0 00 1 0 1 0 0 0 00 1 1 1 1 1 1 11 0 0 1 1 1 0 11 0 1 1 1 1 0 11 1 0 1 1 1 0 11 1 1 1 1 1 1 1

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The sixth and the eighth columns are the same. This verifies that

Example 7 Using the Boolean laws and rules simplify the expression and implement the minimized expression using logic gates: Solution (Using distributive law) (Using the rule )

Example 8 Using the Boolean laws and rules, simplify the following expression and implement the minimized expression using logic gates: Solution (Using distributive law) (Since )

Example 9 Using Boolean algebra techniques, simply the expression:

Solution (Using distributive law) (Since ) (Since ) (Since ) (Since )

Example 10 Using laws and rules of Boolean algebra simplify the Boolean the following expression and implement the simplified expression.

Solution

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(Using distributive laws) (Since ) (Since ) (Using distributive laws) (Since ) (Factoring out ) (Since )

Exercise

(i) Simplify the following Boolean expression and draw the logic circuits for the simplified expressions.a) (ans: ) b) (ans: ) c) (ans: )

De Morgan’s Theorem

De Morgan proposed the following theorems that are an important part of Boolean algebra:

Theorem 1: The complement of a product of variables is equal to the sum of the complements of the variables i.e. Theorem 2: The complement of a sum of variables is equal to the product of the complements of the variables i.e. In terms of logic circuits, theorem 1 can be illustrated as

In terms of logic circuits, theorem 2 can be illustrated as

Example 11 Apply De Morgan’s theorems to the following Boolean expressions with 3 variables:

a) and b)

Solutiona) , applying De Morgan’s theorem 1 =

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b) applying De Morgan’s theorem 2 =

Example 12 Using Boolean algebra simplify the following expression.

Solution

Example 13 Simplify the Boolean expression Solution Given the Boolean expression Exercise

(i) Simplify the following expression using De Morgan’s theorem and Boolean algebra laws and rulesa)b)c)

ASSINGMENT 3

(i) Prove the following Boolean identity (ii) Prove the following Boolean identity

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(iii) Prove the following identity (iv) Simplify the following Boolean expression

(v) Simplify the following expression and show the minimum gate implementation.

(vi) Simplify the following expression using De Morgan’s theorem and Boolean algebra laws and rulesa) b)c)

SIMPLIFICATION OF LOGIC CIRCUITS

Broadly there are two methods to simplify Boolean algebra:(i) Simplification using Boolean algebra and(ii) Simplification using Karnaugh maps.

(i) Simplification using Boolean algebra

This method is as had been explained earlier. Such a simplification leads to the simplification of logic circuit..

Example 14 Determine the Boolean expression for the output of the logic circuit shown below. Solution The Boolean expression for the output of the logic circuit is, Simplifying the expression, have

The simplified expression can be implemented as

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Example 15 Figure (a) below shows a logic circuit with the inputs A and B. The waveforms at the inputs are also shown in figure (b). Determine the minimized circuit and then sketch the waveform at the output.

Solution The output of the logic circuit is Applying the De Morgan’s theorem 1 to the terms on the right, have

The resulting waveform at Y is obtained by adding the waveforms at A and B and is as shown.

Example 16 Using Boolean algebra minimize the logic circuit shown below.

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Solution The output of the logic circuit is Applying De Morgan’s theorem 2 to the right side, have,

Hence, a minimized logic circuit has no logic gate. The output is equal to the value of A itself. In other words the given logic circuit is redundant.

Example 17 The circuit shown below is used to implement the function . What values should be selected for I and J.

Solution The above circuit is redrawn as shown below.

Since the output Y is given to be equal to , therefore, Comparing the terms on the left and right on the above equation, have that, …………………….……………(i) and ……………………………...(ii)

From equation (i), if then . Hence From equation (ii), ,

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Thus, and

Example 18 The figure below shows a combinational logic circuit. Obtain a simplified Boolean expression for this circuit at V, W, X, Y and Z in terms of input variables A, B and C.

SolutionThe logic circuit is redrawn and each is numbered as shown.

The output of gate 2 is Applying De Morgan’s theorem1, we get ……………………………….…………………..(i)The output of gate 3 is …………………………………………(ii)Substituting for V from (i) in equation (ii), we get …………………………………..…………………………………(iii)The output of gate 5 is ……………………………………………………………...……(iv)

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Substituting the value of V from equation (i) into equation (iv) we get ……………………………………...……………………..(v) The output of gate 6 is Substituting the value of V and W for equation (i) and (iii) we get ……………………………………………………………………..(vi)Finally, the output of gate 7 is ……………………………..………………………………….(vii)Substituting for X and Y from (v) and (vii), we get

STANDARD FORMS OF BOOLEAN EXPRESSIONS

Each Boolean expression can be converted into either of two forms: (i) Sum-of-Product (SOP) form or (ii) Product-of-Sum (POS) form

(i) Sum-of-Product (SOP) Form

In Boolean algebra, a product term (also called min-term) is the product of literals (or Boolean variables). In logic circuit circuits, a product term is produced by AND operation with no OR operation e.g. , , , .

A product term is equal to 1 if and only if each of the literals in the term is 1. Its equal to 0 when one or more of the literals are 0.

When two or more product terms are ORed, the resulting expression is called a Sum-of-Product (SOP) e.g. , , .

SOP expression can contain a single variable term but a single overbar cannot extend over more than one variable, although more than one variable in a term can have an overbar e.g. can be a term in SOP expression but not .

Domain of a Boolean expression

The domain of a Boolean expression is the set of variables contained in the expression in either complemented or uncomplemented form e.g. the domain of the expression is the set of variables, A, B and C. D.

Implementation of Sum-of-Products (SOP) Expression

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SOP expressions can be implemented by AND-OR logic. For example, implement the SOP expression .

NB: The no. of AND gates is equal to the number of terms in the sum-of-products expression.

Conversion of a General Expression to Sum-to-Products (SOP) Form Any logic expression can be converted to SOP using Boolean laws e.g.

Example 19: Convert the following Boolean expressions to SOP form.a)b)

Solution a)

b)

d) Standard Sum-of-Product Form

A standard SOP expression is one in which all the variables in the domain appear in each product term of the expression e.g. . If in any product term one of the literals is missing, then the expression is a non-standard SOP expression e.g.

Standard SOP expressions are very important in constructing the truth table or the K-map.

Conversion of Product term to a Standard Sum-of-Product (SOP) Form

The procedure is as follows:-(i) Identify the non-standard product terms in the given expression. Multiply each

such product term by a term made up of the sum of a missing variable and its complement

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(ii) Repeat step (i) until all resulting product terms contain all variables in the domain in either complemented or uncomplemented form.

Example 20 Convert the Boolean expression to standard SOP form.Solution

Example 21 Convert to a standard SOP form.Solution

(ii) The Product-of-Sums (POS) Form

In the Boolean algebra, a sum term (or max-term) is the sum of literals or variables e.g. , , etc.

A sum term is equal to 1 when one or more of the literals in the term are 1 and equal to 0 iff each of the literal is 0 e.g.

or

The Standard form of POS

A standard POS expression is one in which all the variables in the domain appear in each sum term of the expression e.g.

If one of the literals is missing in any max-term, then the expression is non-standard e.g.

Converting a Sum Term to a Standard Product-of-Sums (SOP) FormThe procedure is as follows:-

(i) Identity the non-standard sum term in the given expression. To each non-standard sum term, add a product term consisting of a missing variable and its compliment

(ii) Apply the following rule of algebra : (iii) Repeat step (i) until all sum terms contain all variables in the domain in

either complemented or uncomplemented form.

Example 22 Convert the following Boolean expression to its standard form

Solution Given

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Exercise Convert the Boolean expression

Converting Standard Sum-of-Product (SOP) to Standard Product-of-Sum (POS)

The procedure is as follows:-(i) Evaluate each product term in the SOP expression i.e. determine the

binary number which represents the product terms.(ii) Determine all the binary numbers not included in the evaluation in step (i)(iii) Write the equivalent sum term for each binary number from step (ii) and

express in POS form. NB: A similar procedure is used for the reverse.

Example 23 Convert the following Sum-of-Product (SOP) expression toan equivalent Product-of-Sums (POS) expression. Solution On evaluating each term have Since the possible combination is , then the remaining terms are those for POS i.e. 010, 100 and 110. Since these are binary values that make the sum term 0, therefore the equivalent POS expression is,

Convert SOP Expression to Truth Table FormatThe procedure is as follows:-(i) List all the possible combinations of binary values of the variables in the

given expression.(ii) Convert the SOP expression to standard form if it is not already so(iii) Place a 1 in the output column (Y) for each binary value that makes the

standard SOP expression a 1 and place a 0 for all the remaining values.

Example 24 Construct a truth table for the following expression:Solution On evaluating each term have

, hence the truth table becomes,

INPUTS OUTPUTSA B C Y0 0 0 00 0 1 10 1 0 00 1 1 01 0 0 11 0 1 0

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1 1 0 01 1 1 1

Example 25 Develop a truth table for the following Boolean expressions:

Solution Standardizing the expression we have,

(Some product terms are repeated and one of the repeated terms is retained while the rest are discarded). Thus, the required expression is, Its truth table is

INPUTS OUTPUTSA B C Y0 0 0 10 0 1 10 1 0 10 1 1 11 0 0 11 0 1 11 1 0 11 1 1 0

Converting Product-of-Sums (POS) Expression to a Truth Table Form

Since a POS expression is equal to 0 only if at least one of the sum terms is equal to 0, then the procedure is:

(i) List all the possible combinations of binary values of the variables(ii) Convert the POS expression to standard form if it is not already so.(iii) Place a 0 in the output (Y) for each binary value that makes the expression a 0

and place a 1 for all the remaining binary values.Example 26 Construct a truth table for a standard POS expression

Solution Given the expression , converting to binary equivalent have . Hence the truth table becomes,

INPUTS OUTPUTSA B C Y0 0 0 00 0 1 1

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0 1 0 10 1 1 01 0 0 11 0 1 11 1 0 01 1 1 1

Example 27 Develop the truth table for the following standard POS expression

Exercise (i) Find the canonical Sum-of-Products form for the expression given below (ii) Also find POS expression for the expression in (i).(iii) Determine the canonical POS form and canonical SOP form of the Boolean

expression (iv) Find the min terms or canonical SOP form and max terms or canonical POS

form for the function .(v) Find the max terms or canonical POS form of the function , which

is represented by the truth table

Decimal value A B C f(A,B,C)

0 0 0 0 01 0 0 1 12 0 1 0 13 0 1 1 04 1 0 0 15 1 0 1 06 1 1 0 07 1 1 1 1

(vi) Express as the sum of min terms and as the product of max terms.

The Karnaugh Map (K-Map)

Another method of minimizing expression is using a K-map. It provides a simple set procedure for minimizing the Boolean functions.

K-map is similar to a truth table in that it presents all the possible values of input variables and the resulting output of each value. But instead of being organized into columns and rows like a truth table, the K-map is an array of squares or cells in which each square represents a binary value of the input variables.

Each square is denoted by a binary number or its decimal equivalent e.g. if the function consists of three-variables, then the K-map has 8(23) squares and for four is 16 (24) squares. These maps are as shown below:-

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a) 2-variable K-map

b) 3-variable K-map

c) 4-variable K-map

Minimizing SOP Expression Using K-Map Any function to be minimized or to be reduced is first written in standard Sum-of-

Product form and its min-terms are then written. Each min-term is then converted to its equivalent binary number and a marking ‘1’ is made in the corresponding square in the map. This is referred to as mapping a SOP expression on the K-map.

Example 28 Map the following SOP expression on the K-map:

Solution

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Example 29 Map the following standard sum-of-products (SOP) expression on a K- map: Solution

Example 30 Map the following non-standard sum-of-products (SOP) expression on a K-map: Solution First the given expression is standardized as follows:- or or

After the Boolean expression has been mapped on the K-map, there are three

steps in the process of obtaining a minimum SOP expression.

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(i) Grouping the 1s – the adjacent 1s are grouped with the objective of maximizing the size of the groups and to minimize the number of groups using the following rules:-a) A group must contain either 1,2,4,8 or 16 squaresb) Each square in the group must be adjacent to one or more squares in that

same group but all squares in the same group do not have to be adjacent to each other.

c) Always include the largest possible number of 1s in accordance to rule (a).d) Each 1 on the K-map must be included in at least one group. The 1s already

in a group can be included in another group as long as the overlapping groups included non-common 1s.

(ii) Determining the Product term for each group – the minimum product term and hence the minimum sum-of-products expression is obtained using the following rule:a) Each group of squares containing 1s creates one product term composed of all

variables that occur in only one form within the group are eliminated. These are called contradictory variables.

(iii) Summing the resulting product terms – all the derived minimum product terms

are summed together to form the minimum sum-of-product expression.

Example 31 Simplify the following expression using a K-map:

Solution First the given is standardized i.e.

Next the standard SOP expression in mapped on to a K-map i.e.

Hence the simplified expression is,

Example 32 Simplify the following SOP expression using the K-map:

Solution

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The expression is already in standard form and therefore its mapped directly to the K-map.

Hence the simplified expression is,

Example 33 Simplify the following SOP expression using the K-map:

Solution First the given is standardized i.e.

Next the standard SOP expression in mapped on to a K-map i.e.

Hence the simplified expression is,

Mapping directly on K-map from a Truth Table A truth table representing an output of a Boolean expression can be mapped directly

on a K-map. To illustrate this, consider the truth table below.

INPUTS OUTPUTS

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A B C Y0 0 0 00 0 1 10 1 0 00 1 1 11 0 0 01 0 1 11 1 0 11 1 1 1

On mapping it becomes,

Example 34 Implement the following Boolean expression using minimum number of 3-input NAND gates.

Solution The expression above can be represented in form a truth table as,

Decimal number INPUTS OUTPUTSA B C D F

0 0 0 0 0 01 0 0 0 1 12 0 0 1 0 13 0 0 1 1 14 0 1 0 0 15 0 1 0 1 06 0 1 1 0 07 0 1 1 1 18 1 0 0 0 09 1 0 0 1 110 1 0 1 0 111 1 0 1 1 012 1 1 0 0 113 1 1 0 1 014 1 1 1 0 015 1 1 1 1 0

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Then the variables in the truth are mapped on a K-map as

Hence the resulting simplified expression is’

This can be implemented using 3-input NAND gates as shown below.

IMPLICANTS When a Boolean expression of four or less variables is represented on a K-map,

then the set of adjacent minterms or the simplified SOP term are called the implicants of the expression.

(i) Prime-implicant – An implicant is called prime-implicant of the expression if it is not a subset of any other implicant of the expression. Each product term individually is a prime-implicant.

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(ii) Essential prime-implicant – a prime-implicant which includes a ‘1’ cell, which is not included in any other prime-implicant, on the K-map, is known as an essential prime-implicant of the function.

From the above K-map, there are six prime-implicants I, II, III, IV, V and VI each

formed by a pair of two adjacent minterms. Prime-implicant I and VI are essential prime-implicants because one of their minterms is not included in any other prime-implicant.

From above K-map, no prime-implicant is essential thus it is called a cyclic-prime-implicant map. This is because each minterm is included in at least two implicants.

Example 34 (b): Find the set of prime-implicants and the minimum expressions of the expression below using s a K-map.

Solution:

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From the group of 8 cell pairs have a minterm of

From the group of 4 cell pairs have a minterm of .

Thus, the two mintems above are prime-implicants. Both are essential prime-implicants because prime-implicant contains some mintems i.e. which are not included in any other prime-implicant. Similarly the prime-implicant

contains some minterms i.e. which are not included in any other prime-implicant.

The minimum expression is

‘Don’t Care’ conditions In digital design sometimes a situation arises in which some input variable conditions

are not allowed e.g. in BCD code, there are six invalid combinations. Since these are unallowed states in BCD code, they can be taken as either 1 or 0. This is what is called don’t care condition.

These don’t care terms can be used to advantage on the K-map for simplification of logic equations. Consider a combinational circuit which produces a 1 output corresponding to a BCD input equal and greater than six. The output is 0 if the input is less than six. In form a truth table, it is as shown.

INPUTS OUTPUTSA B C D Y0 0 0 0 00 0 0 1 00 0 1 0 00 0 1 1 00 1 0 0 00 1 0 1 00 1 1 0 10 1 1 1 11 0 0 0 11 0 0 1 11 0 1 0 x1 0 1 1 x1 1 0 0 x1 1 0 1 x1 1 1 0 x1 1 1 1 x

Then this can be mapped on a K-map as,

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Hence the simplified expression is,

Example 35 Consider the K-map shown below. Determine the logic function represented by the map and simplify it in the minimal form.

Solution

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The resulting simplified function is,

Minimizing POS expression using a K-map

The POS expression is obtained from a K-map in the same manner as it is found from the truth table.

Example 36 Consider a Boolean function . The above SOP expression can be written in POS as,

Thus mapping it to a K-map, we obtained

Hence

Example 37 Obtain the minimal POS expression for the Boolean function given below using a four variable K-map.

Solution

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Hence

Example 38 Minimize the multiple-output Boolean function given below, using four-variable K-map.

Where the min-terms with x are don’t care conditions. Solution

Hence

ASSIGNMENT 4

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(i) Obtain the minimal SOP expression for the Boolean function given below using the K-map.

(ii) Express the Boolean function, in sum-of min-terms(iii) Find the set of prime-implicants from the function given below and obtain the

minimum expression/expressions using a K-map.

(iv) Express the Boolean function in product-of max-terms.(v) Express the Boolean function : in product-of-sums form(vi) Simplify the following Boolean functions using K-map:

a) b)

(vii) Given the logical function . Express it in the standard sum-of-products form.

PRACTICAL DESIGNS OF COMBINATIONAL CIRCUIT

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All arithmetic operations can be implemented using adders from basic logic gates. Some of these logic circuits are discussed below.

The Half-Adder The logic symbol of a half adder is as shown

Thus it accepts two inputs and produces two digits on the output: a sum bit (S) and a

carry bit (Cout). The truth table of a half-adder is

Inputs outputsA B S Cout

0 0 0 00 1 1 01 0 1 01 1 0 1

The Boolean expression for the sum output (S) can be expressed as ……………………………………………………….…………(1) And the Boolean expression for the carry output is …………………………………………………………………..(2) The two equations can be implemented using logic circuits as

The Full-Adder The logic symbol of a full-adder is as shown

A full-adder accepts three inputs (two-input A and B, and a carry input (Cin)) and two

outputs: a sum output (S) and a carry-output (Cout). The truth table of a full-adder is

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Inputs OutputsA B Cin S Cout

0 0 0 0 00 0 1 1 00` 1 0 1 00 1 1 0 11 0 0 1 01 0 1 0 11 1 0 0 11 1 1 1 1

The Boolean expression for the sum output as obtained from the truth table is ………………………………….…………(3) ……………………………..………………………..(4) Let , then equation (4) can be written as, ……………………………………..……………………………………(5) Replacing Y with , equation (5) can be written as ……………………………………………..……………………..(6)

The Boolean expression for the carry-output is as shown with three terms added since it has common factors with each of the other terms.

……………………………….…………………………..(7) Equation (6) and (7) can be implemented by using logic gates as

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A full-adder can also be implemented using two half-adders. For a full-adder, the two output equations are, and Hence the full-adder logic circuit using two half-adder is

Parallel Adders As shown above, a single full-adder can add two 1-bit numbers and an input carry.

Thus, to add binary numbers with more than one bit, parallel adders are used. To add two binary numbers, a full adder is required for each bit in the number. Thus, for two-bit numbers, two full-adders are used. Similarly, four full adders are required to add four-bit numbers.

A block diagram of a basic 2-bit parallel adder using two full-adders is as shown.

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Similarly, a 4-bit parallel adder can be constructed using four full adders in parallel as

shown.

DECODERS A decoder is used to decode the binary information in a digital system by changing it

into some other type of number system, preferably decimal or hexadecimal number system. It converts an n-bit binary input code into a maximum of unique output lines.

A 3 to 8 line decoder is as shown. A practical application of this decoder is binary to octal conversion. The input

variables will represent three binary digit number and output will represent the eight digits in the octal number systems.

ENCODERS This is just the reverse of decoding. It has or less input lines and output lines. For example an octal to binary encoder is as shown below.

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MULTIPLEXERS (MUX) It is also known as data selector. It accepts several data inputs and selects only one of

them at a time and directs it to a single output line. A 4 line to 1 multiplexer is as shown below.

The logic symbol and truth table of this MUX are

0 0

0 1

1 0

1 1

Exercise:With the aid of truth tables, draw the logic circuits of the following Multiplexersa) 2 to 1 MUXb) 8 to 1 MUX

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DEMULTIPLEXER [DEMUX] It is also known as data distributor. It does the reverse of the multiplexer i.e. it takes in

a single input and distributes over several outputs. The select inputs will determine or decide, to which output the data input will be transmitted.

For example, a 1 to 4 line demultiplexer with it truth table is as shown below.

Inputs OutputsData inputs

I 0 0 0 0 0 1I 0 1 0 0 1 0I 1 0 0 1 0 0I 1 1 1 0 0 0

Exercise:With the aid of truth tables, draw the logic circuits of the following Multiplexersc) 1 to 2 DEMUXd) 1 to 8 DEMUX

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ELEMENTS OF SEQUENTIAL LOGIC CIRCUITS

Introduction Unlike combinational logic circuits, sequential logic circuits have memory elements

which store the previous output information of the circuit to be used as feedback. A block diagram of a sequential logic circuit is as shown.

The storage elements are devices capable of storing binary information. The binary information stored in these elements at any given time defines the state of the sequential circuit at that time.

The sequential circuits receive binary information from external inputs. These inputs, together with the present state of the storage elements, determine the binary of value of outputs. They also determine the condition for changing the state in the storage elements. Thus a sequential circuit is specified by a time sequence of inputs, outputs, and internal states.

The differences between combinational and sequential circuits are as shown in the table.

Combinational Circuit Sequential CircuitIts output at any instant of time depends on input applied simultaneously at that time.

Its output depends on the present inputs and previous history of inputs

It contains no memory elements It contains at least one memory elements.

It can be totally described by the set of output values only.

It s performance is totally described by the set of subsequent state values as well as set of output values.

It is easy to design, due to absence of memory

It is difficult to design due to presence of memory.

Faster in speed because all inputs are primary inputs applied simultaneously.

Comparatively slower in speed because it has secondary inputs also, which are applied after a delay.

It needs more hardware for its realization. It needs less hardware for its realizationIt is expensive in cost. It is cheaper in cost.

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FLIP-FLOP (FF) A general symbol for a flip-flop is as shown.

It has two outputs labeled as Q and that are inverse (or complement) of each

other. When a reference of the state of the flip-flop is made, its usually referring to the state of its normal (Q) output. There are two operating states of the flip-flop. One is when which is called HIGH state or 1 state or SET state. The other is when which is called LOW state or 0 state or RESET state.

The flip-flop can have one or more inputs as shown in the block diagram. A flip-flop is also called a latch or bistable multivibrator.

Latch It’s the most basic type of flip-flop circuit. When a flip-flop operated without the

clock, it’s referred to as a latch. There are two types of latches depending on whether a NAND or a NOR gate is

used to construct it.

NAND gate Latch Its construction is as shown

Operation: Normally, the SET and CLEAR inputs of the latch are resting in the HIGH state. If the output needs to be changed, one of the inputs is changed to LOW. For example, when SET = CLEAR = 1, there are two possible output states. If

and , the inputs of NAND-2 are 0 and 1, which produces . The 1 from causes NAND-1 to have 1 at both inputs to produce a 0 at .The second case is when and . This shows that the HIGH from NAND-1 produces a LOW at the NAND-2 output, which in turn keeps the NAND-1 output HIGH.

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Thus, as long as SET = CLEAR = 1, the output and . If CLEAR=0 AND SET= 1 and the outputs are and , then keeps

NAND-2 output HIGH with the LOW at CLEAR having no effect. If CLEAR = 1, the latch outputs still remains and .

This can be summarized in a truth table below:

Inputs OutputsSET CLEAR

1 1 No change0 11 00 0 (invalid)

NOR gate Latch Its construction is as shown.

Operation It operation is similar to the NAND gate latch but the SET and CLEAR inputs are

active-HIGH rather than active-LOW. The results are given in the truth table below.

Inputs OutputsSET CLEAR

0 0 No change1 00 11 1 invalid

(i) SET = CLEAR = 0: This condition is the normal resting state for the NOR latch. It has no effect on the output state. In other words, andwill remain in the same state in which they were prior to this input condition.

(ii) SET = 1, CLEAR = 0: This condition always causes the output to go to state where it will remain even after SET returns to 0.

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(iii) SET = 0, CLEAR = 1: This condition will always causes the output to go to state where it will remain even after CLEAR returns to 0.

(iv) SET = 1, CLEAR = 1: This condition tries to set and clear the latch simultaneously. It produces invalid results and should not be used.

CLOCKED SIGNALSDigital systems are of two types:(i) Asynchronous systems: in these systems, the outputs of logic circuits can

change state any time one or more of the inputs change. They are generally more difficult to design and troubleshoot than a synchronous.

(ii) Synchronous systems: In these systems, the exact time at which the output can change states are determined by a signal commonly called a clock.

Clocked signal is generally a rectangular pulse train as shown in the figure below.

A square wave can also be used as clock signal as shown.

The synchronization in a digital system is accomplished through the use of

clocked flip-flops that are designed to change states on one or the other of the clock’s transitions

Clocked flip-flops have a clock input that is labeled as CLK, CK or CP. But CLK is commonly used. The CLK can either be edge triggered or level-triggered. Edge triggered means the CLK is activated by a signal transition and is indicated by the presence of a small triangle on the CLK input. The triggering transition can either be the rising or the falling edge. The two cases are represented in a block diagram form as shown.

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CLOCKED S-R FLIP-FLOP The logic symbol and truth table of an S-R flip-flop are as shown below:

INPUTS OUTPUTS R Q0 0 Q0 (no change)1 0 10 1 01 1 Invalid

(b) Truth table Figure (b) shows the truth table for a clocked S-R flip that is triggered by the

rising edge of the clock signal. Its operation can easily understood with the help of input and output waveforms as shown.

Note that the flip-flop is not affected by the falling edge of the clock pulses. It may also be noted that S and R input levels have no affect on the flip-flop except upon the occurrence of a rising edge of the clock signal.

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S-R Logic gate implementation Below is a simplified version of a internal circuitry of an edge-triggered S-R flip-

flop. The circuit contains three sections:(i) A basic NOR latch(ii) A pulse steering circuit and (iii) An edge-detector circuit

CLOCKED J-K FLIP-FLOP The logic symbol and truth table of J-K flip-flop are as shown below:

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INPUTS OUTPUTJ K Q0 0 Q0 (no change)1 0 10 1 01 1 Q0 (toggles)

(b) Truth table Its operation can easily understood with the help of input and output waveforms

as shown

Initially all the inputs are 0, and the Q output is also assumed to be 0, i.e. When the rising edge of the first clock pulse occurs, condition exists.

Thus the flip-flop does not change its output state, i.e. . When the rising edge of the second clock pulse occurs, condition exists.

Thus the flip-flop toggles to its opposite state i.e. . When the rising edge of the third clock pulse occurs, condition

exists. Thus the flip-flop is cleared to the state.

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When the rising edge of the fourth clock pulse occurs, condition exists. This condition sets the output Q to 1 state.

When the rising edge of fifth pulse occurs, condition exists. This is the condition that sets the output Q to 1. However since Q is already 1, so it will remain there. Hence no change in the output state.

When the rising edge of sixth pulse occurs, condition exists. This is the condition causes the flip-flop to toggle to its opposite state.

When the rising edge of seventh pulse occurs, condition exists. This is the condition causes the clear to state.

J-K Logic gate implementation Below is a simplified version of a internal circuitry of an edge-triggered S-R flip-

flop. The circuit contains three sections:(i) A basic NOR latch(ii) A pulse steering circuit and (iii) An edge-detector circuit

(iv) The only difference between the internal circuitry of edge-triggered J-K flip-flop and S-R flip-flop is that in J-K, outputs are fed back to the pulse –steering NOR gates.

(v) It is because of this feedback connection that J-K flip-flop gives the toggle operation for condition.

THE J-K MASTER-SLAVE FLIP-FLOP

All the sequential circuits that we have been covered so far have problem (All the level sensitive sequential circuits have this problem). Before the enable input changes state from HIGH to LOW, if inputs changes, then another state transition occurs for the same enable pulse. This sort of multiple transition problem is called racing. We can overcome this problem using a two stage J-K flip-flop as shown in the block diagram below.

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In the figure above there are two latches, the first latch on RHS is called master

latch and the one on LHS is called slave latch. Master latch is positively clocked and slave latch is negatively clock.

The internal logic circuit of the master-slave J-K flip-flop is as shown below. During the posive edge of the clock signal, the inputs are first passed on to the

master flip-flop while the the slave flip-flop is disabled. During the the negative edge of the clock siganal, the master flip-flop is disabled while the slave is enabled. Hence the output of the master flip-flop becomes the inputs of the slave flip-flop and are passed as the output and .

CLOCKED D FLIP-FLOP The logic symbol and truth table of J-K flip-flop are as shown below:

Inputs outputD Q0 Q

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1 1 (b) Truth table The output Q will go to the same logic level as the present logic level of D input

when the rising edge occurs at the CLK. In other words, the level present at D will be stored in the flip-flop at the instant the rising edge occurs.

Consider the waveforms below:

An implementation of D flip-flop using J-K flip-flop is as shown below.

D-LATCH

The logic symbol of a D-latch is as shown below:

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Its logic gate implementation is also as shown below. It consists of two NOR gates connected as shown with complement inputs. Its truth table is similar to that of a D flip-flop with the exception that in the later, the inputs are controlled by a clock signal while in this case the input are not controlled. As the inputs are fed to the gates, they are manipulated by the gates based on the present levels of the outputs and a next output is produced. For such a logic circuit, its sometimes difficult to predict the output of latch.

T FLIP-FLOP

This flip-flop is also called a Toggle flip-flop since its outputs toggles continuously based on the clocked changes its value. It based on the characteristic of a J-K flip-flop when both its inputs are at logic level 1.

It logic symbol is as shown:

The logic gate implementation of this flip-flop look like this:-

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The output of the circuit toggles or changes its state from low to high or from high to low depending on the previous state of the output at very instant of positive going edge of the clock signal. Hence it truth table is as shown below

Inputs outputT Q0 Q1 1

Consider the waves below:-

Based on the truth table of a T flip-flop, its Q output is as shown.

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