Crosstalk Minimization in Logic Synthesis for...

Crosstalk Minimization in Logic Synthesisfor PLAs

YI-YU LIU

National Tsing Hua University

KUO-HUA WANG

Fu Jen Catholic University

and

TINGTING HWANG

National Tsing Hua University

We propose a maximum crosstalk effect minimization algorithm that takes logic synthesis intoconsideration for PLA structures. To minimize the crosstalk effect, a technique for permuting wireis used which contains the following steps. First, product terms are partitioned into long and shortsets, and then the product terms in the long and short sets are interleaved. After that, we take ad-vantage of the crosstalk immunity of product terms in the long set to further reduce the maximumcoupling capacitance of the PLA. Finally, synthesis techniques such as local and global transfor-mations are taken into consideration to search for a better result. The experiments demonstratethat our algorithm can effectively minimize the maximum coupling capacitance of a circuit by 51%as compared with the original area-minimized PLA without crosstalk effect minimization.

Categories and Subject Descriptors: B.4.4 [Input/Output and Data Communications]: Perfor-mance Analysis and Design Aids—Worst-case analysis; B.6.1 [Logic Design]: Design Styles—Combinational logic; B.7.1 [Integrated Circuits]: Types and Design Styles—VLSI (very largescale integration)

General Terms: Algorithms, Performance

Additional Key Words and Phrases: Crosstalk, PLA, synthesis, domino logic

1. INTRODUCTION

Coupling capacitance grows reciprocally to the square of the scaling fac-tor. In deep submicron (DSM) technology, exponential growth occurs due

This work is supported in part by NSC Grant No. 94-2220-E-007-040.Authors’ addresses: Y.-Y. Liu, Department of Computer Science and Engineering, Yuan Ze Univer-sity, 135, Far East Rd, Chungli, Taoyuan, Taiwan 320, R.O.C.; email: [email protected]; T.Hwang, Department of Computer Science, National Tsing Hua University, 101, Section 2 KuangFu Road, Hsinchu, Taiwan 300, R.O.C.; K.-H. Wang, Department of Computer Science and Infor-mation Engineering, Fu Jen Catholic University, 510 Chung Cheng Road, Hsingchuang, TaipeiCounty, 24205 Taiwan, R.O.C.Permission to make digital or hard copies of part or all of this work for personal or classroom use isgranted without fee provided that copies are not made or distributed for profit or direct commercialadvantage and that copies show this notice on the first page or initial screen of a display alongwith the full citation. Copyrights for components of this work owned by others than ACM must behonored. Abstracting with credit is permitted. To copy otherwise, to republish, to post on servers,to redistribute to lists, or to use any component of this work in other works requires prior specificpermission and/or a fee. Permissions may be requested from Publications Dept., ACM, Inc., 2 PennPlaza, Suite 701, New York, NY 10121-0701 USA, fax +1 (212) 869-0481, or [email protected]© 2006 ACM 1084-4309/06/1000-0890 $5.00

ACM Transactions on Design Automation of Electronic Systems, Vol. 11, No. 4, October 2006, Pages 890–915.

Crosstalk Minimization in Logic Synthesis for PLAs • 891

to exponential down-scaling. The crosstalk effect of down-scaling results inmore power consumption and unpredictable timing [Shepard and Narayanan1996]. Therefore, crosstalk minimization is currently an important issue[Vittal and Marek-Sadowska 1997; Jiang et al. 2000; Kim et al. 2000; Tienet al. 2002]. There are two approaches to minimizing the crosstalk effect forDSM technology: minimization of total crosstalk and minimization of maxi-mum crosstalk. For low-power-driven designs, research focuses on minimizingthe total crosstalk [Vittal and Marek-Sadowska 1997; Kim et al. 2000; Tienet al. 2002], while for performance-driven designs, research emphasizes min-imizing the slowest switching time, taking switching directions and couplingcapacitance of neighboring wires into considerations. [Tseng et al. 1998; Zhaoand Wong 1999; Duan and Khatri 2004].

In a dynamic programmable logic array (Dynamic PLA), a well-developedstructure using NOR-NOR implementation architecture is divided into twoplanes: the AND plane and OR plane [Blair 1992; Dhong and Tsang 1992;Khatri et al. 1999; Wang et al. 1999, 2001; Mo and Brayton 2002]. In the ANDplane, inputs are computed to form product terms, whereas in the OR plane,product terms are summed to generate outputs. Due to its regular layout, it ismuch easier to estimate the area and delay for a PLA than for cell-based or fullcustom design. This characteristic makes the PLA an attractive alternative toimplementing logic in the DSM era. For example, taking advantage of its pre-dictable delay, Khatri et al. [1999] proposed a unique design methodology forDSM technology by utilizing PLA structure.

Using current computer-aided design tools, a parameterized PLA, unlikeconventional off-the-shelf PLA, can be synthesized as a customized layout fab-rication during the design process [Posluszny et al. 1998; Mo and Brayton 2002;Tien 2003]. In this work, we will study synthesizing a parameterized PLA byan in-house PLA layout compiler, the PLACompiler [Tien 2003].

One disadvantage of domino circuits is that they are very sensitive to noisesources such as leakage, charge sharing, and capacitive coupling. There aredifferent tactics for solving each of these problems. For example, keeper logicprovides weak feedback to hold the state for leakage problems, and secondaryprecharge devices are useful for alleviating charge sharing problems. However,neither is capable of solving capacitive coupling problems. It is generally ac-cepted that the most effective way to solve the crosstalk problem on dominocircuits is by wire spacing and shielding [Khatri et al. 1999, 2000; Harris andGrutkowski 2004]. However, this technique may cause area overhead. Hence,when synthesizing a minimum area overhead PLA, taking crosstalk effect intoconsideration is important. One work addressing this topic is presented in Tienet al. [2002], where the authors propose a PLA product-term ordering algo-rithm to maximize the crosstalk immunity (CT-immune) for total overlappingwire length minimization. The crosstalk effect between adjacent CT-immuneproduct terms can be ignored if they drive the same outputs.

In this work, we will study performance optimization while taking thecrosstalk effect into consideration for domino PLA logic. In domino PLA logic,the product wires always switch either in the same direction or not at all.Therefore, an upper bound on the worst-case switching condition of a victim

ACM Transactions on Design Automation of Electronic Systems, Vol. 11, No. 4, October 2006.

892 • Y.-Y. Liu et al.

Table I. Timing Simulation on Dynamic PLA with Different Product Wire Orderings

Circuit Method P TAND TOR Max Delay (ps) RDelay (%)Original order 68 594 135 20 419.0 100.0

alu2 Min total order 68 150 43 19 414.7 99.0Min max order 68 181 68 11 407.9 97.3

wire is that of assuming that neighboring wires do not make transitions. Inthis case, performance is controlled by the total capacitance of the victim wireto be switched. Our metric for optimization is selected to minimize the maxi-mum overlapping wire length, rather than the total overlapping wire length,since coupling capacitance decreases quadratically as the distances betweenthe two wires increases. On the other hand, the metric of total overlappingwire length will result in the same weighting factor being given to all wires.

To understand that this observation is correct, we perform a set of experi-ments on the relationship between overlapping wire length and circuit delay. Acircuit, alu2, is taken from the MCNC benchmark set as a test example. Threeproduct-term orderings are generated. First, the circuit is area-optimized byEspresso and the product-term wires are ordered following output file ordering[Micheli 1994]. Next, the product terms are ordered to minimize the total over-lapping wire length [Tien et al. 2002]. Finally, the product terms are orderedso as to minimize the maximum overlapping wire length, using the algorithmdescribed in this work. For these three product-term orderings, we use PLA-Compiler together with Virtuoso [Cadence 1999] to generate the layout of eachPLA. Based on the TSMC SPICE MODEL for 0.18 μm mixed signal SALICIDE(1P6M, 1.8V) process technology, timing simulation results are produced byHspice [Synopsis 2001]. The input vector is selected to produce a transitionon a victim wire with the maximum coupling capacitance of the circuit andno transitions on its two neighboring wires. Table I shows the results. In thistable, Original order, Min total order, and Min max order are the results fororiginal ordering, minimizing the total overlapping wire length, and minimiz-ing the maximum overlapping wire length, respectively. Column P representsthe number of product terms. Columns TAND and TOR are the total overlappingwire lengths in the AND plane and OR plane, respectively. Column Max is themaximum overlapping wire length among product wires in the AND plane andOR plane of the PLA. Columns Delay and RDelay are the delay time and de-lay ratio, respectively. From this table, we see that the best delay is the designMin max order where the maximum overlapping wire length is minimized. Thedesign Min total order that produced the least total overlapping wire length hasonly a 1 % delay improvement over the original ordering.

The second experiment is to verify whether the crosstalk effect will causeincorrect results due to discharging of the wire as the process technology ad-vances to deep submicron. The experiment is conducted using a more advancedtechnology. For the design, 0.07 μm technology parameters from the berkeleypredictive technology model (BPTM) [UCB Device Group 2002] are used. Inthis design, there are three product-term wires, and the middle one is a victimwire. A simulation using Hspice is performed. Figure 1 shows the result. Inthis figure, the clock signal is drawn in dotted lines, the middle product-term



Fig. 1. SPICE simulation for dynamic PLA using 0.07 μm process technology.

signal is drawn in dashed lines, and the output signal driven by the victimproduct-term is drawn in solid lines. In this predictive simulation model, thevictim signal stays unchanged and suffers from crosstalk coupling from onlyone of its neighbors between 1 ns and 2 ns (only one neighbor has a transition),and the output signal remains correct in clock cycle one. However, when thevictim signal suffers from crosstalk coupling from both neighbors between 3 nsand 4 ns, the output signal is pulled down and results in an incorrect transitionin clock cycle two.

Therefore, to alleviate timing uncertainty and prevent a circuit from mal-functioning due to crosstalk effects, we should consider minimizing the maxi-mum coupling capacitance of a circuit so as to improve signal integrity. To thisend, the technique of permuting product terms is used, which contains the fol-lowing steps. First, product terms are partitioned into long and short sets, andthen the product terms in these two sets are interleaved. After this, we takeadvantage of the crosstalk immunity of product terms in the long set to furtherreduce the maximum coupling capacitance of the PLA. Finally, synthesis tech-niques, such as local transformation and global transformation, are taken intoconsideration to search for a better result.

The rest of the article is organized as follows. Preliminary background andmotivation for this work are given in Section 2. Our algorithm flow for crosstalkeffect minimization is presented in Section 3. Section 4 presents long set and



Fig. 2. Dynamic PLA schematic view.

short set operations for minimizing the maximum coupling capacitance. Twologic-level transformations to find a better result are proposed in Section 5. Ourexperimental results are shown in Section 6. Section 7 concludes this work.

2. MOTIVATION

2.1 PLA Crosstalk Formulation

The coupling effect between two parallel wires is derived as follows [Sakuraiand Tamaru 1983]:

coupling effect ∝ overlapping length

wire distance2, (1)

where overlapping length and wire distance are the overlapping wire lengthand vertical distance, respectively, between two wires. From Eq. (1), it is ob-served that the coupling effect decreases quadratically with an increase of wiredistance between two neighboring wires. Therefore, we will consider the cou-pling effect between two neighboring wires.

A schematic view of a dynamic PLA core is shown in Figure 2 [Blair 1992],where O1 = (AB + AB)′, O2 = (B + AB)′, and the signal wires {A, A, B, B},{P1, P2, P3, P4}, and {O1, O2} represent input signals, product-term signals, andoutput signals, respectively. Notice that the performance in the AND plane iscontrolled by the size of the PMOS transistor pulling the product-term wireup, whereas the speed of the OR plane is controlled by the size of an NMOStransistor pulling down an output wire. To compute the crosstalk effect of thePLA, the I/O column wires and product-term wires need to be taken into ac-count. However, because I/O columns are interleaved with ground wires, whichprovide good shielding for crosstalk prevention, the crosstalk effect among I/Ocolumns can be ignored. For the product-term wires, the crosstalk effect is a se-rious problem due to the monotonic phase transition property of dynamic PLAs.During the precharge stage, output wires are charged to high, while productterms are discharged to low [Blair 1992; Dhong and Tsang 1992]. Then, during



the evaluation stage, if a victim product term evaluates from low to high and itsneighboring wires stay at no transition, the coupling capacitance of the victimproduct term will incur the timing delay of the circuit.

To estimate the crosstalk effect of domino cells, self-crosstalk effects andcoupling crosstalk effects need to be considered. Fringe capacitance, gate ca-pacitance, and source/drain capacitance contribute to the self-crosstalk effect.Fringe capacitance is the capacitance between the edge of product-term wireand the metal layer. Fringe capacitance is proportional to product-term wirelength. Gate capacitance is the gate-oxide capacitance at the end of the product-term wire. The gate capacitance has the same value for all product-term wires.Source/drain capacitance is proportional to the number of NMOS transistorsthat engage in the product-term wire. We can formulate the crosstalk effect ofeach product-term wire as follows:

crosstalk effect = α · coupling effect + β · fringe capacitance + γ · # NMOS . (2)

Since fringe capacitance and source/drain capacitance are two orders of mag-nitude smaller than the coupling effect, they are negligible in modern DSMfabric technology as compared to the coupling effect [Khatri et al. 2001; Leeet al. 2002]. Thus, the last two terms will be omitted in the capacitance compu-tation.

In this work, we will focus on minimizing the maximum coupling capacitancefor performance optimization between neighboring product-term wires. Sincethere are inter-buffers between the AND and OR planes, the crosstalk effect willnot be propagated from the AND to the OR plane. The crosstalk effects of thetwo planes are computed separately. The overlapping length of two neighboringwires is computed by the number of columns crossed by the two product-termwires. Figure 3 gives an example of computing the maximum overlapping wirelength. The overlapping wire length between two adjacent product terms P1and P2 is 〈P1, P2〉 = (7, 1), where 7 is the overlapping wire length in the ANDplane and 1 in the OR plane. Similarly, overlapping lengths of 〈P2, P3〉 = (5,1), 〈P3, P4〉 = (2, 3), 〈P4, P5〉 = (2, 2), and 〈P5, P6〉 = (6, 2). It can be seen thatthe overlapping of P1 and P2 in the AND plane results in 7, the maximumoverlapping wire length.

2.2 Motivation Example

The overlapping wire length of a dynamic PLA will be less if we utilize the per-mutation of wires and synthesis of different covers of the function. An examplethat illustrates how the wire permutation and synthesis affect overlapping wirelength is shown in the following.

Given a five-input five-output Boolean network, the logic optimization toolEspresso is used to obtain a minimal cover C1:

C1 =

⎧⎪⎪⎪⎪⎨⎪⎪⎪⎪⎩

O1 = P2 + P3 + P5O2 = P5 + P6O3 = P1 + P3O4 = P1O5 = P1 + P4 + P6

,



Fig. 3. Overlapping wire length of minimal cover C1.

Fig. 4. Overlapping wire length of minimal cover C1 after wire permutation.

where C1 has 6 product terms, P1 = I2 I4 I5, P2 = I2 I3 I5, P3 = I3 I4 I5, P4 =I5, P5 = I1, and P6 = I3. If the PLA is synthesized without I/O or product-termpermutation, the maximum overlapping wire length is 7, as shown in Figure 3.On the other hand, if the I/O and product wires are permuted, the resultant PLAis shown in Figure 4, where the maximum overlapping wire length becomes 6.Furthermore, if the function is resynthesized to a different cover, C2:

C2 =

⎧⎪⎪⎪⎪⎨⎪⎪⎪⎪⎩

O1 = P1 + P2 + P3O2 = P2 + P3 + P5O3 = P1 + P4O4 = P4O5 = P1 + P4 + P5 + P6

,

where C2 also has 6 product terms, then P1 = I3 I4 I5, P2 = I1 I2 I3 I5, P3 =I1, P4 = I2 I4 I5, P5 = I3, and P6 = I3 I5, as shown in Figure 5. The resultant



Fig. 5. New cover C2.

Fig. 6. Overlapping wire length of C2 after wire permutation.

PLA with the cover C2 after I/O and product-term permutations are performedis shown in Figure 6. In this case, the number of product terms remains thesame, but the maximum overlapping wire length is reduced from 6 to 4.

This example demonstrates that a minimal cover does not guarantee the goalof a dynamic PLA with minimum overlapping wire length. To reach this goal,both an algorithm to permute I/O and product-term wires, and a synthesis ofdifferent covers must be considered.

3. FLOW CHART OF CROSSTALK MINIMIZATION ALGORITHM

The flow chart of our algorithm is depicted in Figure 7. First, we useEspresso to generate a minimized PLA. Then, the step of PLA crosstalkminimization is performed to minimize maximum overlapping wire lengthof the given cover. After this, local transformation is introduced to finetune the cover and further reduce the overlapping wire length. Then,



Fig. 7. Flow chart of the algorithm.

the shortest maximum overlapping wire length computed in this itera-tion is compared with the best shortest overlapping wire length computedthus far. If the result produced in the current iteration is shorter, thebest shortest overlapping wire length is updated. To prevent the synthesis re-sult from being trapped in a local optimal, the step of global transformation isapplied repeatedly to synthesize different covers, according to the output groupinformation in the OGG (output grouping graph). These covers are the newinitials for PLA crosstalk minimization and local transformation to start with.The loop repeats until the number of vertices in OGG becomes 1, which corre-sponds to the original PLA synthesis result. In this process, the PLA crosstalkminimization step proposes techniques to permute input/output and product-term orderings, and the global transformation and local transformation stepspropose resynthesis techniques.

4. PLA CROSSTALK MINIMIZATION

For a given cover, the PLA crosstalk minimization step permutes the order of in-put/output and product-term wires so as to reduce the overlapping wire lengthof two adjacent product terms. The overlapping wire length of two adjacentproduct terms is determined by both the product terms and I/O orderings. Astraightforward enumeration is to permute all I/O and product-term orderings.Obviously, this is not feasible for a large sized PLA. We propose a four-stepalgorithm to find a solution. First, an initial input (or output) ordering is se-lected. Then, based on the I/O ordering found in the first step, the product-terminterleaving is performed. After this, product-term grouping is used to fur-ther reduce the overlapping wire length. Finally, with the fixed product-term



Fig. 8. The PLA crosstalk minimization procedure.

ordering, we reorder the input and output ordering to achieve a shorter over-lapp. Figure 8 shows the steps of PLA crosstalk minimization.

4.1 Initial I/O Ordering

Since the crosstalk effect will not propagate from the AND plane to the OR planedue to the insertion of inter-buffers between the two planes, we will considerthe crosstalk effect of the two planes separately. The overlapping wire length ofproduct terms is determined by the orderings of input and product-term wiresin the AND plane, and by the orderings of output and product-term wires in theOR plane. To minimize the maximum overlapping wire length, we will optimizethe larger plane first. Here, the size of the AND plane is defined as double thenumber of inputs, and the size of the OR plane as the number of outputs. Hence,the first step of initial I/O ordering is to select the larger plane.

Then, the columns of the selected plane are ordered. The column order isdetermined by the number of product terms it engages, that is, the number ofdots in each column. Columns with more dots are placed inward [Tien et al.2002]. The reason behind this heuristic is that the dots at two end-points ofa product term determine the wire length of this product-term wire. Orderingcolumns with fewer dots at two end-points will reduce the number of productterms with long wire lengths. In Figure 5, there are 10 columns in the ANDplane and 5 in the OR plane. Therefore, the ordering of inputs in the ANDplane is determined. Since I3 and I5 have the greatest numbers of dots (4), theyare put in the rightmost columns (next to the inter-buffer). Figure 9 shows theresultant PLA after the step of I/O ordering is performed.

4.2 Long Set and Short Set Interleaving

Based on the initial input (or output) ordering of the selected plane computedin the previous step, we permute the product-term wires. First, we computethe length of each product term, which is the distance between the outermostdot and the inter-buffer. Notice that only wire lengths in the selected plane aretaken into account.

Second, based on the lengths of the product terms in the selected plane, wepartition them into two sets: a long set, long, and a short set, short. The first � N

2 �longest product terms belong to long, and the remaining N

2 product terms areassigned to short. Finally, we interleave the product terms in long and productterms in short. For example, assume long ={l1, l2, l3, . . . } and short = {s1, s2,s3, . . . }. The product-term ordering will be l1, s1, l2, s2, l3, s3, . . . , etc. Figure 10



Fig. 9. Example of I/O ordering.

Fig. 10. Example of long and short interleaving.

shows the resultant PLA after interleaving the product terms in long and shorton the PLA shown in Figure 9.

We can prove that the resultant overlapping wire length of the PLA is optimalby the step of long set and short set interleaving.

LEMMA 4.1. The maximum overlapping wire length in the selected plane isthe longest product-term wire length in the short set after performing short setand long set interleaving.

PROOF. Assume that there are n product-term wires in the PLA. The first� N

2 � longest product terms belong to long, and the remaining N2 product terms

are assigned to short. Suppose the wire length of the product term si in shortis |si| and the wire length of the product term l j in long is |l j |. It can be easilyseen that |si| ≤ |l j | for all si in short and all l j in long. After performing shortset and long set interleaving, there exist no two product-term wires in long



that are adjacent to each other. Each product-term wire in long is adjacentto a product-term wire in short. Since in both the AND plane and OR plane,one end-point of each product-term wire always starts from the inter-buffer, theoverlapping wire length of adjacent product terms si and l j is determined by thelength of the product term in short, OL(si, l j ) = |si|. Therefore, the maximumoverlapping wire length of the PLA is the longest product-term wire length inthe short set.

THEOREM 4.2. The maximum overlapping wire length obtained by short setand long set interleaving is the minimum in the selected plane.

PROOF. Suppose smax is the longest product-term wire in short. Assume thatthere exists another product-term ordering that produces an overlapping wirelength shorter than |smax|. Then, the product-term wire smax must be adjacent toa shorter product-term wire x, and the overlapping wire length is |x|. Since smax

is the longest product-term wire in short, the shorter product-term wire x mustalso be in short. It can be easily seen that there must exist two product terms la

and lb in long that are adjacent to each other. In this case, the maximum over-lapping wire length of the PLA for this new ordering is determined by the wirelength of la either or lb, both of which are longer than |smax|. This contradicts theassumption that the new product-term ordering obtains an overlapping wirelength shorter than |smax|. Therefore, we prove that the maximum overlappingwire length obtained by short set and long set interleaving is minimized in theselected plane.

4.3 Grouping in Long Set

Crosstalk immunity between two wires is discussed in Tien et al. [2002]. Thebasic idea of crosstalk immunity is as follows. Assume that there are two adja-cent product terms driving the same outputs. One product term is an aggressorand the other is a victim. Let the aggressor evaluate from low-to-high, while thevictim remains low. Assume that crosstalk noise propagates to the victim andcauses a transient high signal on the victim wire. The transient signal of thevictim will be harmless to the output result because the output wires are to bedischarged by the aggressor. Hence, the crosstalk effect between two adjacentproduct terms can be ignored if their output parts are the same.

We can utilize the crosstalk immunity property to further reduce the over-lapping wire length of a dynamic PLA. First, for a given product term in long,we group all of the other products in long that drive the same output signalswith this product term to form a super-product-term set. The product terms in asuper-product-term will be viewed as a single product term. Then, we move theproduct terms in short to long such that the sizes of the two sets are balanced.Note that we do not consider all the product terms for grouping, as does Tienet al. [2002]. Instead, we only group these product terms in long. As a result,the grouping process can reduce the longest product-term wire length in short,that is, the maximum overlapping wire length of the PLA.

For example, given a PLA with N product terms, there are � N2 � product terms

in long and N2 product terms in short. If m product terms can be grouped into

a super-product-term in long, the number of product terms in long will become



Fig. 11. Example of long set grouping.

� N2 � − m + 1. Since the number of product terms in long is reduced, we balance

the sizes of long and short by moving the first m2 longest product terms from

short to long. As a result, the longest wire length of the product terms in shortis reduced. This grouping process repeats until no product terms in long can befurther grouped.

Taking the PLA shown in Figure 10 as an example, we demonstrate how toperform the grouping in long. Initially, long = {P2, P3, P4} and short = {P6, P5,P1}. Since P2 and P3 drive the same outputs, they form a super-product-term.To balance the sizes of the two sets, P1, the longest product term in short, ismoved to long. We can see that the length of the longest product term in shortis reduced from 6 to 4. After interleaving the product terms in the new longand short, we have a PLA with a maximum overlapping wire length of 4 in theAND plane, as shown in Figure 11.

To take input probability into consideration for crosstalk prevention, we willorder the product terms in the set of super-product-terms. For each product termin the set, we compute the transition probability from 0 to 1 for the product.Then, the two product terms that have the lowest probability of transitionare moved outward in the set. The heuristic is that moving the product wirewith less probability of transition outward minimizes the chances of incurringcrosstalk between two adjacent wires, and also doesn’t change the maximumoverlapping wire length. Taking Figure 11 as an example, the product termsP2 and P3 are in the super-product-term set. Since the transition probability ofproduct term P2 is lower than that of P3, assuming all input probabilities of 1and 0 are equal, the product term P2 is moved outward to become a neighboringwire of P6, as shown in Figure 12. The detailed procedure for grouping in longset is shown in Figure 13.

4.4 I/O Reordering

Once the product-term ordering of the selected plane is fixed, the product order-ing of the unselected plane is also determined because the same product term



Fig. 12. Example of I/O reordering.

Fig. 13. The grouping in long set procedure.

extends from the AND plane to the OR plane. Based on the fixed ordering ofproduct terms, we reexamine the I/O ordering. We reorder the input (or output)ordering of the selected plane and order the output (or input) of the unselectedplane to further reduce the overlapping wire length.

Since the product wires within the super-product-term will have no effecton crosstalk computation, we can ignore these wires. The remainder of theproduct wires that will cause crosstalk effects are denoted as effective productterms. For example, in Figure 12, P2, P6, P4, P5, and P1 are effective productterms. Columns of input or output engaging more effective product terms thatmay cause crosstalk should be placed near the inter-buffer. Additionally, thecrosstalk effect is considered only between two adjacent product wires. There-fore, we define the effective dots of an input/output as those dots that occur intwo adjacent effective product terms. True and inverted phases are consideredas a whole. For example, the effective dots in the columns (I1, I2, I4, I3, I5, O1,O2, O3, O4, O5) are (0, 0, 0, 4, 3, 0, 0 ,0 ,0, 4), respectively, in Figure 12.

The columns with nonzero effective dots are selected to be ordered first. Weuse the number of effective dots in each column as a cost function to order



the input and output. I/O columns with more effective dots are ordered closerto inter-buffer so as to reduce the maximum overlap. For columns with zeroeffective dots, we simply use the number of product terms they engage to orderthe columns such that the total wire length can be minimized.

Take Figure 12 as an example. The number of effective dots in each columnfrom left-to-right is (0, 0, 0, 4, 3, 0, 0 ,0 ,0, 4). Since I3, I5, and O5 have nonzeroeffective dots, they are moved toward inter-buffers. Because I3 has more effec-tive dots than I5, I3 is moved closer to the inter-buffer. Then, I5 is moved nextto I3. The remaining inputs and outputs, I1, I2, I4, O1, O2, O3, and O4, havezero effective dots and hence are ordered by the number of product terms theyengage. The resultant PLA is shown in Figure 6.

4.5 Proof of Correctness

In this section, we will prove the correctness of our PLA crosstalk minimizationprocedure, shown in Figure 8. We will first show that the product terms groupedin Step (3) of the PLA crosstalk minimization are immune to each other, thatis, there exists no input pattern to induce the crosstalk error. Then, we willshow that the maximum overlapping wire length computed in the procedure iscorrect, that is, there is at least one input pattern which will make the signaltransition such that the maximum overlapping wire length is incurred.

Assume the switching activities of input signals are independent of eachother. Let the product terms a and v be the aggressor and victim, respectively.The crosstalk effect is induced by both the observability of crosstalk effect andthe satisfiability of aggressor and victim signals [Kim et al. 2000]. They aredescribed as follows.

Definition 4.3 (Observability). The crosstalk error on signal v can be ob-served only if there exists an input pattern which propagates the transition ofv to any primary output. The observability of wire v, denoted as OBSv, can beformulated as

OBSv = {I ∈ P I |∑

F j ∈P O

∂F j (I )∂Gv(I )

} , (3)

where F j is the j -th primary output of function F , Gv is the function of v, and∂F j (I )∂Gv(I ) represents the Boolean difference of F j with respect to Gv [Sellers et al.1968].

Definition 4.4 (Satisfiability). The crosstalk error occurs only if there existsan input pattern which satisfies a phase transition (0 → 1) of a and stable lowof v. The satisfiability of wires v and a, denoted as S ATva, can be formulatedas

SATva = {I ∈ P I |(Gv(I ) = 0) · (Ga(I ) = 1)} , (4)

where Gv(I ) is the function of wire v, Ga(I ) is the function of wire a, and I is aprimary input pattern.

Definition 4.5 (Non-CT-Immune). A product term v is not crosstalk im-mune, or non-CT-immune, to its adjacent product term a if there exists at least



one input pattern which satisfies both satisfiability and observability. This canbe formulated as

Non-CT-Immuneva = (OBSv · SATva �= ∅) . (5)

By Eq. (5), it is easy to see that v is CT-immune to a if either the observabilityOBSv or satisfiability SATva is not satisfied.

Definition 4.6 (Output-Dominance). A product term a is output-dominantover another product term v if the output set driven by v is a subset of thatdriven by a in the OR plane. It is formulated as

ODav = Oa ⊇ Ov , (6)

where Oa is the output set which is driven by product term a and Ov is theoutput set which is driven by product term v.

Definition 4.7 (Input-Dominance). A product term a is input-dominantover another product term v if the input set of a contains that of v in the ANDplane. It is formulated as

IDav = Ia ⊇ Iv , (7)

where Ia is the input set of product term a and Iv is the input set of productterm v.

PROPOSITION 4.8. Consider a NOR-NOR dynamic PLA architecture. If prod-uct term a is output-dominant over a product term v in the OR plane, then theproduct term v is CT-immune to a.

PROOF. Suppose there exists a phase transition (0 → 1) of a and stable lowof v. Since the product term a is output-dominant over v, the output driven byproduct term v must be discharged by a as well. That is, no output differencecan be observed in the output set of v. Hence, OBSv = ∅, so v is CT-immuneto a.

LEMMA 4.9. The product terms driving the same output set are CT-immuneto each other.

PROOF. For each pair of adjacent product terms a and v, the output set Oa

is equal to Ov. Both Oa ⊇ Ov and Ov ⊇ Oa are satisfied. By Proposition 4.8, v isCT-immune to a and a is CT-immune to v. Therefore, a and v are CT-immuneto each other.

THEOREM 4.10. The product terms grouped by Step (3) of the PLA crosstalkminimization, presented in Section 4.3, are CT-immune to each other.

PROOF. In Step (3) of the PLA crosstalk minimization, the productterms driving the same output set are grouped in a super-product-term. ByLemma 4.9, the product terms in a super-product-term are CT-immune to eachother.

PROPOSITION 4.11. Consider a NOR-NOR dynamic PLA architecture. Sup-pose there is no output-dominance relations between product terms a and v.



Then, a is input-dominant over v in the AND plane if and only if v is CT-immuneto a.

PROOF. (⇒) Suppose there is a phase transition (0 → 1) of product terma. Then, all the inputs of a must be 0. Since a is input-dominant over v, theinputs of product term v are 0, as well. So v has a phase transition (0 → 1),also. It is clear that S ATva = ∅. Consequently, v is CT-immune to a.

(⇐) Assume a is not input-dominant over v. There exists at least one inputvariable in v which is not in a. Let the input be t. Now, we can set t to 0 andthe rest of the inputs to 1. Then, there is a phase transition (0 → 1) of a andstable low of v. Hence, the S ATva �= ∅. Therefore, v is non-CT-immune to a.

LEMMA 4.12. If product terms a and v are not output-dominant over eachother, product term a and product term v are CT-immune to each other only ifIa = Iv.

PROOF. By Definition 4.5, a and v are not immune to each other only whenboth (OBSv · S ATva �= ∅) and (OBSa · SATav �= ∅) are satisfied. Since prod-uct terms a and v are not output-dominant over each other, both OBSv andOBSa are nonempty sets. Hence, both SATva and SATav must be empty sets. ByProposition 4.11, SATva = ∅ only when Ia ⊇ Iv. SATav = ∅ only when Iv ⊇ Ia.Therefore, Ia = Iv.

THEOREM 4.13. The pairs of adjacent product terms from Step (2) of the PLAcrosstalk minimization, presented in Section 4.2, are not CT-immune to eachother.

PROOF. Consider a and v of each pair of adjacent wires in different groups. ByLemma 4.12, a and v are CT-immune to each other only when Ia = Iv. However,any identical product terms driving different outputs must have been merged toa single product term by a logic minimization tool. Hence, there are no identicalproduct terms in the AND plane. Therefore, the pairs of adjacent product termsordered by Step (2) in Figure 8 are non-CT-immune to each other.

By Theorem 4.10, in Step (3) of the PLA crosstalk minimization presentedin Section 4.3, we can group the product terms driving the same output signalsin the long set, since they are CT-immune product terms. By Theorem 4.13, thetwo product terms from the long set and short set, respectively, are non-CT-immune to each other. This implies that the maximum overlapping wire lengthcomputed by our algorithm is correct.

5. SYNTHESIS FOR CROSSTALK MINIMIZATION

Given a function, there are many different covers that represent the samefunction. However, different covers will result in different maximum overlap-ping wire lengths after the same I/O orderings, product-term permutations,and grouping algorithms are performed. To search for a cover that mini-mizes the maximum overlapping wire length, we propose a procedure, synthe-sis for crosstalk minimization, which contains two synthesis techniques, local



transformation and global transformation, to search for a better cover. In localtransformation and global transformation, the two-level logic optimization al-gorithm Espresso will be used as a core to find the sum of product forms of agiven function [Micheli 1994].

5.1 Local Transformation

In Espresso, the REDUCE step reduces the size of a product term, while theEXPAND step expands the size of a product term. For a reduced productterm, expanding the product term in different directions will result in differentprimes. In local transformation, REDUCE and EXPAND are performed itera-tively on the product term to select suitable product terms for overlapping wirelength reduction. In each iteration, a reduced product term is expanded to allpossible primes. Then, the wire lengths for all alternatives are computed. Toreduce overlapping wire length, the product term with shortest wire length isselected for expansion.

5.2 Global Transformation

Local transformation is applied to a given synthesis result. If the given initialsynthesis result is not close to the global optimal, it is very difficult for localtransformation to produce a good solution. Therefore, we propose a global trans-formation to synthesize different initial covers for the local transformation tostart with. Global transformation perturbs the initial solution so that we canjump out of the local optimal.

To produce different initial covers, global transformation begins by splittingthe given PLA into several smaller PLAs. Then, each smaller PLA is optimizedindividually by Espresso. Finally, we combine the smaller optimized PLAs to-gether to form a new initial cover. To split each PLA into several smaller ones,we take each output of the PLA as an individual function, since each outputof the PLA can be viewed as an indivisible component. Thus, we can indepen-dently optimize each output function. Since some output functions may sharecommon product terms, these outputs are similar to each other. We can opti-mize similar outputs together to search for a larger common product term toreplace the original common product terms. Therefore, we may have a betterchance to perturb the initial covers.

To measure the similarity of two outputs, the number of common productterms of these two outputs is used. Therefore, the similarity of two outputs,sim(Oi, O j ), is defined as:

sim(Oi, O j ) = the number of common products in Oi and O j .

After computing the similarity for all pairs of outputs, we model the relationsof all outputs as a weighted complete graph, the output-grouping-graph, orOGG(V , E), where V represents output set and the weight on an edge (Oi, O j )is sim(Oi, O j ).

For the first call of the global transformation procedure, we construct theOGG. Then, we use the output group information computed by OGG to spliteach PLA into smaller PLAs, and optimize them individually. Once each smaller



Fig. 14. The procedure of global transformation.

Fig. 15. Output grouping graph of Figure 5.

PLA is optimized, we combine all smaller PLAs into a new PLA to form a newinitial cover. Figure 14 shows the global transformation procedure. After thenew initial cover is synthesized, PLA crosstalk minimization and local trans-formation are performed again to minimize the overlapping wire length of thecover. The preceding algorithm repeats until the OGG becomes a single-vertexgraph. Figure 7 shows the procedure of our overall algorithm.

Now, we use an example to demonstrate how the global transformation gen-erates different initial synthesis results for PLA crosstalk minimization andlocal transformation to start with. Figure 15(a) shows the sum of product rep-resentations of the functions in Figure 5. At the beginning, we perform PLAcrosstalk minimization and local transformation on the original PLA. The PLA



with the shortest maximum overlapping wire length is then recorded. To searchfor a better initial cover for the PLA crosstalk minimization and local transfor-mation to be with, we perform global transformation repeatedly. For the firstcall of the procedure the global transformation, we construct the OGG for thefunction. Since O1 and O2 share two product terms, the second and the thirdones, the weight on the edge (O1, O2) is 2. Similarly, we can compute weightsfor all pairs of outputs. Figure 15(b) shows the resultant OGG. Then, we splitthe PLA into five smaller PLAs accordingly, PLA for O1, one for O2, one for O3,one for O4, and one for O5. We then optimize each smaller PLA individuallyand combine them into a new PLA to form a new initial cover. After this, PLAcrosstalk minimization and local transformation are performed to minimize themaximum overlapping wire length of the new initial cover. The PLA with short-est maximum overlapping wire length computed thus far is recorded. For thesecond call of the procedure of global transformation, vertices O1 and O2 aremerged together, since the edge (O1, O2) has the largest weight. The resultantOGG is shown in Figure 15(c). After this, we split the PLA into four smallerPLAs, according to the OGG. Since the outputs O1 and O2 are grouped together,the new smaller PLA for O1 and O2 is optimized to search for a better cover.Then, we combine each optimized smaller PLA into a new PLA to form a newinitial cover. After performing PLA crosstalk minimization and local transfor-mation for the new initial cover, the best PLA is recorded. For the third call ofthe procedure of global transformation, since edges ({O1, O2}, O5) and (O3, O5)in OGG have the largest weight, we choose to merge O3 and O5, as shown inFigure 15(d). Then, PLA splitting, optimizing, and combining are performed,as in the first call of the procedure of global transformation, to minimize themaximum overlapping wire length of the PLA. For the fourth call of the pro-cedure of global transformation, vertices ({O1, O2} and {O3, O5}) are merged togenerate the new initial cover in Figure 15(e). For the fifth call of the proce-dure of global transformation, we merge {O1, O2, O3, O5} and O4 to form theOGG with the single vertex in Figure 15(f). Since the number of vertices inOGG becomes 1, the iteration ends. Finally, the PLA with the shortest maxi-mum overlapping wire length is chosen as the final result of our synthesis forcrosstalk minimization.

6. EXPERIMENTAL RESULTS

Our experiment is performed on a SUN-Blade1000 with 2 GB of memory. Thesoftware platform is based upon the Espresso package in SIS [Sentovich et al.1992]. The MCNC benchmark suite is used in our experiments. We select cir-cuits with less than 700 product terms. For large designs, we need to divide thePLA into smaller ones for realistic PLA design. River PLA [Mo and Brayton2002] can be applied for this goal, though we do not discuss it in this work.The experiment is conducted to find the minimum overlapping wire length of acircuit. All benchmark circuits are preprocessed by Espresso to generate a PLAcover with minimal area cost.

The experimental results are shown in Tables II–VI. The column labeledOriginal is the initial area-optimized circuit. Columns labeled Min total and



Table II. Results of Maximum Overlapping Wire Length

Original Min total (Tien’s) Min max (Ours)Circuit I O P Max Max RMax (%) P RP (%) Max RMax (%)

alu2 10 8 68 20 19 95.0 68 100.0 11 55.0alu3 10 8 66 19 18 94.7 66 100.0 11 57.9b10 15 11 100 30 28 93.3 100 100.0 19 63.3b12 15 9 43 29 21 72.4 46 107.0 12 41.4b3 32 20 211 64 55 85.9 211 100.0 31 48.4b9 16 5 119 32 27 84.4 119 100.0 16 50.0bc0 26 11 179 52 36 69.2 179 100.0 20 38.5chkn 29 7 140 56 46 82.1 140 100.0 12 21.4dc2 8 7 39 16 13 81.3 39 100.0 12 75.0ex7 16 5 119 32 27 84.4 119 100.0 16 50.0gary 15 11 107 30 28 93.3 107 100.0 21 70.0ibm 48 17 173 95 76 80.0 173 100.0 28 29.5in0 15 11 107 30 28 93.3 107 100.0 21 70.0in2 19 10 136 37 29 78.4 136 100.0 18 48.6in7 26 10 54 51 42 82.4 54 100.0 22 43.1intb 15 7 631 30 28 93.3 631 100.0 17 56.7max1024 10 6 274 20 19 95.0 299 109.1 11 55.0max512 9 6 145 18 17 94.4 157 108.3 10 55.6newcond 11 2 31 20 15 75.0 31 100.0 13 65.0newtpla 15 5 23 27 18 66.7 23 100.0 15 55.6shift 19 16 100 38 24 63.2 100 100.0 13 34.2sqn 7 3 38 14 14 100.0 39 102.6 9 64.3ts10 22 16 128 32 30 93.8 128 100.0 16 50.0vg2 25 8 110 50 48 96.0 110 100.0 21 42.0vtx1 27 6 110 54 48 88.9 110 100.0 18 33.3x1dn 27 6 110 54 48 88.9 110 100.0 18 33.3x6dn 39 5 82 78 66 84.6 82 100.0 18 23.1x7dn 66 15 538 131 76 58.0 538 100.0 23 17.6x9dn 27 7 120 54 50 92.6 120 100.0 30 55.6

average 84.8 100.9 48.4

Min max are the results of work by Tien et al. [2002], which minimizes thetotal overlapping wire length, whereas our method minimizes the maximumoverlapping wire length.

In Table II, I, O, and P are the number of inputs, outputs, and product terms,respectively. The column labeled Max represents maximum overlapping wirelength. The columns RP and RMax are, respectively, the ratio of the productterm number and maximum overlapping wire length of the original circuits tothose of both Tien’s and ours. From Table II, we can see that the maximumoverlapping wire length produced by our algorithm can be reduced by 51%,while only by 15% in Tien’s work, as compared to that of the original circuit.The area of Tien’s method is the same as those of original circuits. Since weperformed a resynthesis of the circuits, the area may not be the same as thoseof the original circuits. Our method has an area overhead ratio of about 0.9%, ascompared with original area-minimized PLA. It is clear that our algorithm cangreatly reduce the maximum overlapping wire length with small area overhead.Table III compares the total overlapping wire lengths. The column labeled



Table III. Results of Total Overlapping Wire Length

Original Min total (Tien’s) Min max (Ours)Circuit Total Total RTotal (%) Total RTotal (%)

alu2 729 193 26.5 249 34.2alu3 559 132 23.6 164 29.3b10 2732 813 29.8 1081 39.6b12 788 260 33.0 254 32.2b3 12746 2079 16.3 2461 19.3b9 921 89 9.7 107 11.6bc0 8630 1743 20.2 2179 25.2chkn 3196 252 7.9 131 4.1dc2 618 193 31.2 270 43.7ex7 921 89 9.7 107 11.6gary 3116 1059 34.0 1301 41.8ibm 13206 822 6.2 942 7.1in0 3202 1059 33.1 1291 40.3in2 4229 1047 24.8 1272 30.1in7 1332 367 27.6 389 29.2intb 3740 164 4.4 183 4.9max1024 3712 458 12.3 245 6.6max512 2352 363 15.4 209 8.9newcond 78 16 20.5 30 38.5newtpla 288 68 23.6 89 30.9shift 3187 356 11.2 421 13.2sqn 369 72 19.5 75 20.3ts10 450 432 96.0 572 127.1vg2 2016 248 12.3 200 9.9vtx1 1465 228 15.6 145 9.9x1dn 1465 228 15.6 145 9.9x6dn 4281 455 10.6 520 12.1x7dn 41494 702 1.7 663 1.6x9dn 1620 285 17.6 215 13.3average 21.0 24.4

Total is the total overlapping wire length of the PLA. The experiments showthat our algorithm can reduce the total overlapping wire length by 75%, whileTien’s method reduces this by 79%.

Table IV shows the effectiveness of each step of our algorithm. The maxi-mum overlapping wire length of the original area-optimized circuit is underthe column labeled Original. The result after the step of initial I/O ordering isshown under the column labeled I/O. Then, the result after the step of long setand short set interleaving is listed under the column labeled Interleaving. Thecolumn labeled Grouping is the result of applying all the I/O and product wirepermutation techniques described in Section 4. Finally, the value shown in thecolumn labeled Synthesis is the result when both permutation and synthesistechniques are applied. The experimental results demonstrate that each stephas effectively contributed to the reduction of the maximum overlapping wirelength.

Table V shows the runtime analysis of wire reordering and resynthesis tech-niques. The column labeled Reordering is the execution time used by PLA



Table IV. Effectiveness of Each Minimization Technique

Original I/O Interleaving Grouping SynthesisCircuit Max Max RMax (%) Max RMax (%) Max RMax (%) Max RMax (%)

alu2 20 20 100.0 13 65.0 11 55.0 11 55.0alu3 19 16 84.2 12 63.2 11 57.9 11 57.9b10 30 28 93.3 20 66.7 19 63.3 19 63.3b12 29 23 79.3 14 48.3 14 48.3 12 41.4b3 64 62 96.9 31 48.4 31 48.4 31 48.4b9 32 27 84.4 20 62.5 16 50.0 16 50.0bc0 52 36 69.2 20 38.5 20 38.5 20 38.5chkn 56 48 85.7 30 53.6 29 51.8 12 21.4dc2 16 14 87.5 12 75.0 12 75.0 12 75.0ex7 32 27 84.4 20 62.5 16 50.0 16 50.0gary 30 28 93.3 21 70.0 21 70.0 21 70.0ibm 95 58 61.1 28 29.5 28 29.5 28 29.5in0 30 28 93.3 21 70.0 21 70.0 21 70.0in2 37 35 94.6 18 48.6 18 48.6 18 48.6in7 51 29 56.9 24 47.1 21 41.2 22 43.1intb 30 28 93.3 19 63.3 17 56.7 17 56.7max1024 20 19 95.0 13 65.0 13 65.0 11 55.0max512 18 17 94.4 12 66.7 12 66.7 10 55.6newcond 20 17 85.0 13 65.0 13 65.0 13 65.0newtpla 27 16 59.3 15 55.6 15 55.6 15 55.6shift 38 24 63.2 12 31.6 13 34.2 13 34.2sqn 14 14 100.0 11 78.6 10 71.4 9 64.3ts10 32 28 87.5 18 56.3 16 50.0 16 50.0vg2 50 46 92.0 30 60.0 30 60.0 21 42.0vtx1 54 50 92.6 34 63.0 34 63.0 18 33.3x1dn 54 50 92.6 34 63.0 34 63.0 18 33.3x6dn 78 50 64.1 22 28.2 18 23.1 18 23.1x7dn 131 58 44.3 24 18.3 23 17.6 23 17.6x9dn 54 48 88.9 36 66.7 36 66.7 30 55.6average 100.0 83.3 56.2 53.6 48.4

crosstalk minimization. The column labeled Resynthesis is the total executiontime of global transformation and local transformation. The overall executiontime is listed in column Total. The column Time is the CPU-time in seconds.Columns Ro and Rs represent the ratio of execution time used by wire reorder-ing and by resynthesis to total runtime, respectively. The experimental resultsshow that in total runtime, 75% of the execution time is used by resynthesis,while 25% is used by wire reordering. In sum, after performing the wire reorder-ing techniques described in Section 4, the maximum overlapping wire lengthof the resultant PLA is greatly reduced. However, we can keep reducing themaximum overlapping wire length by means of resynthesis techniques withmore runtime.

To compare the actual circuit delay of PLA using different implementa-tions, some medium sized circuits are selected for experimentation. For eachcircuit, we generate three product-term orderings: the product terms are or-dered to follow the output ordering of Espresso, to minimize the total overlap-ping wire length, and to minimize the maximum overlapping wire length. After



Table V. Result of Runtime Analysis

Reordering Resynthesis TotalCircuit Time Ro (%) Time Rs (%) Timealu2 0.02 20.0% 0.08 80.0% 0.10alu3 0.01 7.7% 0.12 92.3% 0.13b10 0.25 20.3% 0.98 79.7% 1.23b12 0.03 33.3% 0.06 66.7% 0.09b3 1.56 20.0% 6.23 80.0% 7.79b9 0.12 27.3% 0.32 72.7% 0.44bc0 0.96 16.1% 5.01 83.9% 5.97chkn 0.39 30.0% 0.91 70.0% 1.30dc2 0.02 25.0% 0.06 75.0% 0.08ex7 0.09 20.5% 0.35 79.5% 0.44gary 0.25 17.7% 1.16 82.3% 1.41ibm 1.49 18.3% 6.65 81.7% 8.14in0 0.26 18.1% 1.18 81.9% 1.44in2 0.32 23.4% 1.05 76.6% 1.37in7 0.09 39.1% 0.14 60.9% 0.23intb 2.83 35.3% 5.19 64.7% 8.02max1024 0.38 21.0% 1.43 79.0% 1.81max512 0.12 30.8% 0.27 69.2% 0.39newcond 0.02 66.7% 0.01 33.3% 0.03newtpla 0.00 0.0% 0.03 100.0% 0.03shift 0.22 52.4% 0.20 47.6% 0.42sqn 0.00 0.0% 0.02 100.0% 0.02ts10 0.53 55.8% 0.42 44.2% 0.95vg2 0.19 20.0% 0.76 80.0% 0.95vtx1 0.15 18.8% 0.65 81.3% 0.80x1dn 0.14 18.2% 0.63 81.8% 0.77x6dn 0.11 23.4% 0.36 76.6% 0.47x7dn 8.66 22.4% 30.06 77.6% 38.72x9dn 0.20 18.3% 0.89 81.7% 1.09average 24.8% 75.2%

constructing these three orderings, we use PLACompiler together with Virtu-oso [Cadence 1999] to generate the layout of each PLA. Based upon the TSMCSPICE MODEL for 0.18μm mixed signal SALICIDE (1P6M, 1.8V) process tech-nology, the timing simulation results are produced by Hspice [Synopsis 2001].The input vector is selected to produce a transition on a victim wire with themaximum coupling capacitance of the circuit and no transitions on its twoneighboring wires. The benchmark process is similar to that used for Table I.Table VI shows the results. From this table, we can see that for all cases, the bestdelay is the design where the maximum overlapping wire length is minimized.

7. CONCLUSION

We have proposed a new synthesis flow to minimize the crosstalk effects of PLA.The long and short set interleaving technique reduces the overlapping wirelength of PLAs. To further reduce the longest product-term wire length in short,we group product terms in the long set. Finally, the synthesis techniques of localand global transformations are used to search for a better cover for overlapping



Table VI. Timing Simulation on Dynamic PLA with Different Product Wire Orderings

Circuit Method P TAND TOR Max Delay (ps) RDelay (%)Original 68 594 135 20 419.0 100.0

alu2 Min total 68 150 43 19 414.7 99.0Min max 68 181 68 11 407.9 97.3Original 43 655 133 29 369.2 100.0

b12 Min total 43 189 71 21 340.8 92.3Min max 46 173 81 12 335.7 90.9Original 39 512 106 16 270.4 100.0

dc2 Min total 39 150 43 13 258.5 95.6Min max 39 213 57 12 231.4 85.6Original 54 1215 117 51 417.9 100.0

in7 Min total 54 307 60 42 414.7 99.2Min max 54 339 50 22 399.9 95.7Original 31 74 4 20 381.2 100.0

newcond Min total 31 15 1 15 340.1 89.2Min max 31 28 2 13 336.2 88.2Original 23 267 21 27 253.5 100.0

newtpla Min total 23 61 7 18 241.9 95.4Min max 23 77 12 15 238.1 93.9Original 82 4110 171 78 854.0 100.0

x6dn Min total 82 402 53 66 847.4 99.2Min max 82 430 90 18 781.5 91.5

wire length reduction. The experimental results demonstrate that our PLAsynthesis methodology can effectively reduce the maximum overlapping wirelength of PLA by 51%. It is possible to minimize the power consumption of aPLA by defining a new cost function in terms of overlapping wire length andswitching activities. We will leave this as our future work.

ACKNOWLEDGMENT

The authors would like to thank Prof. Shih-Chieh Chang and Dr. Tzyy-KuenTien for providing us with the PLACompiler.

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Received November 2004; revised March 2006; accepted May 2006


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