CPU + memory

PC

address

200

memory

CPU

PCdata

IRADD r5,r1,r3200

200

ADD r5,r1,r3

Harvard architecture

PCdata memory

address

data

CPU

program memory

address

data

RISC vs. CISC

• Complex instruction set computer (CISC):

– many addressing modes;

– many operations.

• Reduced instruction set computer (RISC):

– load/store;

– pipelinable instructions.

Instruction set characteristics

• Fixed vs. variable length.

• Addressing modes.

• Number of operands.• Number of operands.

• Types of operands.

Programming model

• Programming model: registers visible to the

programmer.

• Some registers are not visible (IR).• Some registers are not visible (IR).

Multiple implementations

• Successful architectures have several

implementations:

– varying clock speeds;

– different bus widths;

– different cache sizes;

– etc.

GPS

receiver

search

enginerenderer display

GPS moving map block diagram

user

interfacedatabase

GPS moving map hardware

architecture

CPUdisplay frame

buffer

GPS

receiver

panel I/Omemory

GPS moving map software

architecture

position database

searchrenderer

pixels

search

timeruser

interface

Four-cycle handshake

• Basis of many bus protocols.

• Uses two wires:

– enq (enquiry);– enq (enquiry);

– ack (acknowledgment).

dev1 dev2

enq

ack

data

Four-cycle example

enq

1 3

4

time

ack

data24

Typical bus signals

• Clock.

• R/W’: true when bus is reading.

• Address: a-bit bundle.• Address: a-bit bundle.

• Data: n-bit bundle.

• Data ready’.

Timing diagrams

A

zero

one

rising falling

stable

10 ns

time

B

C

changing

Typical bus timing for read

• CPU:

– asserts address, address enable;

– set R/W’=1.

• Memory:• Memory:

– asserts data;

– asserts data ready’.

• CPU:

– De-asserts address, address enable.

Bus read state diagram

Get

data Done

Adrs

Wait

See ack

Transaction types

• Wait state:

– state in a bus transaction to wait for

acknowledgment.

• Disconnected transfer:

– bus is freed during wait state.

• Burst:

– multiple transfers.

Host/target design: Cross-Compilazione

• Use a host system to prepare software for

target system:

target

system

host system

serial line:

BDM - JTAG

Typical PC hardware platform

CPU

CPU bus

memory

inte

rfa

ce

device

CPU bus

DMA

controllertimers

bus

interface

bu

s

inte

rfa

ce

high-speed bus

low-speed bus

device

intr

ctrl

Logic analyzers

• A logic analyzer is an array of low-grade

oscilloscopes:

Logic analyzer architecture

UUT sample

memorymicroprocessor

controller

system clock

clock

gen

state or

timing mode

vector

address

displaykeypad

I2C bus

• Designed for low-cost, medium data rate applications.

• Characteristics:

– serial;– serial;

– multiple-master;

– fixed-priority arbitration.

• Several microcontrollers come with built-in I2C controllers.

I2C physical layer

master 1 master 2

SDL

data line

slave 1 slave 2

SCL

clock line

I2C data format

SCL ......

SDL

MSBstart

...

ack

I2C electrical interface

SDL

+• Open collector interface:

SCL

+

I2C signaling

• Sender pulls down bus for 0.

• Sender listens to bus---if it tried to send a 1

and heard a 0, someone else is and heard a 0, someone else is

simultaneously transmitting.

• Transmissions occur in 8-bit bytes.

I2C data link layer

• Every device has an address (7 bits in

standard, 10 bits in extension).

– Bit 8 of address signals read or write.

• General call address allows broadcast.

I2C bus arbitration

• Sender listens while sending address.

• When sender hears a conflict, if its address is

higher, it stops signaling.higher, it stops signaling.

• Low-priority senders relinquish control early

enough in clock cycle to allow bit to be

transmitted reliably.

I2C transmissions

multi-byte write

read from slave

S adrs 0 data data P

read from slave

write, then read

S adrs 1 data P

S adrs 0 data S adrs 1 data P

Personal digital assistant

• PDA: portable, specialized information device.

• Characteristics:

– low cost for consumer market;– low cost for consumer market;

– physically small;

– battery-powered;

– software-rich.

Apple Newton

• First modern PDA.

• Original used ARM 610; later version used

StrongARM (ARM7) last: ARM9.StrongARM (ARM7) last: ARM9.

• Support operations in Runt ASIC: DMA, real-

time clock, video interface, audio, PCMCIA.

• Software written in NewtonScript language.

Newton hardware architecture

ARM 610 ROM RAM

RuntPCMCIA Runt

ASIC

LCD

speaker

serial I/F

A/D

tablet

PCMCIA

infrared

Motorola Envoy hardware

architecture

PCMCIA 1 MB DRAM 4 MB flash

Astro infrared

Magicbus

Astro

system

ASIC

68439

CPU

audio

modem

infrared

power supply

A/Dtouchscreen

Moore’s Law (Sematech)

109

billion-transistor

108

2000 2012

PC on chip

billion-transistor

system-on-chip

Embedding a computer

output analog

CPU

mem

input analog

embedded

computer

Examples

• Personal digital assistant (PDA).

• Printer.

• Cell phone.• Cell phone.

• Automobile: engine, brakes, dash, etc.

• Television.

• Household appliances.

• PC keyboard (scans keys).

BMW 850i brake and stability

control system

• Anti-lock brake system (ABS): pumps brakes to

reduce skidding.

• Automatic stability control (ASC+T): controls • Automatic stability control (ASC+T): controls

engine to improve stability.

• ABS and ASC+T communicate.

– ABS was introduced first---needed to interface to

existing ABS module.

BMW 850i, cont’d.

brake

sensor

brake

sensor

brake

sensor

brake

sensor

ABShydraulic

pump

Ruby II

advanced

communication

controller

organization

ARMcore

512 x 32SRAM

counter/timers

interruptcontroller

paralleli/f 1,2,3,4

external

control

address (22)

externalinterrupts (3)

clockcontrol

clock

UART2

serial

UART1

PCMCIAhost

interface

parallelinterface 0

externalbus

control

serial

address (22)

data (8/16/32)

I2C, ...

8 data bits & control

controller

high-speedserial i/f

hostFIFOs

(16 x 8)

serialFIFOs

(16 x 8)

I/Omodeselect

VIP

organization

ARM6core

768 x 32SRAM

timer &watchdog

interruptcontroller

parallelinterface

control

externalinterrupts (3)

clockcontrol

clock

ports

ADCs (2)

DRAM

B and D

G.711

addressdecoder

externalbus

control

serial

address (23)

data (8/16/32)

ras, cas

chip selects

controller

DSPserial i/f

mux address

codechandset/hands-free

S0-interfacechannels

battery, volume

Typical VIP system configuration

Driver

hands-freeV24 interface

volume

hook switch

K E Y

P A D

power

S0-ISDN interface

ROM

RAM

ISDNSubscriberProcessor

hook switch

OneC

VWS22100

GSM chip

organization 32 KHz

JTAGtest/debug

ARM7TDMIcore

interruptcontroller

are cs

programRAM

programROM

radio i/fDSP radio

port

PCM i/faudio i/f

SIM i/f

RTC

bootROM

UART1

UART2/IrDA

high-speedserial i/f (2)(20)

(13)

(6)

(6)

(4)

(5)

(4)

DS

P b

us

cntrl (6)

addr (20)

data (16)

interruptcontroller

config./status

dataROM

dataRAM

powermanager

memorycontroller

Oak DSPcore

ha

rdw

acop

roc

ADC

keypadscanner

GPIOPWM

RTC

externalbus

control

(7)

(10)

(11)D

AR

M b

us

DSPsubsystem

Typical GSM handset architecture

VWS22100

SIM

card eeprom

radiomodule

IrDA

speaker

mic

K E Y

P A D

ROM

RAM

VWS22100

LCD

ringer

Ericsson-VLSI Bluetooth Baseband Controller

organization

ARM7TDMIcore

4 KbyteI-cache

16K x 32SRAM

internalROM

control

JTAGsignals (5)

clockcontrol

clock

EBC

externalbus

control

control

address (20)

data (8/16)

radio interface

block

USB i/f

I2C i/f

UART1,2,3

FIFOsI/O

modeselect

interruptcontroller

counter/timers

Typical Bluetooth application

flashflash Bluetooth

Basebandaddress

memoryradio

moduleflashmemory

BasebandController

control

data

host interface

memory module

(RS232/USB)

Bluetooth characteristics

Process 0.25 um Transistors 4,300,000 MIPS 12

Metal layers 3 Die area 20 mm2

Power 75 mW

Vdd 2.5 V Clock 0 – 13 MHz MIPS/W 160Vdd 2.5 V Clock 0 – 13 MHz MIPS/W 160

AM

AM

AM

AM

DR

AM

DR

AM

DR

AM

DR

AM

DR

AM

DR

AM

DR

AM

DR

AM

DR

AM

DR

AM

DR

AM

DR

AM

RA

[11

:0]

cas[3:0]

]

analoguesound v

ide

o

Typical

ARM7500

system

organizationARM7500

DR

A

DR

A

DR

A

DR

A

RO

M

RO

M

I/Omodule

I/Omodule

LA[28:0]

D[31:0]

ras[3

:0]

inte

rrup

ts

BD[15:0]

moduleselects

keyboard& mouse

analogueinputs

organization

ARM7500 characteristics

Pro ces s 0.6 um Trans i s to rs 550,000 MIPS 30

Metal l ay ers 2 Di e area 70 mm2

Po wer 690 mW

Vdd 5 V Cl o ck 0 to 33 MHz MIPS/ W 43Vdd 5 V Cl o ck 0 to 33 MHz MIPS/ W 43

ARM7100

organization

LCDcontroller

control

address (28)

data (32)

clock PLLpowermgt.

counter/timers

MMUARM7core

8 Kbytecache

3.6864 MHz

32.786 KHz

interruptcontroller

externalbus

control

AMBA

ARM710a

data (32)

DRA(13)

codec i/f

FIFOs

UART

RTCosc.

32.786 KHz

RAS, CAS(8)

WE, OE(2)

DRAMcontroller

sync serial expansion

parallel I/O PSU control

The Psion

Series 5

hardware

ARM7100

ROMDRAM

ADC

PSU

PC cards

Flash

hardware

organization

640 x 240

digitizing

LCD

tablet

codec

IrDA Tx/Rx

RS232

keyboard

infrared

audio

ARM7100 characteristics

Process 0.6 um Transistors N/A MIPS 30

Metal layers 2 Die area N/A mm2

Power 14 mW

Vdd 3.3 V Clock 18.432 MHz MIPS/W 212Vdd 3.3 V Clock 18.432 MHz MIPS/W 212

CPU core

SA-1core d

ata

ca

ch

e

instructioncache

instructionMMU

dataMMU

min

i-ca

che

read bufferwrite buffer

LCD (5)

data (32)

address (26)

system bus

SA-1100

organization

3.6864 MHz

32.786 KHz

clockPLL

RTCosc.

memory &PCMCIA

LCDcontrol

DMAcontrol bridge

serial 0

serial 1

serial 2

serial 3

serial 4reset

control

interruptcontrol

OStimer

general-purpose I/O

powermanager

RTC

LCD (5)

I/O pins (28)

battery (3)

address (26)

control

USB (2)

SDLC (2)

IrDA (2)

UART (2)

Codec (4)

peripheral bus

reset (2)

SA-1100 characteristics

Process 0.35 um Transistors 2,500,000 MIPS 220/250

Metal layers 3 Die area 75 mm2

Power 330/550 mW

Vdd 1.5/2 V Clock 190/220 MHz MIPS/W 665/450Vdd 1.5/2 V Clock 190/220 MHz MIPS/W 665/450