1880 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 40, NO. 10, OCTOBER 1993

= qnp= 2 x&m

di = 0.2 pm Gate length I Lpm NA = 0.5 x 1015/cc

CLOCK VOLTAGE = 4 v = 1o15/cm2sec E, = 12.4

po = ~ s 0 0 c m 2 / v . s

Si without fringing InP without fringing

Si with fringing

.-

Transfer t ime (s)

Fig. 2. Transfer inefficiency against transfer time for InP and Si OECCD with and without the effect of fringing field.

166- 1 6 ~ 1 103 lo6 lo9 lon

Frequency (Hz)

Fig. 3. Transfer inefficiency as a function of signal frequency for InP OECCD for three different storage times.

frequency is 10 kHz, and the clock voltage is 4 V. The fringing field significantly increases the charge transfer efficiency, and it is more in the case of InP than Si.

Fig. 3 is the plot of transfer inefficiency against modulating sig- nal frequency at different storage time. The plot indicates a wide coverage of frequency spectrum, from to 10” Hz. From very low frequency up to that corresponding to the storage time, the transfer inefficiency is constant and does not depend on modulating frequency. However, at a frequency near to the storage time, there is a rise in transfer inefficiency, and the value remains unchanged up to a frequency 10 GHz. Beyond 10 GHz, there is a fall and again rise of transfer inefficiency independent of storage time which in- dicates that the behavior is oscillatory. This can be explained from

(10) and (1 l ) , and it may set a frequency limit to the use of InP OECCD. The results are thus interesting for further work.

REFERENCES

[ I ] N. Ula, G. A. Cooper, J . C. Davidson, S. P. Swierkowsky, andC. E. Hunt, IEEE Trans. Electron Devices, vol. ED-39, pp. 1032-1040, 1992.

[2] R. J. Strain and N. L. Schryer, Bell Syst. Tech. J . , vol. 50, pp. 1721- 1740, 1971.

[3] C. H. Chan and S. G. Chamberlain, SolidState Electron., vol. 17, pp.

[4] J. G. C. Bakker, IEEE Trans. Electron Devices, vol. ED-38, pp. 1152-

[ 5 ] M. J. Howes and D. V. Morgan, Charge Coupled Devices and Sys-

491-499, 1974.

1161, 1991.

tems. New York: Wiley, 1979.

CMOS Compatible Shorted Anode Auxiliary Cathode Lateral Insulated Gate

Bipolar Transistors

E. M. Sankara Narayanan, G. A. J. Amaratunga, and W . I. Milne

Abstract-The performance of CMOS compatible shorted anode aux- iliary cathode lateral insulated gate bipolar transistors (SA-ACLIGBT), fabricated using a standard 2.5 pm digital CMOS compatible high volt- age integrated circuit process, is investigated. Typical on-state current densities of more than 240 A/cm* at a gate voltage of 10 V and a for- ward voltage of 5 V have been obtained in these devices. These devices show a latchup-free, current saturation behavior when compared to their equivalent shorted anode LIGBT’s. Measured high voltage turnoff characteristics of the SA-ACLIGBT are superior to those of the conventional SA-LIGBT. These results confirm that by placing an auxiliary cathode and extending a p+ buried layer from under the p well into the drift region of the SA-LIGBT structure, the holes flowing into the p well can be diverted to improve device performance. The auxiliary cathode plays a vital role in preventing the triggering of the parasitic thyristor; it also plays an important role in extracting minor- ity carriers during the turnoff transient.

INTRODUCTION

Recently, we proposed a modified lateral insulated gate bipolar transistor suitable for HVIC’s [ 11. It was shown through simulation that improvements in latchup immunity and turnoff time could be achieved in an LIGBT structure by incorporating a p+ auxiliary cathode and an extended pf buried layer. In this brief, the perfor- mance of this auxiliary cathode lateral insulated gate bipolar tran- sistor (ACLIGBT) is experimentally verified.

DEVICE DESIGN

The basic difference between the SA-ACLIGBT structure and an SA-LIGBT is the presence of an additional p+ cathode between the p well and the pf anode. The auxiliary cathode is connected to the common source. The following devices are considered here:

Manuscript received February 24, 1992; revised May 12, 1993. This work was supported by the Science and Engineering Research Council, U.K. The review of this brief was arranged by Associate Editor T. P. Chow.

The authors are with the Engineering Department, Cambridge Univer- sity, Trumpington Street, Cambridge, CB2 IPZ, U.K.

IEEE Log Number 921 1109.

0018-9383/93$03.00 0 1993 IEEE

IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 40, NO

n d r i f t I p bu r ied l aye r n b u r i e d l aye r

D subs t ra te

Fig. I . The cross sectional view of an anode shorted ACLIGBT structure (type C ) .

10, OCTOBER 1993 1881

1) a device with the p+ buried layer placed under the p well only

2) a device with the p+ buried layer extended into the drift re- gion in such a way that it covers the entire length of the auxiliary cathode (type B); and

3 ) an n+ buried layer under the anodeldrain, in addition to the extended p+ buried layer (type C). A schematic cross section of this device is shown in Fig. 1.

Devices grown on an n- epitaxial layer with a thickness of 9 p m and a substrate concentration of 1 X lOI5 cm-3 are considered. The p well and p buried layer concentrations are optimized within the range of 1 X 10l6- 4 X IO” ~ m - ~ , based on CMOS process com- patibility [ 2 ] . The distance between the p well and the p’ anode is 40 pm. The auxiliary cathode is kept 20 pm away from the anode in the SA-ACLIGBT. The concentration of the p well is adjusted to have a threshold voltage of about 1 V for a gate oxide thickness of 400 A. The geometrical channel length is 5 pm. The p substrate, the p+ auxiliary cathode, the p buried layer, and the source are all connected to ground.

(type A);

OFF-STATE ANALYSIS

High reverse blocking voltage capability of these devices is ob- tained using the RESURF principle [ 3 ] , [4]. The simulated break- down voltages for the type A SA-ACLIGBT structure is 138 V, while that of an equivalent SA-LIGBT structure is 300 V. This is due to the comer breakdown at the auxiliary cathode of the SA- ACLIGBT because of improper RESURF. This is overcome in type B devices by using a p+ buried layer which extends halfway into the drift region to achieve rapid JFET like pinchoff between the p+ auxiliary cathode and the extended buried layer in the off-state. In the present design, the JFET-like pinchoff occurs at a voltage of 15 V. The simulated breakdown voltages in both SA-ACLIGBT and SA-LIGBT type B structures are close, i.e., 264 and 275 V, respectively.

The type C device has a charge controlled n+ buried layer under the anodeldrain, in addition to the extended p+ buried layer. The n + buried layer helps in reducing the parasitic substrate current and preventing latchup of CMOS devices in HVIC’s [ 5 ] .

ON-STATE ANALYSIS

The on-state current conduction mechanism of the SA-ACLIGBT is similar to that of the SA-LIGBT. The detailed current flow paths in the SA-ACLIGBT are best illustrated using the equivalent circuit shown in Fig. 2. The total current is comprised of anode and drain currents flowing through the p + anode and the n+ drain contact. In turn, the anode current comprises of the hole currents flowing into different collector regions. The MOS channel currents is comprised of the electron current at the n+ drain contact and the base electron

current required to maintain all the pnp transistors. The constituent bipolar transistors in the SA-ACLIGBT are

QpA QpR pnp p+ anode, n- drift region, p+ buried layer

Qps pnp p+ anode, n- drift region, p substrate

Qpw pnp p+ anode, n- drift region, p well

Qn npn n + source, p well, n- drift region.

pnp p+ anode, n- drift region, p+ auxiliary cathode

In an SA-LIGBT, the lateral pnp transistor QpA does not exist. From the equivalent circuit shown in Fig. 2, similar to that in

[6], the total current of the anode-shorted ACLIGBT structure can be expressed as

Here, I D R is part of the MOS current flowing directly between the n+ contact at the anodeldrain and the cathode contact, andfi , h,f3 andf, are fractions of the remaining part of the MOS current re- quired to maintain the bipolar transistors involving the auxiliary cathode, p+ buried layer, the p substrate, and the p well, respec- tively, as collectors. Prior to latchup, the total device current in the SA-ACLIGBT is determined by the MOS channel current and the current gain of the four pnp transistors. Equation ( I ) can be simplified to

Below the bipolar on-set voltage, the presence of the auxiliary cathode will increase the on-resistance of the drift region. Above the bipolar on-set voltage, the reduce base width of the extra lateral pnp transistor (epA) gives it a higher bipolar current than the lateral pnp transistor (epw) which is the only active lateral transistor in the conventional SA-LIGBT. Hence, the SA-ACLIGBT will show a lower forward drop compared to the conventional SA-LIGBT in bipolar injection mode.

The most important feature of the SA-ACLIGBT is the pres- ence of the auxiliary cathode which acts to divert the hole current flowing into the p well. At low current levels, this is easily achieved. As the forward voltage increases, the vertical pnp tran- sistor (eps) saturates first because of shorter base width and holes start to flow laterally. However, the depletion region underneath the auxiliary cathode will be pinched off as in a JFET with the p+ buried layer and the p+ auxiliary cathode acting as gate electrodes. Thus, the hole current flowing into the p well is effectively diverted even after Qps reaches saturation. The presence of JFET-like sat- uration between the p+ auxiliary cathode and the p+ buried layer ensures latchup suppression even after the vertical transistor reaches saturation in the SA-ACLIGBT. This is a very important feature of the SA-ACLIGBT in that it has the ability to automatically limit the lateral current flow into the p well through JFET-like satura- tion.

EXPERIMENTAL RESULTS

A CMOS compatible HVIC process, in which various types of lat- eral MOS controlled power devices can be fabricated without ad- versely affecting the performance of the CMOS circuitry, was used to fabricate SA-ACLIGBT and SA-LIGBT structures. The details of the process are described elsewhere [7].

1882 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 40. NO. 10, OCTOBER 1993

I c:mo, Fig. 2. The simplified equivalent circuit of an SA-ACLIGBT

TABLE I THE MEASURED BREAKDOWN VOLTAGE OF A, B, A N D C SA-ACLIGBT

AND SA-LIGBT STRUCTURES

Breakdown Voltage (V) Breakdown Voltage (V) Device Type SA-ACLIGBT SA-LIGBT

A B C

103 210 254

220 224 260

BREAKDOWN VOLTAGE PERFORMANCE The average measured breakdown voltage of each of the devices

is shown in Table I. Of these, the type A SA-ACLIGBT structure shows the lowest breakdown voltage. The increase in the break- down voltage in the type C structure, in comparison to the type B device, is due to the presence of a charge controlled n + buried layer under the shorted anode preventing punchthrough. The breakdown voltages of all these devices are lower than their equivalent SA- LIGBT counterparts. Even though the trend observed is the same between simulation and experimental results, the actual breakdown voltage values are different. The reason for this is thought to be due to the simulator not taking into account three-dimensional cor- ner effects due to the square cell geometry of the test devices.

ON-STATE PERFORMANCE

The bipolar onset voltage for all types of anode-shorted ACLIGBT varies between 1 and 2 V. The current prior to the bi- polar on-set voltage is insignificant (less than 5 mA) in all cases. A typical I( V ) characteristics of the type B SA-ACLIGBT with the extended p+ buried layer is shown in Fig. 3. This device does not show latchup, and shows current saturation behavior.

A comparison of the f ( V ) performance between type A and B structures reveals that the forward drop decreases with the presence of an extended p + buried layer. This is due to the reduction in the collector resistance of the vertical pnp transistor. The device with the nf buried layer (type C) shows higher on-resistance and higher bipolar on-set voltage. The reduced current gain of the vertical pnp transistor with the substrate as its collector leads to a higher on- resistance. None of the SA-ACLIGBT devices showed any latchup under test conditions. These results confirm that the auxiliary cath- ode is effective in preventing latchup. On the other hand, the type B SA-LIGBT latches up at a typical current density of 340 A/cm2.

ANODE

Fig. 3 The I ( V ) characteristics of the SA-ACLIGBT structure (type B).

Fig. 4. The measured high voltage transient wave form of the SA- ACLIGBT (type B) when the gate voltage (top) is switched from 5 to 0 V. The output voltage (bottom) is measured across a load.

SWITCHING PERFORMANCE

The turnoff transient for a type B SA-ACLIGBT when conduct- ing approximately 100 mA is shown in Fig. 4. As can be seen, a turnoff time of less than 800 ns has been obtained in this case. The

IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 40, NO. IO, OCTOBER 1993 1883

tumoff time for the equivalent SA-LIGBT is 1.08 F S under identical conditions. Measured tumoff transient of all SA-ACLIGBT’s, when a 200 V supply voltage is connected through a resistive load and the gate voltage is switched from 5 to 0 V, is about 60% of that of equivalent SA-LIGBT’s.

CONCLUSION

The SA-ACLIGBT, which incorporates an auxiliary cathode in the drift region of an SA-LIGBT and a p+ buried layer beneath it for JFET-like pinchoff, offers a latchup-free on-state performance compared to the anode-shorted LIGBT. In addition, due to the presence of an additional pnp transistor, the SA-ACLIGBT has a higher bipolar current gain when compared to an equivalent SA- LIGBT. It also shows superior tumoff characteristics due to the presence of the auxiliary cathode.

ACKNOWLEDGMENT

The authors wish to thank J. Humphrey, Dr. K. W. Kwan, C. Star- buck, and Prof. H. A. Kemhadjian of Southhampton University Microelectronics Centre, Southampton, UK, for their valuable sug- gestions and help in fabricating the devices.

REFERENCES

[l] E. M. Sankara Narayanan, G. A. J . Amaratunga, Q. Huang, W. I. Milne, and K. W. Kwan, “A novel modified lateral insulated gate tran- sistor structure,” in Proc. Symp. High Voltage Smart Power ICs, vol.

[2] E. M. Sankara Narayanan, Ph.D. dissertation, Cambridge Univ., 1992. [3] J . A. Appels and H. M. J . Vaes, “High voltage thin layer devices,”

IEDM Tech. Dig., 1979, pp. 238-241. [4] E. M. Sankara Narayanan, G. Amaratunga, and W. I. Milne, “A study

of the RESURF principle for thin layer high voltage integrated cir- cuits,” in Proc. 4th Int. Symp. Power Semiconductor Devices ICs, Tokyo, May 1992, pp. 172-175.

[5 ] Q. Huang, G. Amaratunga, E. M. Sankara Narayanan, and W. I. Milne, “Static CMOS latch-up considerations in HVIC design,” IEEE J. Solid State Circuits, vol. 25, pp. 613-616, 1990.

[6] D. N . Pattanayak, A. L. Robinson, T. P. Chow, M. S. Adler, B. J . Baliga, and E. J . Wildi, “N channel lateral insulated gate transistors: Part I-Steady-state characteristics,” IEEE Trans. Electron. Devices, vol. ED-33, pp. 1956-1963, 1986.

[7] E. M. Sankara Narayanan, G . Amaratunga, W. I. Milne, J . I. Hum- phrey, and Q. Huang, “Analysis of CMOS compatible lateral insu- lated base transistors,” IEEE Trans. Electron Devices, vol. 38, pp.

89-15, 1989, pp. 124-132.

1624-1632, 1991.

A Nonpinchoff Gradual Channel Model for Deep- Submicron MOSFET’s

M. Fujishima and K. Asada

Abstract-A new drain current model for a short channel MOSFET is proposed, which is named the nonpinchoff model. In this model, the effect of horizontal electric field is precisely taken into account to solve the two-dimensional Poisson’s equation. The pinchoff point, where the horizontal electric field tends to be infinity in the conventional gradual-

Manuscript received April 23, 1993; revised May 28, 1993. The review

The authors are with the Department of Electronic Engineering, Univer-

IEEE Log Number 9211175.

of this brief was arranged by Associate Editor S. Furukawa.

sity of Tokyo, 7-3-1 Hongo, Bunkyo-ku, Tokyo 113.

channel approximation, disappears in the nonpinchoff model, so that linear and saturation regions are smoothly connected. As a result, the ambiguity of the boundary between linear and saturation region in a short channel MOSFET can be understood using a single equation for drain current.

NOTATION

effective surface-channel thickness distance from source edge gate-oxide capacitance the coefficient for short channel effect drain current drain current calculated using gradual-channel approxi-

mation gate length gate width total surface charge sheet density surface charge sheet density corresponding to longitu-

threshold voltage gate voltage surface potential permittivity of silicon carrier mobility on low field carrier mobility taking into account transverse field de-

effective mobility; velocity saturation and transverse

coefficient of longitudinal field effect

dinal field difference

pen d e n c e

field dependence are taken into account

I . INTRODUCTION

Models for current-voltage characteristics of MOSFET’s, such as a gradual-channel approximation [ 11, were conventionally de- rived assuming that the boundary of the linear and saturation re- gions is clear [3], [2]. These are reasonable assumptions when MOSFET in the saturation region can be regarded as a constant current source, taking channel-length modulation into account, which is modulation of the distance from the pinchoff point to the drain edge as shown in Fig. 1. However, such a boundary tends to be ambiguous in deep-submicron MOSFET’s, as shown in Fig. 2. Actual surface charge never physically disappears even at a pinchoff point. Moreover, the concept of channel-length modula- tion loses its physical meaning for MOSFET’s on SO1 substrates with nearly nondoped channel [4].

In this brief, we propose a novel nonpinchoff gradual-channel model considering the gradient of horizontal electric field, which is neglected in the conventional model, so that the surface charge does not disappear and the effective channel-length modulation fac- tor in the conventional models is automatically taken into account.

11. NONPINCHOFF MODEL

In the nonpinchoff gradual-channel model, an effective surface- channel thickness is introduced as tCH, as shown in Fig. 3. Al- though Fig. 3 shows the cross section view of a bulk MOSFET, the model can apply for an SOUMOSFET as shown later. Surface charge sheet density Q(x) is then derived as

0018-9383/93$03.00 0 1993 IEEE