CCS Hardware Test and Commissioning Plan

CCS Hardware Test and Commissioning Plan

ECAL Off-Detector Electronics Workshop

7-8 April. 2005

Kostas Kloukinas CERN

7/4/2005 Kloukinas Kostas 2

Overview

CCS Development Status

Production Plan

CCS during Integration and Commissioning


The FEC-CCS System Design satisfy the requirements from:

Tracker ECAL Preshower Pixel RPC

Three components: mFEC: small mezzanine card suitable for VME and PCI utilization. PCI-carrier: motherboard for one mFEC FEC-CCS: VME motherboard for 8 mFECs.

FECtracker = CCSecal*


mFEC & PCI carrier

to facilitate development work

to be used in the lab and test beams.

mFEC on a PCI carrier board


FEC-CCS V2 (Prototype)

VME backplane

ECAL backplane

mFECs

TTC input

VME Interface FPGA

Trigger FPGA


FEC-CCS V3 (Final) V2 to V3 modifications:

Splitting of 1-wire bus for temperature sensors and serial ID chip.

Reassignment of JTAG backplane signals.

QPLL & TTCrx control lines.

Routing of spare FPGA lines at the P2 connector.

One board assembled. Tested O.K.


Prototype Test Status VME to Local Bus interface is O.K..

All 8 mFECs can be and accessed from the VME bus. Conforms to the VME 64x “plug & play” standard. VME Interrupter is tested.

Various Functions Electronic Serial Number tagging using a serial ID chip. Airflow temperature monitoring of the OPTOBAHNs on mFECs

Fast Timing path is tested. TTCrx – Trigger FPGA – mFECs – control rings. Send trigger commands to FE and DCC.

Power consumption (measured) Card fully equipped with 8 mFECs 7A @ 3.3V, 1A @ 5.0V => ~30W dissipated

Pending Issues: TTS signal functionality. DCC-CCS-TCCs integration tests. VME bus JTAG basckplane controller access.


Pre-Production Status FEC-CCS:

Version 1: First prototype. 2 units have been fabricated. Were used in the TRACKER test beam

and in the ECAL test-beam setups (summer 2004).

Version 2: Second prototype. 8 units have been fabricated. All units are tested and fully equipped with mFECs. They are available for distribution.

Version 3: Final version. Pre-production of 10 boards is in progress. 1 unit delivered (11/3) and currently being tested 9 more will be delivered around early April.


FEC-CCS Test Bench XDAQ (HAL) framework

Full plug&play support

Software development by: E. Vlassov F. Drouhin

CERNscientific Linux

>_


Component Traceability

Managing the distribution of FEC-CCS boards.

FEC-CCS Project Website: proj-fec-ccs.web.cern.ch/proj-FEC-CCS


Final Production Tracker: 352 control rings => 44 FEC-CCS boards ECAL: 368 control rings => 46 FEC-CCS boards Preshower: 48 control rings => 20 FEC-CCS boards Pixels: 120 control rings => 16 FEC-CCS boards RPCs: 25 control rings => 4 FEC-CCS boards -----------------------

130 FEC-CCS boards

116 FEC-CCS boards => 930 mFECs 50 PCI FEC boards => 50 mFECs

---------------- 980 mFECs

Spares should be added….


Production Schedule

Production of 900 mFECs is in progress. Production of 140 FEC-CCS boards to start soon.

All components have been procured PCB manufacturing and assembly companies found.

Production Testing Will be done at CERN Test bench and test procedures are currently under development.


Integration & Commissioning

FEC-CCS board should facilitate:

Front-End system testing & debugging.

Possibility to run DCC-CCS-TCC(s) standalone.

Enable data taking when LTC-TTCci system is unavailable.


Final System TTC/TTS signal paths

Contr

olle

r

LTC

TTC

ci

Global Trigger Controller

Local Triggers

TTCTTS

TTCmi

Contr

olle

r

FMM

FMM

TTC

ci

TTC

ex

TTC

ci

TTC

ci

TTC

ci

TTC

ex

TTC

ci

TTC

ci

TTC

ex

TTC

ci

CCS CCS CCS

Con

trol

ler

DC

C

TC

C

DC

C

TC

C

DC

C

TC

C

DC

C

TC

C

TTS

CCS

TTC


FEC-CCS during Integration When final System is not yet available / operational

Requirements: Enable Slow Control for the FE electronics. Generation of Local Trigger Commands and

their distribution to the FE and to the OD electronics. Off-Detector electronics (DCC, TCCs) synchronization

at the level of one supermodule.

Implementation: Hardware

Interface with external signals to synchronize internal operations.

Firmware Trigger FPGA functionality to allow the generation

and distribution of the Local Trigger Commands.

Software To support these functionalities.


FEC-CCS Block Diagram Support for 1~8 control rings

per board.

VME 9U board.

VME64x compatible.

Control information passes through the VME bus.

Fast Timing Signals passes through the TTC link.

VMEinterface

FPGA

mFEC

mFEC

mFEC

mFEC

mFEC

mFEC

mFEC

mFEC

TTCrx

QPLL

Local Bus

Fast

Tim

ing

sig

nals

JTA

G

ECAL TTC/TTS bus

VMEbus

TTC link

TriggerFPGA

External I/O


FEC-CCS Piggy Back Board

Prepared by Mark Dejardin

ECAL Test Beam Summer 2004

Trigger FPGA logic.


FEC-CCS Multi I/O board

As a replacement of the Piggy Back I/O board.

Propose to build a 3U Rear VME Backplane Transition Board

Connects on spare Trigger FPGA lines.

Only FEC-CCS V3supports this card.

LVTTL I/O

NIM I/O4 IN4 OUT 1 clock in1 clock out(+ 4 IN/OUT spares)

LVTTL to NIM

NIM to LVTTL

VM

E R

J2 c

onnect

or


Trigger FPGA firmware design

Local Businterface

&Control

Registers

Trigger CommandManager

QPLL

Clk40_L1to mFECs

TTC Encoder

CCSLocal Bus

TTC signalto DCC/TCCs

TTCrx

40MHz

160MHz

Clk40

Clk40_L1

Clk40

NIM to TTLTTL to NIMtranslators

IN

OUT

CCS Clock

Piggy Back Board

Trigger FPGA

80MHz

Clk80

Clk40 Clk160

4

4

Token Ring Clock Encoder

L1

110101111

L1

B<7:0>

TTCRX_RDY

TTC in

BRCST<7:2>

L1ACCEPT


Trigger Command Manager (1/4) FEC-CCS modes of operation

REMOTE: Trigger Commands as received from the TTCrx chip

are being distributed to Token Rings and the ECAL backplane. Used for Normal Data Taking operation.

LOCAL: Allow the generation of Local Trigger commands. Used for system debugging.

Mode Selection Auto

Remote/Local selection is automating depending on the status of the TTCRX_RDY signal.

Forced LOCAL User selection


Trigger Command Manager (2/4)

Trigger Command Assignments on the Token Rings are not common between subsystems.

The FE ASICs decode these commands in a fixed manner.

Mapping of TTC B channel commands to Token Ring Trigger Commands can be done by a LUT in the Trigger FPGA.

B-Go commandTTC Brcst<5:2> Function T Ring Function T Ring Function T Ring Function T Ring Function T Ring Function

1 0000 Not Used2 0001 BC0 101 BC0 101 BC02 0010 TestEnable TEST_ENABLE3 0011 PrivateGap4 0100 PrivateOrbit5 0101 ReSync 101 RESYNC 110 ReSync 110 ReSync 101 ResetTBM6 0110 HardReset RESET7 0111 ResetEventCounter 111 ResetROC8 1000 ResetOrbitCounter Send9 1001 Start

10 1010 Stop11 1011 Free1 110 APV_CALIBRATE 111 Monitoring 111 CalPulse 110 CalSync12 Free213 Free314 Free415 Free516 Free6

100 L1 100 L1 100 L1 100 L1

EVcntRes

TTCrx signal

RPCs

BcntResL1ACCEPT

TRACKER ECAL Preshower PIXEL

LUT

SSID

BRCSTR1

BRCST<5:2> RE

G TTC_B110B

TTC_B101B

TTC_B111B

TTC

fro

m T

TC

rxTTC_L1ACCEPT

Mapping of TTC B channel commands to Token Ring Trigger Commands


Trigger Command Manager (3/4) Generation of Local Trigger commands

Local L1 Trigger Command.

Delay (0-255)

LOC_B110B

LOC_B110B_delayed

LOC_B101B

LOC_B101B_delayed

LOC_B111B

LOC_B111B_delayed

GEN1

GEN2

Internal

EN1

Soft

EN2

External

EN0

Ext_IN1

Ext_IN2

Ext_IN3

Ext_IN4

SEL0

SEL1

TTCrx

EN3

Counter(16-bit)

COUNT_in

COUNT_out

LOC_L1_delayed

LOC_L1

LOC_L1

L1ACCEPT

End of Count

Ext_IN1

Ext_IN2

Ext_IN3

Ext_IN4

SEL2

Sync

End Of Count

Send

LOC_L1 command channel

Exter

nal s

igna

ls

Inte

rnal

sig

nals

Exter

nal s

igna

ls


Trigger Command Manager (4/4)

Frequency Generator 1F

req

1

GEN1

Frequency Generator 2F

req

2

GEN2

OUT1_delayed

OUT1OUT1

OUT2_delayed

OUT2OUT2

EXT_IN

LOC_L1LOC_B110BLOC_B101BLOC_B111B

GEN1TTC_X1

EXT_IN

LOC_L1LOC_B110BLOC_B101BLOC_B111B

GEN2TTC_X2

to E

xte

rna

l Out

pu

ts

LOC_B110B_delayed

LOC_B110BB110B

LOC_B101B_delayed

LOC_B101BB101B

LOC_B111B_delayed

LOC_B111BB111B

EXT_IN

LOC_L1LOC_B101BLOC_B111B

GEN1GEN2

TTC_110

EXT_IN


GEN1GEN2

TTC_101

EXT_IN


GEN1GEN2

TTC_111

B_command_send

B_command

ETTC

LOC_B110BLOC_B101BLOC_B111B

Soft _B_command

RLUT

SEL0

SSID

LUT

SSID

BRCSTR1

BRCST<5:2> RE

G TTC_B110B

TTC_B101B

TTC_B111B

TTC

LOC_L1_delayed

LOC_L1LOC_L1EXT_IN

LOC_B110BLOC_B101BLOC_B111B

GEN1GEN2

TTC_L1ACCEPT SEL3

TTC_L1ACCEPT

LOC_L1

LOC_L1_delayedL1

SEL7

TTC_B110B

LOC_B110B

LOC_B110B_delayedB110B

SEL11

TTC_B101B

LOC_B101B


SEL15

TTC_B111B

LOC_B111B


to T

oke

n R

ing

En

cod

er

to T

TC

En

cod

er

fro

m T

TC

rx

TTC_L1ACCEPT L1


Wrap Up

Flexible and configurable logic allows for: Single shot commands. Single shot Bursts of commands. Sequence of multiple commands. Periodic Sequence of multiple commands. Synchronization with external signals.

Generic design The Integration Physicist/Engineers can modify the Trigger

Generation logic as required for their setup. Other sub systems could possibly utilize these functionalities Easy firmware maintenance. Unique version for all subsystems.

Comments & Discussion…..


Backup Slides


Piggy-Back PCB

R. Benetta, M. Dejardin


FEC-CCS Piggy Back I/O board

by Mark Dejardin

Prepared for the ECAL Test Beam in Summer 2004.


Trigger FPGA Registers

Availa

ble o

nly fo

r the

ECAL Test

Beam

sum

mer 2

004


Trigger FPGA design

Local Businterface

&Control

Registers

ECALLocal TriggerManagement

Logic

Trigger InsertionLogic

QPLL

Clk40_L1to mFECs

Clock ManagementLogic

CCSLocal Bus

TTC signalto DCC

TTCrx40MHz

160MHz

Clk40 Clk40_L1

Clk40Clk40 Clk40_L1

NIM to TTLTTL to NIMtranslators

BOB

EOB

Laser In

TDC Start

TDC Stop

Laser Out

Loc L1

CCS Clock

Piggy Back Board

Trigger FPGA


Overview of CCS Board

TTCrx

OptoRX

TTS/

TTCbus

FPGA

QPLL

TTC_clk

E_TTC_clk

mFEC

VMEbus

mFEC

mFEC

mFEC

mFEC

mFEC

mFEC

mFEC

40MHz

160MHz

CLK40

CLKL1ACC

CLK+T1

FPGA

B channel


FEC-CCS Production Testing

Production Testing will be done at CERN Separate Test Benches:

For the mFECs will be PC based. Using PCI carrier boards.

For the FEC-CCS boards will be VME based. Hardware needed:

PCI bus, preferably allowing hot plug-in. TTC/TTS backplane driver board. TTCvi or TTCci .

Software needed PC software for mFEC testing Linux software for FEC-CCS testing.

CCS Hardware Test and Commissioning Plan

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