Carrier Recovery and Automatic Gain Control on FPGA’s based platform

(IEEE 802.15.3c mm-Wave PHY Application)

Khaled Sobaihi, Akram Hammoudeh, David Scammell Faculty of Advanced Technology

University of Glamorgan, Pontypridd, UK Email: {ksobaihi, amhammou, dscammel}@glam.ac.uk

Abstract— recently the standardisation of the large unlicensed millimetre wave band (Oxygen absorption zone around 60 GHz) has been completed and published under the IEEE 802.15.3c standard, to enable multi-Gigabit data rate Wireless Personal Area Network (WPAN).

To achieve such data-rate, a new physical PHY layer totally different from the conventional WPANs has been defined. The published IEEE 802.15.3c PHY layer introduces new preamble and payload frame structures that need new signal processing mechanisms at the receiver side.

This paper introduces an efficient implementation of the Carrier Recovery and Automatic Gain Control (AGC) for an IEEE 802.15.3c compliant receiver developed using a Field-Programmable Gate Arrays (FPGAs) and a Software Defined Radio (SDR) platform.

Index Terms— Automatic Gain Control, Carrier Recovery,

Costas Loop, FPGAs, IEEE 802.15.3c, Software Defined Radio.

I. INTRODUCTION The IEEE 802.15.3c defines three operating modes and a

common mode allowing different PHY layers to communicate. The single carrier (SC PHY) mode for low-power and low-cost applications uses Single Carrier Block Transmission (SCBT). The SC PHY supports operation in NLOS as well as LOS, with or without Single Carrier Frequency Domain Equalization (SC-FDE). The High Speed Interface (HSI PHY) mode is designed for bidirectional high-speed data-rates using Omni-directional antennas and orthogonal frequency-division multiplexing (OFDM) with forward error correction (FEC). The third PHY is Audio/Visual (AV PHY), which has two PHY modes, the high-rate PHY (HRP) and low-rate (LRP), both of which use the OFDM transmission and Forward Error Correction (FEC) based on Convolution Code, to transmit uncompressed HD video streaming. [1].

Software-Defined Radios (SDRs) are highly reconfigurable hardware platforms that provide the technology to realize many sophisticated signal processing tasks, including channel estimation, equalization and synchronization. Therefore, SDRs play a key role in the new generation wireless transceivers resulting in significantly more complex designs with respect to traditional modems. Field programmable gate arrays (FPGAs) are an attractive option for the

implementation of those tasks for reasons of performances, power consumption and configurability [2][3][4].

II. SOFTWARE DEFINED RADIO ARCHITECTURE Fig 1 shows a common super-heterodyne transmitter and

receiver SDR architecture. The SDR front-end consists of the standard analogue devices used in conventional transceivers: filters, frequency up/down converters, power amplifiers (PAs), low noise amplifiers (LNAs), etc.... At the receiver, the received signal is passed through a band pass filter, before being down converted to an intermediate frequency and amplified. It is then demodulated through a quadrature demodulator to I-Q baseband paths, filtered, amplified and converted to the digital domain.

The Analogue to Digital Converters (ADCs) and Digital to Analogue Converters (DACs) interface the analogue RF front ends to the digital part, implemented on reconfigurable platform

Digital Domain

ADC

ADC

DAC

DAC

LNA

PA

Reconfigurable platform

FPGAs, DSPs

Modulation Demodulation Channel coding OFDM TDM FDM CDMA

90°

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LO

90°

LO

LPF

LPF

LPF

LPF

I

Q

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Tx

LO

BPF

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Figure 1 Software defined radio architecture

that consists of FPGAs, DSPs or both. Signal processing functions encapsulated in either PHY layer or medium access control (MAC) layer include: Modulation/Demodulation, Coding, OFDM, Time Division Multiplexing (TDM) and communication protocol of a wireless WLAN/WPAN are executed on FPGAs or DSPs. The SDR platform is able to adapt itself to the transmission scenario with any modulation scheme, channel coding predefined in the wireless standard.

I. GOLAY COMPLIMENTRY CODES Recently the orthogonal Golay complementary sequences

have been proposed in the third cellular and WLANs standards, to be used in the preamble for synchronization and channel estimation. The Golay complimentary sequences have an attractive property that the sum of their a-periodic auto-correlation functions equals to zero for all nonzero time shifts, in other words, the sum of their auto-correlations has maximum peak and no side-lobe. [6][7].

Let 𝑎𝑁(𝑖) and 𝑏𝑁(𝑖) be the pair of complementary Golay sequences for 𝑖 = 0, … .𝑁 − 1 with 𝑁 = 2𝑀 of length, and 𝑅𝑎, 𝑅𝑏 the auto-correlation of 𝑎𝑁 and 𝑏𝑁 respectively. The Golay sequences are defined by the following auto-correlation property:

𝑅𝑎(𝑖) + 𝑅𝑏(𝑖) = �2𝑁𝛿(𝑖), 𝑖 = 00, 𝑖 ≠ 0

� (1)

𝛿(𝑖) is the Kronecker delta function. Fig 2 shows the cross-correlations of aN, bN and the sum of those cross-correlations. The auto-correlation of 𝑎𝑁(𝑖) and 𝑏𝑁(𝑖) sequences are as follow:

𝑅𝑎(𝑖) = � 𝑎𝑁(𝑘)𝑎𝑁∗ (𝑘 + 𝑖)𝑁−𝑖−1𝑘=0 (2)

𝑅𝑏(𝑖) = � 𝑏𝑁(𝑘)𝑏𝑁∗ (𝑘 + 𝑖)𝑁−𝑖−1𝑘=0 (3)

Figure 2 Cross-correlation of an, bn and their sum

The construction of the complementary Golay sequences is defined by the recursive relation:

𝑎0(𝑘) = 𝛿(𝑘)𝑏0(𝑘) = 𝛿(𝑘)𝑎𝑛(𝑘) = 𝑎𝑛−1(𝑘) + 𝑊𝑛𝑏𝑛−1(𝑘 − 𝐷𝑛)𝑏𝑛(𝑘) = 𝑎𝑛−1(𝑘) −𝑊𝑛𝑏𝑛−1(𝑘 − 𝐷𝑛)

(4)

Where n represents the iteration number and 𝑛 = 1,2 …𝑁, 𝐷𝑛 is a delay and 𝐷𝑛 = 2𝑃𝑛, 𝑃𝑛 is any permutation of {0, 1, 2 …𝑁 −1}, 𝑊𝑛 is an arbitrary complex number of unit amplitude. When 𝑊𝑛 have values +1 and -1, the binary Golay complementary sequences is obtained [6].

An efficient matched filter directly related to the sequences {𝑎𝑁,𝑏𝑁} generated by eq.4 is given in Fig 3. This matched filter performs simultaneously the correlation of the input signal 𝑥(𝑘) with the two complementary sequences {𝑎𝑁(𝑘),𝑏𝑁(𝑘)} , the two outputs produce the two corresponding to the aperiodic cross-correlation functions {𝑅𝑎(𝑘),𝑅𝑏(𝑘)}. Such digital matched filter is called an Efficient Golay Correlator (EGC) [6].

For binary Golay sequences of length 2𝑀 , the number of multiplications and additions equal to log2 𝑀 and 2 log2 𝑀 respectively, while in straightforward matched filter implementation it would be M and M-1 respectively. The number of delay elements required for both EGC and straightforward matched filter are the same and equals to 𝑀− 1 [6].

II. SC PHY FRAME FORMAT

III. SC PHY FRAME FORMAT Fig 4 shows the proposed frame format for the IEEE

802.15.3c standard. A PHY preamble shall be added at the head of the payload frame to aid receiver algorithms related to automatic gain control (AGC), timing acquisition, carrier recovery, frame synchronization and channel estimation. The payload frame contains blocks of data separated by a cyclic-prefix (CP) [1].

The Frame synchronization (SYNC) field is used for frame detection and uses 14 repetitions of a128 Golay code (128 samples length Golay code). Start frame delimiter (SFD) is used to establish frame timing and header rate, and consists of [a128 -a128 a128 -a128] or [a128 a128 -a128 -a128] for high rate or medium rate respectively. The CES field, used for channel estimation consists of [a256 b256 a256 b256 b128].

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Correlation with an

Correlation with bn

ZD1 ZDn-1

Figure 3 Efficient Golay Correlator (EGC)

IV. PRO DESIGN

V. PROPOSED DESIGN Fig 5 presents the block diagram of the proposed schematic

that integrates the carrier recovery and automatic gain control. Both AGC and the carrier recovery are based on the feedback scheme. The preamble detector activates/deactivates the AGC and the carrier recovery when the preamble sequences are present.

VI. PREAMBLE DETECTOR

VII. PREAMBLE DETECTOR Fig 6 illustrates the data flow diagram of the preamble

detector, Efficient Golay Correlator (EGC) of length equals to 128 samples are used to generate picks correspond to each ‘A128’ Golay sequence. The output of the EGC is auto-correlated and averaged over the length of the sequence (L = 128) with the following formulas:

𝑅𝑛 = 1𝐿∑ 𝑟𝑘. 𝑟𝑘+𝐿∗𝑛+𝐿−1𝑘=𝑛 (5)

Fig 7 shows the signal plot of the auto-correlation of the Golay sequences, averaged over sequence’s length. This signal is compared to threshold to validate the presence of the SYNC part of the preamble.

Figure 7 Preamble Detection Signals

VIII. AUTOMATIC GAIN CONTROL In order to keep the received baseband signal close to a

desired power and provide a processable signal level to the next stages, the Automatic Gain Control (AGC) is employed in both parts (Analogue and digital parts), the analogue AGC is used to keep the signal level within the dynamic range of the ADC. In this paper, only the digital AGC will be analyzed and implemented on a FPGA platform. The proposed AGC doesn’t require complex mathematical functions like division, logarithm or exponential etc..., which makes it suitable for FPGA implementation.

Fig 8 shows the detailed AGC schematic, the output power is

calculated using multiplication and addition operations then smoothed through an N-length moving average filter using the formula:

𝑃𝑛� = 1𝑁∑ 𝑃𝑖𝑖=𝑛+𝑁𝑖=𝑛 = 1

𝑁[𝑃𝑛 + 𝑃𝑛−1 − 𝑃𝑛−𝑁−1] (6)

Where 𝑃𝑛 = 𝐼𝑛2 + 𝑄𝑛2

The estimated power is compared with a reference power to generate an error signal that increments/decrements the gain accumulator with a factor of 2-k (easily realizable with kth right

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Carrier Recovery

Preamble Detector

Figure 5 AGC and Carrier Recovery loops

Figure 6 Data Flow Diagram of Preamble Detector

Figure 4 SC PHY IEEE 802.15.3c proposed frame structure

Figure 8 Proposed Digital AGC Schematic

shift operation). When the output is locked to reference power PREF, the output power fluctuates around the locked value by:

∆𝑃𝑃𝑛

= 𝑃𝑛−𝑃𝑛−1𝑃𝑛

≅ �12�𝐾−1

(7) The dynamic range of the AGC depends on the dynamic

range of the gain accumulator (number of bits of the accumulator), if the width of the accumulator is B the dynamic range in dB equals to:

DRdB = 10 log(2B − 2K−1) ≅ 7(B − K + 1) (8)

IX. CARRIER RECOVERY A carrier (Frequency) recovery system accomplishes two

basic functions: it derives an estimate of the carrier frequency offset ∆𝑓 then it compensates for this offset by counter-rotating the received signal at an angular speed 2𝜋∆𝑓 [10].

Fig 9 shows the implemented carrier recovery, scheme

which is based on the classical Costas Loop where it consists of three main parts:

A. Phase Detector This is the key component of the carrier recovery; the

structure of this detector is relevant to the preamble of the Fig 4, which is 𝜋

2𝐵𝑃𝑆𝐾 modulated. The phase error is calculated

through the equation:

𝜖𝑘 = 𝐼𝑘 ∙ 𝑠𝑖𝑔𝑛(𝐼𝑘) − 𝑄𝑘 ∙ 𝑠𝑖𝑔𝑛(𝑄𝑘) (9)

B. Loop Filter The loop filter plays a critical role in the feedback carrier

recovery. To ensure the stability of the loop and eliminate any noise or glitches, the general proportional and integral filter is used with transfer function in Z-domain:

𝐻𝑍 = 𝐾𝑝 + 𝐾𝑖1

1−𝑍−1 (10)

C. Numerically Controlled Oscillator (NCO) The role of the NCO is to generate a countering angle to

compensate any frequency offset at the receiver, Fig 10 illustrates a digital NCO structure; the output can be expressed as:

𝑋𝑛𝑐𝑜𝑘 = 𝐴𝑛𝑐𝑜𝑒𝑗(2𝜋𝑓𝑛𝑐𝑜𝑘𝑇−𝜑�) (11)

Where Anco, fnco and T are Amplitude, frequency and sampling period of the NCO. Where 𝜑� the estimated frequency offset.

X. FPGA PROTOTYPING For the rapid FPGA prototyping of the design, the Xilinx

System Generator for Matlab Simulink is used. Design is captured in the DSP friendly Simulink modeling environment using a Xilinx specific block set. All of the downstream FPGA implementation steps including synthesis and place and route are automatically performed to generate an FPGA programming file.

The design starts by fixed-point simulation and validation using Simulink as the modeling interface. Once the design is verified and validated, it is translated into efficient HDL code along with the integration of the Intellectual Property Cores (IP Cores) before synthesis, place and route for the FPGA.

The implementation of the whole receiver including the AGC, Carrier Recovery and Matched Filter has been performed on Xilinx XtremeDSP Developement Kit, the main features of this development board are:

a. Virtex-4 XC4VSX35 main FPGA, b. 2 Channels ADC (14-bits up to 105 MSPS), c. 2 Channels DAC (14-bits up to 160 MSPS).

TABLE I. FPGA RESOURCES USED FOR THE AGC

Device Utilisation Summary Virtex4 xc4vsx35-10ff668

Resources Used Available Utilisation Flip flops Slices DSP48s

210 159

2

30,720 15,360

192

1% 1% 1%

TABLE II. FPGA RESOURCES USED FOR THE CARRIER RECOVERY

Device Utilisation Summary Virtex4 xc4vsx35-10ff668

Resources Used Available Utilisation Flip flops Slices DSP48s

223 173

2

30,720 15,360

192

1% 1% 1%

Table I and II show the amount of the resources used for the AGC and Carrier recovery respectively. The AGC has been designed with a 32 bit gain accumulator and data path, K equal to 3 and a moving average performed over 16 samples, the simulation and the implemented design demonstrate a large dynamic range of +100dB.

In the implementation of the carrier recovery the Xilinx IP core is used to implement the NCO block, the multiplications

Sin and Cos Lookup table ∆ϕ

Sin(ϕ)

Cos(ϕ)

Z-1

Phase Accumulator

Mod 2π

Matched Filter In Out

Phase Detector

Z-1

Loop Filter

NC

O

I

Q

+

-

Ki

Kp

Figure 9 Costas Loop Based Carrier Recovery

Figure 10 Numerically Controlled Oscillators (NCO)

done in the loop filter are replaced with shift operations, whereas the embedded multipliers are used in the phase detection, resulting in a large saving of resources and an improvement in precision. Fig 11 and 12 show the implemented design of the AGC and Carrier Recovery respectively using Xilinx System Generator.

Figure 11 System Generator of the AGC Schematic

Figure 12 Carrier Recovery Schematic

XI. HARDWARE TESTING The implemented receiver has been tested with a 62.4 GHz

wireless radio system; the bandwidth of the transmitted signal is 50MHz with 16-QAM modulation, shaped with a root raised cosine filter of 0.5 roll-off factor. The bit-rate achieved is 100Mbps. Fig 13 shows the theoretical and the measured Bit Error Rate (BER) versus the estimated Signal to Noise Ratio (SNR). The BER measurement has been performed in rectangular room with a geometry shown by Fig 14. The transmission is line of sight with the transmitter and receiver 4m apart and uses horn to horn antennas. Thus, realizes a quasi-Additive White Gaussian Noise (AWGN) channel.

XII. CONCLUSION This paper proposed the design and the implementation of

an optimized AGC and carrier recovery suitable for SDR receiver based on the IEEE 802.15.3c Millimeter-Wave (mm-Wave) standard on the Virtex 4 FPGA. In these designs minimum resources are used by avoiding complex operations, instead shift operations are used, a good performances versus complexity has been achieved and verified in real mm-Wave wireless radio link. BER measurement for different estimated SNRs. performed in rectangular room, for SNR above 10 db those measurements are comparable to theoretical BER.

Figure 13 Theoretical and Measured BER vs. SNR for 16-QAM Transmission

REFERENCES [1] IEEE 802.15.3c Standard - “Wireless Medium Access Control (MAC) and

Physical Layer (PHY) Specifications for High Rate Wireless Personal Area Networks (WPANs) Amendment 2: Millimetre-wave-based Alternative Physical Layer Extension”, IEEE Oct. 2009

[2] Cruz P, Carvalho N.B, Remley K. “Designing and Testing Software-Defined Radios” IEEE Microwave Magazine, June 2010.

[3] Dick C, Harris F, Rice M. “Synchronization in software radios. Carrier and timing recovery using FPGAs” IEEE Symposium on Field-Programmable Custom Computing Machines, 2000, pp. 195

[4] Hen-Geul Yeh, Ingerson P. “Software-defined radio for OFDM transceivers”, 4th Annual IEEE Systems Conference, 2010, pp 261

[5] Shono T, Shirato Y, Shiba, H, Uehara K, Araki K, Umehira M. “IEEE 802.11 wireless LAN implemented on software defined radio with hybrid programmable architecture”, IEEE Transactions on Wireless Communications, Vol 4, Sept. 2005

[6] Popovic B.M. “Efficient Golay correlator”, Electronics Letters, Vol 35, pp. 1427-1428, 1999

[7] Budisin S.Z. “Efficient pulse compressor for Golay complementary sequences” Electronics Letters, Vol 27, pp. 219, Jan. 1991

[8] Kimura, R. ; Funada, R. ; Nishiguchi, Y. ; Ming Lei ; Baykas, T. ; Chin-Sean Sum ; Junyi Wang ; Rahman, A. ; Shoji, Y. ; Harada, H. ; Kato, S. “Golay sequence aided channel estimation for millimeter-wave WPAN systems” IEEE 19th International Symposium on Personal, Indoor and Mobile Radio Communications, 2008.

[9] Chonghoon K, Sungbin I. “Digital automatic gain control for software radio W-CDMA base stations” Electronics Letters, Vol 39, pp 318-320, Feb 2003.

[10] Umberto M, Aldo N.D. “Synchronization Techniques for Digital Receivers” New York, Plenum Press, 1997.

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Figure 14 Measurement Geometry of the Rectangular Room