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The Memory/Logic Interface in FPGA’s with Large Embedded Memory Arrays The Memory/Logic Interface...
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Transcript of The Memory/Logic Interface in FPGA’s with Large Embedded Memory Arrays The Memory/Logic Interface...
![Page 1: The Memory/Logic Interface in FPGA’s with Large Embedded Memory Arrays The Memory/Logic Interface in FPGA’s with Large Embedded Memory Arrays Steven J.](https://reader031.fdocuments.us/reader031/viewer/2022032310/56649d6b5503460f94a49fa3/html5/thumbnails/1.jpg)
The Memory/Logic Interface in FPThe Memory/Logic Interface in FPGA’s with Large Embedded MemGA’s with Large Embedded Mem
ory Arraysory Arrays
Steven J. E. Wilton, Member, IEEE, Jonathan Rose, Member, IEEE,
and Zvonko G. Vranesic, Senior Member, IEEE
Laboratory of Reliable ComputingDepartment of Electrical EngineeringNational Tsing Hua UniversityHsinchu, Taiwan
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ReferenceReference S. J. E. Wilton, “Architectures and algorithms f
or field-programmable gate arrays with embedded memory,” Ph.D. dissertation, Dept. Elect. Comput. Eng., Univ. Toronto, Toronto, Ont., Canada, 1997.
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OutlineOutline Introduction
Baseline architecture
Experiment methodology and result
Enhanced architecture and its improvement
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IntroductionIntroduction In the past, FPGA’s have been primarily used t
o implement small logic subcircuits As the capacities of FPGA’s grow, they will be
use to implement much larger circuits than ever before
In order to address the storage requirement of large system, FPGA with large embedded memory arrays are now developed by many vendors
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IntroductionIntroduction One of the challenges when embedding memory
arrays into FPGA is to provide enough interconnect between memory arrays and logic resources
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Baseline ArchitectureBaseline Architecture
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Memory/Logic Interconnect BlockMemory/Logic Interconnect Block
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Benchmark Circuit GenerationBenchmark Circuit Generation Need to generate benchmark circuit for the arc
hitecture because Typical circuits have only a few memories each To gather hundreds of those is not feasible
The solution is to study the types of memory configuration found in systems, and develop a stochastic memory configuration generator Make sure they are realistic by some circuit analysis
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Circuit Analysis Circuit Analysis Memory configuration
Logic memory clustering
Interconnect patterns Point to point patterns Shared-connection patterns Point to point with no shuffling patterns
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Memory ConfigurationsMemory Configurations 171 circuits with total of 268 user memories, th
ey are from Recent conference proceeding Recent journal articles Local designer Customer study conducted by Atera
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Memory ConfigurationsMemory Configurations
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Logic Memory ClusteringLogic Memory Clustering
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Interconnect PatternsInterconnect Patterns
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Stochastic Circuit GenerationStochastic Circuit Generation A stochastic circuit generator is developed using the st
atistics gathered during circuit analysis The steps of generating a benchmark circuit
Choosing logical memory configuration Division logical memories into cluster Choosing interconnect pattern for each cluster Choosing number of data-in data-out subcircuits for the c
lusters Generate logic subcircuits and connect them to memory a
rrays
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Implementation ToolImplementation Tool Each benchmark circuit generated is
“implemented” in each FPGA Logical to physical mapping Placement
Place memory and logic blocks simultaneously Routing
Initially nets to memory have higher priority Between each iteration the nets are reordered Repeat 10 times Increase W Determine the minimum value of W
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Memory/Logic Flexibility ResultMemory/Logic Flexibility Result
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Memory/Logic Flexibility ResultMemory/Logic Flexibility Result
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Area ResultArea Result The area of the FPGA is the sum of
Logic blocks Memory blocks Routing resources
Programmable switch Programming bits Metal routing segments
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Area ResultArea Result
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Delay ResultDelay Result A delayed model is used to measure the memory
read time of all memories in the circuit CACTI: to estimate array access time Elmore: address in and data out
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Delay ResultDelay Result
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IssuesIssues Nets connect more than one memory block to
one or more than one logic block When combining the small memory arrays to
implement a large one When data in pins of several user memories are
driven by a common data bus
Such nets often appear but unfortunately they are hard to route, especially for larger architecture
We can use higher value of Fm for larger architecture or?
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Further InvestigationFurther Investigation
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Enhanced ArchitectureEnhanced Architecture The above motivates them to study memory to
memory connection more closely An enhanced architecture
Adding extra switches between memory arrays to support these nets
Result Extra switches take up negligible area Improvement in both speed and routability
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Enhanced ArchitectureEnhanced Architecture
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Baseline ArchitectureBaseline Architecture
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Enhanced ArchitectureEnhanced Architecture
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Evaluation of Enhanced ArchitectureEvaluation of Enhanced Architecture Maze routing algorithm must be restricted such
that it uses memory-to-memory switches only to implement memory-to-memory connection
If the maze router is not modified…
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Routing Result Using Standard MazeRouting Result Using Standard Maze
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Routing Result Using Standard MazeRouting Result Using Standard Maze
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Modified MazeModified Maze Even though some tracks will be wasted if a
circuit contains no or few memory-to-memory connections, it alleviates the problem above
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Area ResultArea Result
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Area ResultArea Result
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Delay ResultDelay Result
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ConclusionConclusion Even with this relatively unaggressive use of the
memory-to-memory switches, area is improved somewhat and speed is improved significantly
The development of algorithms that use these tracks more aggressively is left as future work
The enhanced architecture reduces the channel width by 0.5~1 tracks, and improved the speed by 25%