Session 6

BiTS Workshop 2013 Archive

AND, AT THE WAFER LEVEL

For many in the industry, performing final test at the wafer level is still a novel idea. While providing some much needed solutions, it also comes with its own set of challenges. The four papers in this session look at wafer-level test from a number of different perspectives. The first one discusses the mechanical and electrical differences between wafer-level probe and wafer-level test using spring pins, focusing on requirements for performing final test at the wafer-level. The second presentation provides a comparison between traditional probe test for an RF wafer level chip scale package (WLCSP) and a final test socket solution. TSV issues lead our third author to share technologies that can bridge between 3D stacking and the 3D IC  without  TSVs.  Finally,  we’ll  gain  insight  into  what  some  consider  the  holy grail of burn-in and test – wafer-level burn-in  (WLBI).  Now  that  WLBI   is  possible,   it’s   important   to  understand  when  it’s  appropriate  to  consider  WLBI  versus  other  burn-in alternatives.

Spring Probes and Probe Cards for Wafer-Level Test Jim Brandes—Multitest

A Comparison of Probe Solutions for an RF WLCSP Product James Migliaccio—RF Micro Devices

Bridging Between 3D and 3D TSV Stacking Technologies Belgacem Haba, Ph.D.—Invensas

Wafer-Level Burn-in Decision Factors Steve Steps—Aehr Test Systems

COPYRIGHT NOTICE The paper(s) in this publication comprise the Proceedings of the 2013 BiTS Workshop. The content reflects the opinion of the authors and their respective companies. They are reproduced here as they were presented at the 2013 BiTS Workshop. This version of the papers may differ from the version that was distributed in hardcopy & softcopy form at the 2013 BiTS Workshop. The inclusion of the papers in this publication does not constitute an endorsement by BiTS Workshop, LLC or the workshop’s  sponsors.

There is NO copyright protection claimed on the presentation content by BiTS Workshop, LLC. (Occasionally a Tutorial and/or TechTalk may be copyrighted by the author). However, each presentation is the work of the authors and their respective companies: as such, it is strongly encouraged that any use reflect proper acknowledgement to the appropriate source. Any questions regarding the use of any materials presented should be directed to the author(s) or their companies.

The  BiTS  logo  and  ‘Burn-in  &  Test  Strategies  Workshop’  are  trademarks  of  BiTS  Workshop,  LLC.  All  rights  reserved.

This Paper

2013 BiTS Workshop ~ March 3 - 6, 2013

Paper #31

And, at the Wafer Level

Session 6

Bridging Between 3D and 3D TSV Stacking

Technologies

2013 BiTS WorkshopMarch 3 - 6, 2013

Belgacem Haba, Ph.D.Invensas

Conference Ready 2/11/2013

Content• Introduction• DRAM Application• Package on Package Application• Summary

3/2013 Bridging Between 3D and 3D TSV Stacking Technologies 2

2013 BiTS Workshop ~ March 3 - 6, 2013

Paper #32

And, at the Wafer Level

Session 6

Packaging evolution

3/2013 Bridging Between 3D and 3D TSV Stacking Technologies 3

Die Stacking

Package Stacking

BGATSV die stacking

Packaging evolution

3/2013 Bridging Between 3D and 3D TSV Stacking Technologies 4

Die Stacking

Package Stacking

BGATSV die stacking

2013 BiTS Workshop ~ March 3 - 6, 2013

Paper #33

And, at the Wafer Level

Session 6

Content• Introduction• DRAM Application• Package on Package Application• Summary

3/2013 Bridging Between 3D and 3D TSV Stacking Technologies 5

M U

nits

DRAM Challenge: 2012-2017

DRAM Growth:

Source: Gartner, DeDios

3/2013 Bridging Between 3D and 3D TSV Stacking Technologies 6

2013 BiTS Workshop ~ March 3 - 6, 2013

Paper #34

And, at the Wafer Level

Session 6

Design Challenge:Shrink the Board to Increase

Battery Size & Life

SSD DRAMFAN

Denser: 䇾Ultra-Book䇿 Memory Form-Factor

DRAM

3/2013 7Bridging Between 3D and 3D TSV Stacking Technologies

Dual Die DRAM Package Structures

Opposing-Face DDP

Face-Up DDP with RDL

Face-Up DDP with FOW

Dual Face Down (DFD)

3/2013 Bridging Between 3D and 3D TSV Stacking Technologies 8

2013 BiTS Workshop ~ March 3 - 6, 2013

Paper #35

And, at the Wafer Level

Session 6

DFD Photos11.5 mm square

3/2013 9Bridging Between 3D and 3D TSV Stacking Technologies

RDL QDP Structures: Spacer and Stairstep

Stair step QDP

(no spacers)

RDL QDP(with

spacers)

( QDP: Quad Die Package )

10Bridging Between 3D and 3D TSV Stacking Technologies3/2013

2013 BiTS Workshop ~ March 3 - 6, 2013

Paper #36

And, at the Wafer Level

Session 6

New Quad Die DRAM Package 䇾QFD™䇿

Single-pass Wirebond

Four DRAM die two spacer dieNo RDL, Short bondwiresThin construction:

Two die tallNo topside wirebonds

Improved thermal properties

Quad Face Down

17 x 17 mm x 1mm tall

3/2013 Bridging Between 3D and 3D TSV Stacking Technologies 11

Form factor

Standard SO-DIMM (2,640mm2) vs. DIMM-in-a-PACKAGE (394mm2)

12Bridging Between 3D and 3D TSV Stacking Technologies3/2013

2013 BiTS Workshop ~ March 3 - 6, 2013

Paper #37

And, at the Wafer Level

Session 6

Top ICBottom IC Symmetric IC Performance

2133 MT/s (95C)

Top die 2133MT/s(15 unit sample size)

DQ

DQS/DQS#

DQ

DQS/DQS#

Bottom die 2133MT/s(15 unit sample size)

Measured at 95C on production ATE (Advantest 5501)

Faster: Monolithic Performance from All Die

3/2013 13Bridging Between 3D and 3D TSV Stacking Technologies

DDP = Dual Die Package

DDP Control Structure

Dual Face Down Structure

Speed Bin Yield1000 Unit Sample: Same Wafer Lot

DDPControl

Dual Face Down:

Bottom Die

67% Delta

Dual Face Down:

Top Die

1333

+21

33

Significant Speed Bin Yield Gain

67% gain in 2133MT/s speed bin yield vs. control DDP using same wafer lot.

3/2013 14Bridging Between 3D and 3D TSV Stacking Technologies

2013 BiTS Workshop ~ March 3 - 6, 2013

Paper #38

And, at the Wafer Level

Session 6

In-System Test SetupAgilent Infinium DSA91204A 12GHz Digital Signal Analyzer

EVGA SR-2 Classified motherboardIntel Xeon X5650 processor

For full-speed in-system probing of DQ, DQS

15Bridging Between 3D and 3D TSV Stacking Technologies3/2013

Functional At-Speed Testing DFDModule Tested Component Nominal

Speed Die density & # die/module

One DIMM/Channel(4 DQ loads/channel)

Two DIMMs/Channel(8 DQ loads/channel)

Invensas 8Gbyte Quadrank RDIMM w/DFD(1Gbit (x4)) die)

1333 MHz Components1Gbit (x4 org x 2/package)(72 memory die/module)

>1600MT/s 1600MT/s

Market 8Gbyte Quadrank RDIMM with single die packages (2Gb: single x8 die)

1333 MHz components2Gbit (x8 org x 1/package)(36 memory die/module)

~1600MT/s 800MT/s(barely operates)

Market 16GbyteQuadrank RDIMM with DDP packaging (2Gb: x4 die, DDPs)

1333 MHz components2Gbit (x4 org x 2/package)(72 memory die/module)

~1600 MT/s 800MT/s (barely operates)

3/2013 16Bridging Between 3D and 3D TSV Stacking Technologies

2013 BiTS Workshop ~ March 3 - 6, 2013

Paper #39

And, at the Wafer Level

Session 6

DFD Reads DIMM1&2, 2DPC, 1600MT/s

DQS (DIMM0)

DQ1 (DIMM0)

DQS (DIMM1)

DQ1 (DIMM1)

DIMM1 being readDIMM0 being read

3/2013 17Bridging Between 3D and 3D TSV Stacking Technologies

DFD Writes at 1600MT/s and 2DPC

DQS (DIMM0)DQ1 (DIMM0)DQS (DIMM1)

DQ1 (DIMM1)

3/2013 18Bridging Between 3D and 3D TSV Stacking Technologies

2013 BiTS Workshop ~ March 3 - 6, 2013

Paper #310

And, at the Wafer Level

Session 6

Content• Introduction• DRAM Application• Package on Package Application• Summary

3/2013 Bridging Between 3D and 3D TSV Stacking Technologies 19

Processor-Memory Architecture

The interconnect determines the computing performance and power usage

3/2013 20Bridging Between 3D and 3D TSV Stacking Technologies

2013 BiTS Workshop ~ March 3 - 6, 2013

Paper #311

And, at the Wafer Level

Session 6

PoP PiP TMV TSV

Existing Processor-Memory Stacking Solutions

• The total market size for Package-on-Package stack was about 800M in 2010

• Except for TSV, the stack packaging infrastructure is well established

3/2013 21Bridging Between 3D and 3D TSV Stacking Technologies

Wide IO Roadmap

• Wide IO is approximately an order of magnitude increase in IO compared to current memory interface

• One method of implementing wide IO is using memory with TSV, which is not expected within the next few years

2010 2011 2012 2013 2014 2015 2016?Mobile DRAM LPDDR LPDDR2 LPDDR3

Emerging Wide IOPackaging PoP PoP PoP PoP TSV

Mobile processor to memory

interconnect168 168 240 240 1250

Clock Speed (MHz) 400 533 800 200

Power 2X 1X 0.8X 0.5X

# of Channels Single Single Dual Dual Quad+Bandwidth

(GBps) 1.6 4.2 8.5 12.8 >12.8

3/2013 22Bridging Between 3D and 3D TSV Stacking Technologies

2013 BiTS Workshop ~ March 3 - 6, 2013

Paper #312

And, at the Wafer Level

Session 6

Wide IO Roadmap

• The goal of BVA PoP is to offer TSV capabilities for PoPapplications utilizing conventional PoP infrastructure and materials

2010 2011 2012 2013 2014 2015 2016?Mobile DRAM LPDDR LPDDR2 LPDDR3

EmergingWide IO Wide IO

Packaging PoP PoP PoP PoP BVA PoP TSVMobile processor

to memory interconnect

168 168 240 240 IO ranging from 200 to 1000+ 1250

Clock Speed (MHz) 400 533 800

High IO offers high bandwidth at low

speed200

Power 2X 1X 0.8X Enables intermediate power reductions 0.5X

# of Channels Single Single Dual Dual Quad+ Quad+Bandwidth

(GBps) 1.6 4.2 8.5 12.8 >12.8 >12.8

3/2013 23Bridging Between 3D and 3D TSV Stacking Technologies

BVA

3/2013 Bridging Between 3D and 3D TSV Stacking Technologies 24

• Stand-off issue eliminated: Wire-bond based memory-logic interconnect

• 1000+ wide IO: 0.2 mm pitch easily possible• High performance at low-cost: Conventional

PoP materials and processes

2013 BiTS Workshop ~ March 3 - 6, 2013

Paper #313

And, at the Wafer Level

Session 6

BVA PoP Scalability

• Assigning the same amount of area for IO as that of the current 0.5 mm pitch PoP, BVA with 0.2 mm pitch can offer up to 1440 IO

2 3 4 5 60.50 200 288 - - -0.40 248 360 - - -0.30 336 492 640 - -0.25 408 600 784 960 -0.20 512 756 992 1220 1440

Pitc

h (m

m)

No. of IO rows

3/2013 25Bridging Between 3D and 3D TSV Stacking Technologies

Overmold and Wire Exposure Process

3/2013 Bridging Between 3D and 3D TSV Stacking Technologies 26

Average wire protrusion height Top view of Overmolded bottom package

Prot

rusi

on H

eigh

t (um

)

2013 BiTS Workshop ~ March 3 - 6, 2013

Paper #314

And, at the Wafer Level

Session 6

Test Vehicle Assembly: PoP Stack

• The top surface of the of the bottom package has bond wires projectingoutwards by about 0.1 mm. The two packages were joined using conventional PoP SMT approach

Top surface of bottom package Fully Assembled BVA PoP Package

3/2013 27Bridging Between 3D and 3D TSV Stacking Technologies

Differential impedance

2 differential SIGsGNDs all around

S

S

D

Dbva(um) S (um)

DifferentialImpedance

(ohm)50 240 12550 280 13550 320 14450 360 15150 400 158

Different technology implementationfor target impedance

3/2013 28Bridging Between 3D and 3D TSV Stacking Technologies

2013 BiTS Workshop ~ March 3 - 6, 2013

Paper #315

And, at the Wafer Level

Session 6

Differential return loss and insertion loss

BVA itself is not too big an issue for RL and IL – assumed 550 um BVA height

Dbva (um) S (um)50 24050 400

3/2013 29Bridging Between 3D and 3D TSV Stacking Technologies

240 um

400 um240 um

400 um

Return loss Insertion loss

Summary• Demonstrated two technologies that can bridge

the gap before the TSV technology arrives• The two technologies offer platforms for higher

bandwidth• Platforms that uses available assembly and

available testing infrastructures

3/2013 Bridging Between 3D and 3D TSV Stacking Technologies 30