Basic Principles, Challenges and Opportunities of STT-MRAM...

Headway Technologies , Inc. A TDK Group CompanyL Thomas et al., MSST 2017 - Santa Clara, May 17th,2017

Basic Principles, Challenges and Opportunities of STT-MRAM

for Embedded Memory Applications

Luc Thomas

TDK- Headway Technologies,463 S. Milpitas Boulevard, Milpitas CA 95035, USA


Guenole Jan, Son Le, Santiago Serrano-Guisan Yuan-Jen Lee, Huanlong Liu, Jian Zhu,

Jodi Iwata-Harms, Ru-Ying Tong, Sahil Patel, Vignesh Sundar, Dongna Shen, Yi Yang, Renren He,

Jesmin Haq, Jeffrey Teng, Vinh Lam, Paul Liu, Yu-Jen Wang, Tom Zhong, and Po-Kang Wang.

MRAM Team at TDK - Headway Tech.


Magnetic Random Access Memories

More than 20 years ago: Field-MRAM

1st research program: IBM / Motorola (1995)1st product: Freescale / Everspin (2006)

From S. Parkin and K. Roche IBM


60 years ago: TDK first foray in MRAM technology

TDKs 18x24 bit Magnetic Core Memory

Source: columbia.edu/cu/computinghistory/core.html

Source: wikipedia.org/wiki/Magnetic-core_memory

MRAM was the predominant computer memory from the 50s to the 70s


Outline

Basic principles of STT-MRAM

STT-MRAM integration

STT-MRAM in emerging memory landscape


Magnetic Tunnel Junction (MTJ) device Two ferromagnetic electrodes separated by a thin MgO tunnel barrier

Tunnel Magnetoresistance (TMR): device resistance depends on the relative orientation of the magnetization of the two magnetic electrodes

Yuasa et al. (AIST) Nature Materials2004From S. Parkin and K. Roche IBM


Magnetic Tunnel Junction (MTJ) device Two ferromagnetic electrodes separated by a thin MgO tunnel barrier

Tunnel Magnetoresistance (TMR): device resistance depends on the relative orientation of the magnetization of the two magnetic electrodes

Reproduced from website of MultiDimension Technology Co.,Ltd.Yuasa et al. (AIST) Nature Materials2004


Perpendicular Magnetic Anisotropy (PMA) MTJ PMA is needed for data retention scaling and writing efficiency

PMA is based on interfacial anisotropy between MgO and CoFeBIkeda et al., Nature Mat. 2011, Worledge et al., APL 2012)

Free layer sandwiched between to MgO interfaces for the free layer for enhanced anisotropy and data retention

Dual reference layer for reducing dipolar fields and enhanced stability

Free Layer

PinnedLayer 2

PinnedLayer 1

Ikeda et al., IEDM2014


High data retention in PMA-MTJs

1ppm 10 years retention at 225C

Developed a MTJ stack of high PMA and thermal stability to satisfy solder reflow requirement of 260C for 90 seconds (2016 VLSI TSMC/TDK)

Method of projecting error rate from chip level data in ppm regime


3000

4000

5000

6000

7000

8000

9000

-8 -6 -4 -2 0 2 4 6 8

Resistance vs magnetic field hysteresis loops

H (kOe)

R (O

hms)

AP state

P state

Two well-defined resistance states depending on orientation of magnetic electrodes

Magnetic field


Low R state0

High R state1

Before endurance test

Afte

r end

uran

ce te

st

Current

Res

ista

nce

100k devices

Reading with Tunnel Magnetoresistance Read operation by probing the resistance of the device at low voltage bias

True Binary device: no resistance drift of the 2 resistance state even after repeated cycling at maximum drive current


Writing with Spin-Transfer Torque Transfer of spin-angular momentum from polarized conduction electrons to electrodes magnetization

Reproduced from Quantumwise.com

Read:Tunnel Magnetoresistance

Write:Spin Transfer Torque

VoltageR

esis

tanc

e

1

3 3

12

4

2 4

electron flow electron flow

Phenomenon discovered in 1996 by two theoreticians:

John Slonczewski (IBM)Luc Berger (Carnegie Mellon)


Write 1

Write 0

10ns 10us 10msPulse Length

0

1

-1N

orm

aliz

ed V

olta

ge (a

.u.)

Switching Current scales with area (constant current density)- smaller device -> smaller current requirement

Current inversely proportional to pulse width- faster -> higher current requirement

Trade-offs of STT writing

Chart1

7349305612300

57400.0640.232

45400.2560.928

25550.5762.088

381001.0243.712

521201.65.8

621702.3048.352

3.13611.368

4.09614.848

5.18418.792

6.423.2

7.74428.072

9.21633.408

10.81639.208

12.54445.472

14.452.2

16.38459.392

18.49667.048

20.73675.168

23.10483.752

25.692.8

28.224102.312

30.976112.288

33.856122.728

36.864133.632

40145

43.264156.832

46.656169.128

50.176181.888

53.824195.112

57.6208.8

61.504222.952

65.536237.568

69.696252.648

73.984268.192

78.4284.2

82.944300.672

87.616317.608

92.416335.008

TDK (2012)

TOSHIBA (2008)

IBM (2012)

LEAP(2012)

Tohuku U.(2012)

Device Diameter (nm)

Switching Current (uA)

Sheet1

diameterEbIc0efficiencyRef

69907376.1761.2328767123APEX 2012

59865755.6961.5087719298APEX 2012

51844541.6161.8666666667APEX 2012

37742521.9042.96APEX 2012

45893832.42.3421052632APEX 2012

54905246.6561.7307692308APEX 2012

63916263.5041.4677419355APEX 2012

5056491.1428571429Toshiba IEDM 2008

0.5Samsung VLSI 2012

2029.4300.98IBM 2012

2330400.75IBM 2012

2727400.675IBM 2012

3232550.5818181818IBM 2012

40481000.48IBM 2012

44601200.5IBM 2012

54671700.3941176471IBM 2012

60441.3636363636

4570451.5555555556

75481.5625

5351560.9107142857LEAP(2012)

52600.8666666667

54650.8307692308

70951230.7723577236Tohuku U.(2012)

000

20.0640.232

40.2560.928

60.5762.088

81.0243.712

101.65.8

122.3048.352

143.13611.368

164.09614.848

185.18418.792

206.423.2

227.74428.072

249.21633.408

2610.81639.208

2812.54445.472

3014.452.2

3216.38459.392

3418.49667.048

3620.73675.168

3823.10483.752

4025.692.8

4228.224102.312

4430.976112.288

4633.856122.728

4836.864133.632

5040145

5243.264156.832

5446.656169.128

5650.176181.888

5853.824195.112

6057.6208.8

6261.504222.952

6465.536237.568

6669.696252.648

6873.984268.192

7078.4284.2

7282.944300.672

7487.616317.608

7692.416335.008

Sheet1

TDK (2012)

TOSHIBA (2008)

IBM (2012)

LEAP(2012)

Tohuku U.(2012)

Junction Diameter (nm)

Efficiency (kBT/uA)

Sheet2

TDK (2012)

TOSHIBA (2008)

IBM (2012)

LEAP(2012)

Tohuku U.(2012)


Energy barrier (uA/KbT)

TDK (2012)

TOSHIBA (2008)

IBM (2012)

LEAP(2012)

Tohuku U.(2012)


switching current (uA)

Sheet3


Trade-offs of STT writing (contd)

Write current scales with energy barrier for data retention

Energy barrier: EB~ KuV

Write current: Ic0 = (4e/) (/P) EB

STT efficiency: EB/Ic0 ~ 1-2 in kBT/A

Writing is probabilistic

-1

-0.5

0

0.5

1

0 1000 2000 3000 4000 5000

PMA_Ms1200_K=1e7_60x60x2_c2_a=0v01_Pz=pos10d_I=500uA

Mx(ave)My(ave)Mz(ave)

Mx(

ave)

Time(ps)

STT vanishes for parallel alignment of PL and FL

Switching time inversely proportional to angle between PL and FL

Thermal fluctuations provide initial kick


Outline





Integration of 8 Mb test chips at TDK - Headway

8Mbits (16x512k) 1T-1MTJ IBMs 90nm CMOS technology 50F2 cell size Sense Amplifiers for reading Redundancy and 2bit ECC FEOL in IBM foundry BEOL in TDK-Headways fab

AccessTransistor

WL

BLT

BLC


STT MRAM process integration MRAM only add three additional layers (MTJ and electrodes) to standard

CMOS BEOL: 3 to 4 mask adder

MTJ stack is about 20 nm thick, can be easily integrated into CMOS backend process


Defect rate of 8 Mb chip

Distribution of device current in the P state Quantile plot Log scale

less than 0.4 ppm defect rate

1 ppm

read current (a.u.) read current (a.u.)


400C annealing after MTJ patterning

400C BEOL process can add up to several hours, depending on how many metal layers on top of MTJ

Elemental movements and morphology changes can degrade anisotropy, exchange coupling, and defect level

- selection of materials, diffusion barrier and interface/growth quality

- Thorough engineering needed for electrodes, film stack, process, encapsulation

2.5 hours @400C after MTJ etching

Diameter ~ 30 nm (electrical) DRR = 175% RA of 8.5 -m2 HC = 3300 Oe with no offset


Error free writing on 8 Mb chips without ECC Down to 6 ns write pulse While keep data retention to 142C for 10 years

Temperature (C)

ef

f

1ppm @ 142C for 10 years

Error free writing in chip level (TDK VLSI2014 & 2016)


Temperature dependence (TDK VLSI2014)Fast operation down to 4.5 ns demonstrated over wide temperature range

-25C 0C 25C 55C 85C 125C

No

ECC

2 bi

t EC

C

No Error

104.5 104.5 104.5 104.5 104.5 104.5

104.5 104.5 104.5 104.5 104.5 104.5


Outline





STT-MRAM vs other memory technologies


STT-MRAM requirements

Critical requirements depend on application

from S.H Kang, Qualcomm (Proc. VLSI 2014)


Cost is directly related to density & cell/chip sizeCurrent available scales with transistor size

- Standalone DRAM : GB chips, cell size ~4F2F smallest feature at technology node (28,20,14/16nm,)

MTJ < 20 nmWrite current < 20 ATMR ~ 300%

- Embedded Flash / DRAM : cell size ~40-50F2MTJ ~ 40-100 nmWrite current > 100 ATMR > 100%

STT-MRAM Challenge

Kent & Worledge, Nature Nano (2015)


Lower cost Similar or Smaller bit cell sizeVery few added mask layersDoes not interfere with CMOS transistor performances (as a add-on in the backend metal layers)

Almost universal memoryCombines non-volatility, high speed, and infinite enduranceCan replace eFlash, eDRAM, and last-level cache (LLC) SRAMEfficient system architectures, without moving data between code storage, and working memory, and data storage

Higher energy efficiency (longer battery life) mobile and IoT applications have low duty cycles and need fast wake-up and

low standby power

Embedded STT-MRAM is cheaper and better!


6-Transistor SRAM scaling challenge

Samsung VLSI 2016

22nm to 10 nm node:

- Expected area scaling: 4.8X- Actual scaling: ~ 2X

400F2 at 10nm vs 52F2 at 40nm

Complex design limits scaling

Dramatic increase of the area occupied by memory vs logic in performance SoC and CPUs


Opportunity for eMRAM as Last Level Cache

1/ Pulse width1.5ns1.8ns2.3ns

Volta

ge (a

.u)

NO ECC

Compact design 1T-1MTJ 8 Mb written without error with 1.5 ns write pulse

TDKVLSI 2016


Summary

STT-MRAM combine low write current, data retention and write speed, and is compatible with BEOL processes.

Working chips have been demonstrated

MTJ device can be tailored to specific applications that require data retention or speed,

Great opportunity for embedded applications from eFlash to SRAM replacement (both Samsung and TSMC have announced production)

Many challenges remain: writing efficiency, read margin (TMR), process control (tight pitch, uniformity),


Circa 1970 Intel corporation - Computer history museum

1970: Magnetic memories lose the war to Silicon

2017: year of the comeback

for MRAM?

Slide Number 1Slide Number 2Slide Number 3Slide Number 4Slide Number 5Slide Number 6Slide Number 7Slide Number 8Slide Number 9Slide Number 10Slide Number 11Slide Number 12Slide Number 13Slide Number 14Slide Number 15Slide Number 16STT MRAM process integrationSlide Number 18Slide Number 19Slide Number 20Slide Number 21Slide Number 22Slide Number 23Slide Number 24Slide Number 25Embedded STT-MRAM is cheaper and better!Slide Number 27Slide Number 28Slide Number 29Slide Number 30

Basic Principles, Challenges and Opportunities of STT-MRAM...

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