Axel Jantsch1

Networks on ChipA Paradigm Change ?

Axel Jantsch

Laboratory of Electronics and Computer Systems, Royal Institute of Technology, Stockholm

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Challange:

How do we organize a chip with one or several billion of transistors?

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Why can’t we just continue?Trends and Challenges

Deep submicron effects Communication versus Computation Global synchrony Design productivity gap Heterogeneity of functions

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Arbitrary Composability Given: Set of components C and combinators OA1, A2: assamblages of componentsB is a component (C,O) is arbitrarily compasable if

A1 + B => A2can be done with effort independent of size (A1)

A1 + => A2B

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Network on Chip

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What is a NoC based Platform?

A Platform is defined by(A) the communication infra-structure from the

physical level to the application level; (B) the provided services (e.g. load balancing, power

management, fault-tolerance, resource allocation, task scheduling, external I/O, etc.);

(C) the design methodology mapping and implementing applications to the platform.

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How does a NoC Platform help?

ReusePredictability

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Reuse Components and resources Communication infra-structure

Reuse of the physical designLower level communication servicesHigher level communication servicesNetwork services (operating system and middleware)

Application parts and features Design, simulation and prototype environment Verification effort

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Predictability Communication performance Electrical properties Design and verification time

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The price we pay

Less optimal products

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Development of NOC based systems

BACKBONE

PLATFORMS

SYSTEMS

Baseband platform

Database platform

Multimedia platform

High-perforrmance communication systems

High-capacity communication systems

Virtual reality games

Entertainment devices

Personal assistant

Data collectionsystems

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A NoC Platform Based Design Process

Configuring the platform Selecting resources Reuse of features Evaluation and integration

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Conclusion

Arbitrary composability at physical, architectural, and application level is necessary

If NoC can deliver that it will significantly change design and architecture of SoCs

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Status of Research at KTH Definition of the protocol stack up to the transport

layer Design of a buffer-less switch and a hot-potato

routing technique NoC simulator Fault model and error handling scheme Development of a quasy-sycnhronous clocking

scheme Development of a NoC Assamble Language