Athens 2004 Symposium on Innovation of Computer Science Curriculum in Higher Education Athens 2004...

Symposium on Innovation of Computer Science Curriculum in Higher Education Athens 2004Athens 2004

Decision Diagrams:Decision Diagrams:Principles of Programming Principles of Programming

Dragan Janković[email protected]

Faculty of electronic engineeringUniversity of Niš


OUTLINES

- Introduction- Binary decision diagrams- Multiple-valued decision diagrams- Applications in Logic design

- Implementation principles- Shared DDs- Unique table- Strong canonicity- Attributed edges- Computed table- Memory management and dynamic reordering

- Universal DD package - Conclusion

“Give me enough strong support,I will move the Earth up “


Verification of synthesized netlist vs. final netlistFinal

– 2843 inputs, 4178 outputs, 150215 states– 2.634 million gates– 3861939 loc (parsed in 1:41 min)

Synthesis– 2843 inputs, 4178 outputs, 150218 states– 2.635 million gates– 222610 loc (parsed in 15 sec)

Equivalence Check: 18:10 CPU min, 0.373 GByte

Circuit complexity


Logic design problemsand the others


“ Decision diagrams arethe state-of-the-art

data structure in VLSI CAD for representation and manipulation

of Discrete functions “

W H Y ?


Binary Decision Trees.• A BDT is a rooted, directed tree that

consists of two types of nodes, terminal nodes and nonterminal nodes.– Each nonterminal node v

• is labeled by a variable var(v) • and has two successors :

– low(v) corresponding to the case where the variable v is assigned 0

– and high(v) corresponding to the case where v is assigned 1.

– Each terminal node v • is labeled by value(v) which is either 0 or 1.


Graphical representation

1

32

0 1

01

1

0

10

index(v) = 2

vnon-terminal

terminalvalue(u)

u

high(v)

low(v)


Truth Table Decision Tree

– Node represents decision

– Follow blue line for value 0

– Follow red line for value 1

– Function value determined by terminal value.

00001111

00110011

01010101

00010101

x1 x2 x3 f x1

x3

x2

x3x3x3

10

x2

110 0 0 0

0 1

1010

0 1 0 1 0 1 0 1


1) Merge equivalent terminals

a a

0 0

x3

0 1

x3

x2

0 1

x3

0 1

x3

x2

x1

x3 x3

x2

x3

0 1

x3

x2

x1

a

Reduction rulesSymposium on Innovation of Computer Science Curriculum in Higher Education Athens 2004Athens 2004

y

x

z

x

2) Merge isomorphic nodes

x3 x3

x2

x3

0 1

x3

x2

x1

x3

x2

0 1

x3

x2

x1

y

x

z

x

y

x

z

x


x3

x2

0 1

x3

x2

x1

3) Eliminate Redundant Tests

y

x

y

x2

0 1

x3

x1


ROBDD or BDD

Binary Decision Diagram

• A BDD is a rooted, directed acyclic graph with two types of vertices, terminal vertices and nonterminal vertices.– Each nonterminal vertex

• is labeled by a variable var(v)• and two successors, low(v) and high(v)

– Each terminal vertex • is labeled by a either 0 or 1.


STATE – OF – THE – ARTDATA STRUCTURE

????


b3 b3

a3

Cout

b3

b2 b2

a2

b2 b2

a2

b3

a3

S3

b2

b1 b1

a1

b1 b1

a1

b2

a2

S2

b1

a0 a0

b1

a1

S1

b0

10

b0

a0

S0

• Functions– All outputs of 4-bit adder– Functions of data inputs

A

B

Cout

SADD

• Shared Representation– Graph with multiple roots– 31 nodes for 4-bit adder– 571 nodes for 64-bit adder Linear growth

Representing Circuit Functions

GByte28104Truth-vector


• Logic Circuit Comparison

– Do circuits realize identical function?• Basic task of formal hardware verification• Compare new design to “known good” design

A

C

B

O1

T1

T2

ABC

O2

T3


• Generate Complete Representation of Circuit Function– Compact, canonical form

– Functions equal if and only if representations identical– Never enumerate explicit function values– Exploit structure & regularity of circuit functions

A

C

B

O1

T1

T2

ABC

O2

T3

b

0 1

c

a

b

0 1

c

a


Network Evaluation

Task: Represent output functions of gate network as OBDDs.

A

B

C

T1

T2

Out

Resulting Graphs

A B CT1 T2

Out

0 1

a

0 1

c

0 1

b

0 1

b

a

0 1

c

b

c

b

0 1

b

a

•A new_var ("a");•B new_var ("b");•C new_var ("c");•T1 And (A, 0, B);•T2 And (B, C);•Out Or (T1, T2);

Generating OBDD from Network


• Verification– Combinational equivalence (UCB, Fujitsu, Synopsys,

…)– FSM equivalence (Bull, UCB, MCC, Siemens,

Colorado, Torino, …)– Symbolic Simulation (CMU, Utah)– Symbolic Model Checking (CMU, Bull, Motorola, … )

• Synthesis– Don’t care set representation (UCB, Fujitsu, …)– State minimization (UCB)– Sum-of-Products minimization (UCB, Synopsys, NTT)

• Test– False path identification (TI)


• Systems Represented as Finite State Machines– Sequential circuits

– Communication protocols

– Synchronization programs

• Analysis Tasks– State reachability

– State machine comparison

– Temporal logic model checking

• Traditional Methods Impractical for Large Machines– Polynomial in number of states

– Number of states exponential in number of state variables.

– Example: single 32-bit register has 4,294,967,296 states!

Finite State System Analysis


Pentium bug 475 million $ loss

Verification (equivalence check)

RTL compiler

net compiler

gate

gate

synthesis cons.

compare


How to implement Decision Diagrams ?


• Min

imal

mem

ory •Efficient m

anipulation


The basic tasks in DD programming

• Determine the data structure to represent a node• Provide efficient construction of DDs from a specification

• Provide efficient manipulation

“Optimal” DD does not exist –

Dependent on the underlying application one should be favored

There are a different types of DDs


DDs based packages

- standard part of many VLSI CAD systems - efficient implementation of one or a few strongly related DD types for some particular class of discrete functions (BDD, KDD, …)

Existing packages:• Rudell’s package (Synopsys)• David Long’s package (Carnegie Mellon University) in SMV, VIS, SIS.• CUDD (University of Colorado)• PUMA (University of Freiburg)• BEMIITA, etc.


Basic principles in DD programming

Shared DDs

Unique table

Strong canonicity

Attributed edges

Computed table

Memory management and dynamic reordering


Node representationNode representationstruct DdNode{

DdHalfWord index; - index of variable assigned to the node

DdHalfWord ref; - counter of references DdNode *next; - pointer to the following node in the

Unique table

union { CUDD_VALUE_TYPE value; - for terminal nodes

DdChildren kids; - for non-terminal nodes

} type}

struct DdChildren { struct DdNode *T; - pointer to the THEN successor

struct DdNode *E; - pointer to the ELSE successor}


vector:: mapping : variables to levels and vice-versa

Shared DDs

-representation of multioutput functions

-system of functions

-functions shared the same nodes

-reduction in space

b3 b3

a3

Cout

b3

b2 b2

a2

b2 b2

a2

b3

a3

S3

b2

b1 b1

a1

b1 b1

a1

b2

a2

S2

b1

a0 a0

b1

a1

S1

b0

10

b0

a0

S0


Strong canonicity

-DDs are a canonical representation-One DD corresponds to the only one function and -One function can be represented by only one DD-Conditions:

- DD is ordered and reduced - There is no isomorphic nodes


Unique table

-all nodes are stored in table called “Unique table”-Unique table is “hash” based table-Two approaches:

- unique table- each variable separate subtable

To do:-Choose the good “key” and hash function-Choose the right size of hash table -Influence to the number of “hits”-Depends on the application-Fine tuning of the package performance


Decision: store the KEY into the node structure or not?

-reduce storage memory

-avoid repeated calculation of the node KEY

Before the generation of the new node we should try

to find the same node in the Unique table.-return existing node

-generate a new node and insert it into Unique table

Key = v + _HASH_KEY(G) + _HASH_KEY(H) + _HASH_KEY(I) + _HASH_KEY(J) + _HASH_KEY(K)

PUMA


Compute table

-Avoid repeated calculation

-All results are stored in table called “Compute table”

-Compute table is “hash” based table

-Two approaches:- compute subtables for each operation separately- unique compute table- generic approach (only one operation)

-Arguments: - operation

- arguments of operation- result


Before calculation try to find the same operation with the same arguments:

- return the existing result- perform the operation and store result into compute table


Attributed edges

-complemented edge-EVBDD (efficient representation of multipliers)

Complemented edges

- denotes complemented functions- complexity for the operation negation is O(1)- dot at the edge in graph representation- the last bit in pointer to the node:

- 0 – denotes noncomplemented function- 1 – denotes complemented function

- Reduction in memory up to 20%


Equivalent Pairs

x

xx

x

xx

xx

Limitation: Position of dots is not arbitrary


Memory management

- limited memory- garbage collection

- performed:- automatically (free space less than 20%)- manually

- Reference counter used in garbage collection-There are: living nodes (ref. Count >0 ) and dead nodes (ref count. = 0 )- Garbage collection operation removes the dead nodes out of the unique table


Good Ordering Bad Ordering

Linear Growth

0

b3

a3

b2

a2

1

b1

a1

Exponential Growth

a3 a3

a2

b1 b1

a3

b2

b1

0

b3

b2

1

b1

a3

a2

a1

)()()( 332211 bababa

Dynamic reordering- DDs are very sensitive to the variable ordering


Finding the good variable ordering

- very hard problem

-A lot of different methods:-exact methods (exponential complexity)-heuristic methods-statistical methods-evolution algorithm based methods-dynamic variable ordering method-Sifting method-Lower-bound sifting method-Etc.- Choose one of the above methods depends on the functions, application, computer resources, etc…- apply automatically or manually


Dynamic Variable ReorderingDynamic Variable Reordering

– Richard Rudell, Synopsys

• Periodically Attempt to Improve Ordering for All BDDs– Part of garbage collection– Move each variable through ordering to find its best location

• Has Proved Very Successful– Time consuming but effective– Especially for sequential circuit analysis


a3

b2 b2

a3

a2

a3

b1

b2

0

b3

b1

1

b2

a3

a2

a1

a3

b2

b3

b2

a3

a2

a3

b2

0

b1

b3

1

b2

a3

a2

a1

a2

a3

b1

b2

0

b3

b2

a3

1

b1

a2

a1

a3

b2

0

b3

b2

a3

a2

1

b1

a1

a3 a3

a2

b1 b1

a3

b2

b1

0

b3

b2

1

b1

a3

a2

a1

• • •a3

b2

0

b3

b2

a3

a2

1

a1

b1

BestChoices

Dynamic Reordering By SiftingDynamic Reordering By Sifting

– Choose candidate variable– Try all positions in variable ordering

• Repeatedly swap with adjacent variable

– Move to best position found


b1 b1

b2b2 b2b2

e f g h

i jb1 b1

b2

b1

b2

b1

e f

g h i j

Swapping Adjacent VariablesSwapping Adjacent Variables

• Localized Effect– Add / delete / alter only nodes labeled by

swapping variables– Do not change any incoming pointers


DDs manipulations

• Building of DDs

• Performing binary operation over two DDs

• Performing transform over DDs


Boolean Operations on BDDs

u v

f g<op>

Case 1: u and v are terminals. Then resulting graph is a single terminal w:

value(w) = value(u) <op> value(v)


0

f1

<op>

Case 2: u and v are non-terminals and index(u) = index(v) = i

i

f2 g1

i

g2

01 1

0

f1 <op> g1

i 1

f2 <op> g2

Get theserecursively


0

f1

<op>

Case 3: u is a non-terminal, index(u) = i v is either a terminal or index(v) = j > i

i

f2 g1

j

g2

01 1

0

f1 <op> g

i 1

f2 <op> g

j > i

or x

x = 0 or 1

APPLY( )


Pseudocode for Apply Operation

function Apply( F, G )

if ( AlreadyComputed( F, G ) ) return result;

else if ( F=={0,1} && G=={0,1} ) return oper( F, G );

else if ( Var( F ) == Var( G ) )

u = CreateNode( Var(F), Apply(Fx’,Gx’), Apply(Fx,Gx));

else if ( Var( F ) < Var( G ) )

u = CreateNode( Var(F) , Apply(Fx’,G ), Apply(Fx,G ));

else /* if ( Var( F ) > Var( G ) ) */

u = CreateNode( Var(G) , Apply(F,Gx’ ), Apply(F,Gx ));

InsertComputed( F,G,u );

return u;


Example: F=ac+bc+d G=ac’+d F+G = ?

a

d

c

b

10

a

c

d

10

+

A1

A2

A6

A3

B1

B5

B2

A4 A5 B3 B4

A1,B1

A2,B2

A6,B2

A3,B2

A4,B3 A5,B4

A6,B5

A5,B2 A3,B4


A1,B1

A2,B2

A6,B2

A3,B2

A4,B3 A5,B4

A6,B5

A5,B2 A3,B4

a

d

c

b

10

c

1 1

a

d

c

b

10reduction


Improvement:

APPLY procedure if-then-else operator ITE

Definition: ITE is a binary operator defined by

where F,G,H are arbitrary switching functions

HFGFHGFite ,,


I T E r e a l i z a t i o n

)H,G,F(iteZ ,

v - t h e t o p v a r i a b l e o f F , G , H .

vv ZvZvZ

vv HFGFvHFGFv

vvvvvvvv HFGFvHFGFv

vvvvvv H,G,Fite,H,G,Fite,vite

vvvvvv HGFiteHGFitev ,,,,,,

T e r m i n a l c a s e s :

FFiteFGiteGFite 0,1,,,0,,1 .


Realization of arbitrary binary operations over BDDs by ITE operator

T a b l e N a m e E x p r e s s i o n E q u i v a l e n t f o r m0 0 0 0 0 0 00 0 0 1 A N D ( F , G ) GF ),G,F(ite 00 0 1 0 F > G GF ),G,F(ite 00 0 1 1 F F F0 1 0 0 F < G GF )G,,F(ite 0

0 1 0 1 G G G0 1 1 0 X O R ( F , G ) GF )G,G,F(ite0 1 1 1 O R ( F , G ) GF )G,,F(ite 11 0 0 0 N O R ( F , G ) GF )G,,F(ite 01 0 0 1 X N O R ( F , G ) GF )G,G,F(ite1 0 1 0 N O T ( G ) G ),,G(ite 10

1 0 1 1 F G GF )G,,F(ite 11 1 0 0 N O T ( F ) F ),,F(ite 101 1 0 1 F G GF ),G,F(ite 11 1 1 0 N A N D ( F , G ) GF ),G,F(ite 11 1 1 1 1 1 1


Generation of MDDs

Similar as generation of BDDs.

CASE operator instead ITE operator

Definition: CASE for q-valued functions is as an operator of q+1 argument as

or in form:

where

iFGG,,G,G,FCASE iq for 110 ,

1

0

110 ,,,,q

i

ii

q GFJGGGFCASE

iF

iFFJ i 0

1


C A S E r e a l i z a t i o n

110 qG,,G,G,FCASEZ

110110

110

11111111

0000

,,,,,,,,,,

,,,,,,

q

vvvvq

vvvv

qvvvv

qqqqGGGFCASEGGGFCASE

GGGFCASEvCASEZ

w h e r e

jvFFjv a n d jvGG ii

v j .

T e r m i n a l c a s e s :

FqFCASE

FGGqCASE

GFGCASEGGFCASE qq

1,,1,0,

,,,,1

,,,,1,,,,010

1011


A n e w i n t e r p r e t a t i o n o f I T E a n d C A S E

C o n n e c t i o n b e t w e e n r o w s o f t h e o p e r a t i o n t a b l e a n da r g u m e n t s i n I T E a n d C A S E

R e a l i s a t i o n o f a r b i t r a r y b i n a r y o p e r a t i o n so v e r B D D s b y I T E

O P 0 10 v 0 , 0 v 0 , 1

1 v 1 , 0 v 1 , 1

0,01,00,11,1 ,,,,,,, vvbitevvbiteaitebaOP .


E x a m p l e : I T E

A N D o p e r a t i o n O R o p e r a t i o n

A N D 0 1 O R 0 10 0 0 0 0 11 0 1 1 1 1

0,,0,0,1,,0,0,,0,1,,, baitebiteaitebitebiteaitebaAND

baitebiteaitebitebiteaitebaOR ,1,0,1,,1,0,1,,1,1,,, .


R e a l i s a t i o n o f a r b i t r a r y b i n a r y o p e r a t i o n so v e r M D D s b y C A S E

T a b l e : D e f i n i t i o n o f o p e r a t i o n q O P .

q O P 0 1 q - 10 v 0 , 0 v 0 , 1

v 0 , q - 1

1 v 1 , 0 v 1 , 1 v 1 , q - 1

q - 1 v q - 1 , 0 v q - 1 , 1 v q - 1 , q - 1

1,11,10,1

1,11,10,1

1,01,00,0

,,,,

,,,,,,

,,,,,,(,

qqqq

q

q

vvvbCASE

vvvbCASE

vvvbCASEaCASEbaqOP


E x a m p l e : C A S E

L e t 3q

3 - A N D 0 1 2 3 - O R 0 1 20 0 0 0 0 0 1 21 0 1 1 1 1 1 22 0 1 2 2 2 2 2

3 - A N D a n d 3 - O R b y C A S E

3 - A N D ( a , b ) = ))2,1,0,(),1,1,0,(,0,( bCAS EbCAS EaCAS E

3 - O R ( a , b ) = ))2,2,2,(),2,1,1,(),2,1,0,(,( bCA S EbCA S EbCA S EaCA S E


Direct DDs generation

• Function represented by cubes or analytical

• Generate DD for each cube

• Add contribution of each cube


F=[0000222200001000] (1X 2) , (30 1)


Transform over DDs

Calculation of T over BDDs is done by performingoperations defined by rows of the basic operatormatrices Ti(1).

BDD for f BDD for g=T(f)

ITE operators in each node

and cross-point

-Reed-Muller, Walsh, …


Symbolic Manipulation with OBDDsSymbolic Manipulation with OBDDs

• Strategy– Represent data as set of OBDDs

• Identical variable orderings

– Express solution method as sequence of symbolic operations

– Implement each operation by OBDD manipulation

• Algorithmic Properties– Arguments are OBDDs with identical variable

orderings.– Result is OBDD with same ordering.


Sample Function ClassesSample Function ClassesFunction Class Best Worst Ordering Sensitivity

ALU (Add/Sub) linear exponential High

Symmetric linear quadratic None

Multiplication exponential exponential Low

• General Experience– Many tasks have reasonable OBDD (or other DDs)

representations– Algorithms remain practical for up to 500,000

nodes– Heuristic ordering methods generally satisfactory


•••

•••

Lower Bound for MultiplicationLower Bound for Multiplication

– Bryant, 1991• Integer Multiplier Circuit

– n-bit input words A and B

– 2n-bit output word P

• Boolean function

– Middle bit (n-1) of product

• Complexity

– Exponential OBDD for all possible variable orderings

Multn

•••

•••

a0

an-1

b0

bn-1

p0

pn-1

pn

p2n-1

Actual NumbersActual Numbers 40,563,945 BDD nodes to

represent all outputs of 16-bit multiplier

Grows 2.86x per bit of word size

IntractableFunction


Universal DD package

At Faculty of electronic engineering Nis (version 1.0)

Features:

• MDD generation for function represented by truth vector or cubes:• Generation of the truth-vector of MV function from its DD.• Spectrum generation from STDD.• Symbolic showing of DD.• Arbitrary operation over two MDDs• Arbitrary transform over MDD.• Some operation over STDD.


Conclusions

“What do you think about DDs ?”


DDs

Logic design problemsand the others


Athens 2004 Symposium on Innovation of Computer Science Curriculum in Higher Education Athens 2004...

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