634 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. SC-18, NO. 6, DECEMBER 1983

A Precision Curvature-CompensatedCMOS Bandgap Reference

BANG-SUP SONG, STUDENTMEMBER,IEEE,ANDPAUL R. GRAY, FELLOW,IEEE

Ab.~tract—A precision curvature-compensated switched-capacitor band-

gap reference is described which employs a standard digital CMOS processand achieves temperature stability significantly lower than has previouslybeen reported for CMOS circuits. The theoretically achievable tempera-ture coefficient approaches 10 ppm/ 0 C over the commercial temperaturerange utilizing a straightforward room temperature trim procedure. Experi-mental data from monolithic prototype samples are presented which are

consistent with theoretical predictions. The experimental prototype circuit

occupies 3500 milsz and dissipates 12 mWwith+ 5 Vpowersupplies,Theproposedreferenceis helieved to be suited for use in monolithic data

acquisition systems with resolutions of 10 to 12 bits.

I. INTRODUCTION

A N essential element of the analog and digital inter-face function is a voltage reference to control the

scale factor of conversion. The temperature stability of areference source is a key factor in the accuracy of theoverall data acquisition function. Therefore, the ability tointegrate an entire data acquisition system within a singleCMOS VLSI chip is contingent upon the ability to realize aCMOS compatible voltage reference with a very low tem-perature drift. Since its introduction by Widlar [1], thebandgap referencing (BGR) technique has been widelyemployed for implementing a voltage reference source inbipolar integrated circuits. The temperature stability of thebandgap reference has been continuously improved vianew circuit and technology innovations such as curvaturecompensation and laser trim [2]–[5]. In CMOS technology,the BGR technique has been directly applied [6]–[8]. How-ever, the development of a high-performance CMOS band-gap reference has been hindered by several limiting factorsattributable to the peculiarities of the bipolar devices avail-able in a standard CMOS process, the high offset and driftof CMOS op amps that make up the circuit and theinherent curvature problem in the bandgap reference.

This paper will describe one circuit implementation of aprecision CMOS bandgap reference which overcomes someof the drawbacks of a standard CMOS process, and em-bodies curvature compensation and differential offset

Manuscript received April 6, 1983; revised August 3, 1983. This workwas supported by the National Science Foundation under Grants ECS-8023872 and ECS-8120012, IBM Corporation, and the MICRO Project.

B.-S. Song is with Bell Laboratories, Murray Hill, NJ 07974,P. R. Gray is with the Department of Electrical Engineering and

Computer Science, Electronics Research Laboratory, University of Cali-fornia, Berkeley, CA 94720.

cancellation to achieve experimental typical temperaturedrifts of 13.1 and 25.6 ppm/ 0C over the commercial andmilitary temperature ranges, respectively. In the proposedreference, a temperature-stable voltage is developed byadding linear and quadratic temperature correction volt-ages to the forward-biased diode voltage which is obtainedfrom the substrate p-n-p transistor available in CMOSprocesses. The linear temperature correction voltage isproportional to the absolute temperature (commonly calledPTAT) while the quadratic temperature correction voltageis proportional to the absolute temperature squared(PTAT2). They are independently adjustable to set thereference output voltage for a minimum temperature drift.

The offset voltage of the CMOS op amp is eliminatedusing the correlated-double sampling (CDS) technique [9].The base current and base spreading resistance of thenative substrate p-n-p transistor are cancelled to the firstorder and the amplification ratio is set by a capacitor ratiorather than a resistor ratio. Due to the cyclic behavior ofthe offset cancellation in this technique, the output refer-ence voltage is not available at all times. However, thereference can be operated synchronously with other ele-ments of the systems. Since the periodic offset sample andsubtraction cycle effectively removes the low-frequency l/~noise component of a CMOS op amp along with its offset,the dominant noise source is the thermal noise of a CMOSop amp which is designed to be on the order of 100 pV(rms) at the output in 500 kHz bandwidth.

In Sections II and III, the primary limitations in aconventional CMOS BGR implementation and the temper-ature curvature in bandgap references are discussed. InSection IV, a curvature-compensated switched-capacitorCMOS bandgap reference is introduced. In Section V,experimental results measured from monolithic prototypesamples are presented and the problems related to thedesign of p-n-p transistors are discussed. The theoreticalanalysis of BGR temperature compensation techniques isincluded in the Appendix.

II. CONVENTIONALCMOS BGR IMPLEMENTATION

One example of a conventional CMOS BGR implemen-tation in an n ‘-well CMOS process is shown in Fig. 1.Transistors QI and Qz are substrate p-n-p transistors whosecollectors are always tied to the most negative power

0018-9200/83/1200-0634$01 .00 01983 IEEE

SONGANDGRAY:PRECISIONCURVATURE-COMPENSATEDCMOSBANDGAPREFERENCE 635

1R2 R3

v0s

Vref0

I 1, +12

V,ef=VBE+(I+% )(AVBE+Vo~)I

[ ~ Q, Qz

L Lv Ss

Fig. 1 Exampleof a conventionalCMOSbandgap reference.

supply because, in an n ‘-well CMOS process, the p+diffusion in the n--well, the n--well itself and the p-substrate form a vertical p-n-p structure as shown in Fig.2(a). Therefore, it is not possible to sense the collectorcurrent directly as in the bipolar bandgap reference so asto reduce the error due to the finite current gain [3], [4]. Ina p ‘-well process, a dual circuit incorporating n-p-n tran-sistors would be used. While many other circuit implemen-tations are possible, this circuit appears to be as good asany. Therefore, individual error sources will be describedone by one for this circuit in the rest of this section. Allresistors are the p ‘-diffusion resistor in the n ‘-well and theCMOS op amp is assumed to have an infinite gain with theoffset voltage of VO,.This assumption is justified becauseCMOS op amps usually have enough gains such that theerror due to finite-gain effects is negligible for this applica-tion.

Assuming that transistor Q1 in Fig. 1 has an area that islarger by a factor A than transistor Qz, and both are in theforward active region, the output voltage of the reference isgiven by

(1~ef=vBE+ 1+: (AVBE+V&)1

(1)

where VBE is the emitter-base voltage of transistor Q1,AVBEis the difference between the emitter-base voltages oftransistors Q1 and Q2, and VO,is the input offset voltage ofthe operational amplifier. The value of this expression isinfluenced by the nonidealities of the bipolar transistors asillustrated in Fig. 2(b). If these are taken into account, thetransistor emitter–base voltage is given by

1 rb11VBE= F’Jn # + F’~ln~ + —

A&(2)

S1

l+Fl

where VT is the thermal voltage kT/q, 11 is the emittercurrent of transistor Q1, Isl is the saturation current oftransistor Ql, & is the current gain of transistor Q1 and rbis the effective series base resistance of Qz. The secondterm in this expression results from the fact that whilethe collector current is a well-defined function of theemitter-base voltage, the current sensed and controlled by

Base Emitter

t P+ h+

%

(a)

y- AV,E +?

-1

rb/A

I&

I I(b)

Fig. 2, (a) Substrate p-n-p transistor profile. (b) Nonideal parameters inthe PTAT correctionvoltagegenerationcircuit.

this circuit is the emitter current. The third term resultsfrom the voltage drop in the finite series base resistance.The difference between the two emitter-base voltages isgiven by

1

l+FlAVBE = V~ln A + V~ln $ + V~ln ~

1 ‘rlbid

1+T2

(3)

where 12is the emitter current of transistor Qz and B2is thecurrent gain of transistor Qz. If the bipolar transistors usedto implement the reference are ideal in the sense that theyhave infinite current gain and zero base resistance, and ifthe emitter currents of the transistors are in fact equal,then only the first terms in (2) and (3) are nonzero.However, because of the relatively poor performance ofCMOS-compatible devices, these terms can strongly in-fluence the performance of the reference. The presence ofthe operational amplifier offset voltage in the output, mul-tiplied by the gain factor (1+ R ~/R1), which is typicallyon the order of 10, is also an important degradation.Finally, the variation of the bias currents 11 and Iz withtemperature must be carefully considered. In the followingsubsections, the effects of these nonidealities are examinedin more detail.

A. Operational Amplifier Offset

The operational amplifier offset is the biggest errorsource that causes the nonreproducibility in the outputvoltage temperature coefficient. Normally, a bandgap ref-erence is trimmed to an output voltage which is prede-termined to give a near-zero temperature coefficient of theoutput. Large, non-PTAT components in the output due to

636 IEEEJOURNALOFSOLID-STATECIRCUITS,VOL.SC-18,NO.6, DECEMRER1983

the op amp offset cause the trimming operation to give anerroneous result. If we assume the offset voltage VO,isindependent of temperature, the resulting temperaturecoefficient error due to a 5 mV VO$,for example, isapproximately

(11++ Vo,

TC error =1 10 X5mV

~,f TO = 1.26 VX300K

=132 ppm/ ‘C. (4)

That is, a temperature coefficient on the order of 132ppm/ 0C will result in the reference output temperaturecoefficient from a 5 mV temperature-independent offsetvoltage in the operational amplifier if the reference istrimmed assuming the offset is zero. This offset errorcontribution can be reduced by making AVBEbigger, ineffect decreasing the gain factor (1+ R2 /R1) as implied by(l). One way to achieve this is to obtain AVBEby taking thedifference of two cascaded transistor strings discussed laterin Section IV. In this work, however, offset cancellationtechnique is employed to further reduce this error while thecascading scheme is used for the PTAT current generation.

B. Bias Current Variation

If the resistors RI, R2, and R3 have a zero temperature

coefficient, then the bias currents in transistors QI and Qzmust be PTAT since the voltage across RI is PTAT. Thefinite temperature coefficient of actual resistors formedfrom the source-drain diffusion or from polysilicon layersresults in non-PTAT variation of the bias current. This inturn causes an additional component in the temperaturevariation of the V~~ term in the output. If only the firsttwo terms of (2) and (3) are taken, the V~~ is given by

VJn AV~~ = V~ln #- = V~ln ~

S1 1 S1

V~ln A= VJn Rl(%)

Rl(To)~sl ‘V’in RI(T)(5)

where TOis the reference temperature, usually room tem-perature. Note that the first term is the V~~ variation thatresults when there is no resistor temperature coefficient,and the second is that which results when a temperaturecoefficient is present, Further insight can be obtained byexpanding this second term as a Taylor series in tempera-ture about TO,and neglecting higher order terms:

‘BE = ‘BEl,dezd – ‘T

;$$ ~(T-To)-VT& $ $T-TO)2- . . . . (6).—0 .

From this relation it can be seen that even a purely linearvariation in resistor value with temperature results in anoutput temperature variation with both PTAT and PTAT2temperature variation components. Assuming the resistortemperature behavior is known and reproducible, the PTAT

portion can be compensated by simply changing the targettrim value of the output voltage. For example, (6) can beused to show that a 1000 ppm/ 0C resistor TC wouldresult in a – 21 ppm/ 0C reference output TC, whichcould be removed by simply raising the output voltage trimtarget by approximately 8 mV. However, cancellation ofPTAT2 term precisely requires curvature compensationdiscussed later.

C. Other Effects

The effects of various nonidealities, including base resis-tance, ~ mismatch, @ variations with temperature, and ~variations with collect current can be evaluated with theuse of (l), (2), and (3). Which of these effects is the mostimportant in a given circuit application is strongly depen-dent on the nature of the bipolar transistors in the particu-lar technology used. If the well (base) doping is particularlylight, as is often the case, then the intrinsic base resistanceeffect, represented by the last term in (3), may well be themost important. The temperature coefficient in the outputdue to this term is given by

‘cerrOr=(l+wwb*+@+2a(7)

For example, assuming a 2 kfl base resistance with 1000ppm/ 0C TC, a 30 PA PTAT bias current level, a /3 of 150,and a ~ TC of 7000 ppm/ 0C, an output TC of – 8.6ppm/ 0C results. As in the case of the bias current varia-tion, this can be partly compensated by modifying the trimtarget voltage if these parameters are reproducible. Theother errors mentioned above are negligible if transistorperformance is reasonably good. Another error source re-sults from the temperature coefficient of the ratio of thediffused resistors RI and R2. Data presented later showthat for resistors used in this experimental work a differen-tial ratio TC of 1 to 2 percent is achieved. Fortunately, thiserror is negligible compared to those already discussed.

III. CURVATUREIN BANDGAP REFERENCES

For a bandgap reference which is ideal in the sense thatthe operational amplifier is ideal, the bipolar transistorshave infinite current gain, zero intrinsic base resistance,and have perfect exponential junction relationships, andthe bandgap of silicon varies linearly with temperature, theoutput voltage is typically given by [10]

()V,c~=VgO+V~(4–n–a) l+ln$ (8)0

where VgOis the extrapolated silicon bandgap at O K, n isthe exponent of the mobility variation in the base of thebipolar transistor (typically about 0,8), a is the exponent ofthe temperature variation of the bias current (1 for PTATbias current, for example), and TOis the temperature atwhich the reference output temperature coefficient is zero,

SONGANDGRAY:PRECISIONCURVATURE-COMPENSATEDCMOSBANDGAPREFERENCE 637

usually chosen to be near room temperature. Equation (21)derived in the Appendix is the more general form of (8).This relation illustrates the well-known fact that even foran ideal bandgap with an optimally chosen TO,the outputvoltage as a function of temperature displays a curvaturewhich causes it to decrease both for temperatures higher orlower than TO.Usually, the practical performance aspect ofinterest is the maximum total variation of the outputvoltage over the range of temperatures. A further complica-tion is the fact that the bandgap of silicon in fact does varywith T2, as well as linearly with temperature [11], [12]. Thishigher order temperature variation adds a curvature term,increasing the effective TC even for optimally adjusted

-references. These effects together combine to give a bestachievable TC of about 25 ppm/ 0C for a temperaturerange of –55° C to 125° C.

Several approaches have been suggested for curvaturecorrection. If the quantity (4 – n – a) in (8) could be madezero, then there would be no curvature other than thecurvature of the silicon bandgap. This could be achievedfor example by using a very strongly temperature-depen-dent bias current or by linearizing V~~directly [5]. Severalauthors have proposed simply adding in higher order tem-perature-dependent terms in the output to cancel thePTAT2 term of the output voltage variation [4]. This is theapproach used in this paper to be described in the nextsection.

IV. PRECISION SWITCHED-CAPACITOR CMOS BGR

TECHNIQUE

In order to implement voltage references in CMOS tech-nology which have performance approaching that achiev-able in bipolar technology, special steps must be taken tocounteract the relatively poor performance of CMOS opamps and CMOS compatible bipolar transistors. In addi-tion, curvature compensation, already widely applied inbipolar references, must be incorporated. In this section,the implementation of the techniques in CMOS technologyis described.

A. Curvature Compensation

The overall concept of BGR temperature compensationis illustrated in Fig. 3 and general BGR temperature com-pensation techniques are described in the Appendix. Thefirst step is to add a PTAT correction voltage KVT to V~~to cancel out the linear temperature variation of V~~.Afterthe PTAT correction voltage is added, the reference outputV,efwill exhibit mostly the quadratic temperature variationas shown in Fig, 3. If a PTAT2 correction voltage IV’; isadded to that to cancel out the quadratic temperaturevariation of 1“~~,the final reference output V,efshould driftonly due to higher order temperature variations and a zerotemperature coefficient is achieved at TO.One implementa-tion of a switched-capacitor bandgap reference which em-bodies curvature compensation as well as offset-cancelledamplification is illustrated in Fig. 4. The gain G of the gain

KV~ , FV;

~vref

I

1

Emi!rTO T To T T. T

Fig. 3. Curvature-compensationconcept (not seated).

I Temp Indep [Tll I ID

Current

Generator b----lI , I

I

Fig. 4, Overall schematic of the curvature-compensatedswitched-capa-citor CMOSbandgap reference.

block is determined by the capacitor ratio C2/Cl. Thecurrent 10 is temperature-independent (TI) while 1~ isPTAT. The bias current 1~ is also TI.

If the effects of the base current and the base spreadingresistance are neglected, the reference output V,~fis givenby

where

(9)

‘vT1nA+2v&’)+M:r+””” ’10)The inclusion of the PTAT2 voltage means that the trimprocedure for the reference consists of two steps, one togive the correct output voltage for the uncompensatedreference, and one to trim the value of the PTAT2 voltagethat is added in. A key advantage of the circuit configura-tion chosen is that it allows the PTAT2 component to beadjusted independently from the basic reference. The firstpart of the trim procedure is to disconnect the PTAT2component (set 1~ to zero), and trim the absolute outputvoltage. In the particular experimental device described

638 IEEEJOURNALOF SOLID-STATECIRCUITS,VOL.SC-18,NO. 6, DECEMBER1983

Voo

VssFig 5. PTAT and TI current generators for the bias currents IT and 10.

here, it is most convenient to do this with a combination ofa capacitor array to adjust the Cz/C1 ratio, and a resistorstring to provide fine adjustment through adjustment ofthe bias current Id. Even though two different physicaltrim arrays are involved, in effect one trim operation isperformed and a total resolution of approximately 12 bitsis achieved in the absolute value of the final output voltage.Next the PTAT current 1~ is turned on and its ratio to 10 isadjusted with another resistor string to give a change in theoutput equal to the desired PTAT2 compensation value.Both trimming operations are done at room temperature.

The currents lT and 10 are generated using the circuitshown in Fig. 5, The bias current ID is generated in thesame manner as the TI current 10. The stacked-cascodeconnection formed by transistors Ml to kf~ causes theemitter currents of transistors Q6 and Q, to be equal.The same scheme is also employed for the matching of theemitter currents of transistors Qg and QIO. Transistors J4gand &l10form a start-up circuit for this self-biased circuit.As indicated, transistors Q1 and Q6 have emitter areaslarger by a factor of A than the remaining transistors.Therefore, the voltage developed across the resistor RI isPTAT and the current Z~ through RI is also PTAT. Thevoltage VOformed by the transistor Qg and the resistor R ~is approximately temperature independent. The tempera-ture stability of P’Ois not critical because it affects only thePTAT2 component of the output voltage (not PTAT). TheTI voltage VOis developed across R3 and the current 10through R ~ is also TI. Therefore, the current ratio 1~/10 iseasily trimmed by R ~.

In the presence of the mismatches of Ml – M2 andJ411– M12 transistor pairs, the voltages across RI and R ~deviate from the ideal values. If the gate-source voltagemismatches of MOS transistor pairs inclusive in the biascircuit of Fig. 5 are assumed to be V~l, V~2, and V~3,respectively, and current mirrors and p-n-p transistors areassumed to be ideal, the three bias currents 1=, 10, and IDare given by

1~ = ~ (2V~ln A + V~l), (11)1

Io=+(~+vm2) (12)3

and

ID=+(K+V.J,4

(13)

The factor 2 in (11) results from cascading transistors

Q4- Qti and Q5- Q7 @ reduce the error contribution of themismatch voltage V*l. For this application, cascading oftwo devices is enough for the PTAT current generation.Depending on applications, several transistors can becascaded to reduce the offset error contribution in such aBGR implementation, discussed in Section II. Substituting(11), (12), and (13) into (9) and (10), and neglecting higherorders, we obtain

= ‘BEl,deil + ~vT + ~v; + ~ (14)

where

~= ~++ ,(vT-vT)T+2yJ5vJ#vm,o0 110

C2R3V~ln A–4 cRv~ V.2+5VV. ‘3” (15)

110

The constant u represents the standard deviation (%) of thetemperature coefficient of R4. The error voltage V, is lessthan 1 mV at room temperature. Therefore, the tempera-ture coefficient uncertainty resulting from the mismatchvoltages is 50 times smaller than the uncertainty caused bythe op amp offset of existing designs given by (4).

B. Offset- Cancelled Amplification

In order to remove dc offsets from the amplifier, it isdivided into two stages as shown in Fig. 6. In the firstoffset-storage mode, all the MOS switches are closed to

SONGANDGRAY:PRECISIONCURVATURE-COMPENSATEDCMOSBANDGAPREFERENCE 639

s,

Vf I

● - Input Referred h .q = Vfz J I%

(c)

Fig. 6. Gam block which embodies offset-cancelled am Iification. (a)c?First offset-storagemode. (b) Second offset-storagemo e. (c) Amplifi-

cation mode.

sample the offset voltages of the individual op amps. In theprocess of opening the MOS switches $ and S2, thechannel charges are injected into the op amp summingnodes to load the capacitors Cl and Cz, The charge injec-tion differential voltage Vfl due to the mismatch of switchesS1 and S2 is sampled across Cl and C2 along with the offsetvoltage VO,l. In the second offset-storage mode, the firstgain stage charges the coupling capacitor to compensatefor the input differential voltage VI, After the switches S3and Sd are opened, two stages are connected in a feedbackamplification mode, and the amplification of AV~~ takesplace by the capacitor ratio C2/C1. When referred toinput, the feedthrough difference of the switches S3 and SJis reduced by the open-loop gain of the first stage. Note thebottom plate of one capacitor Cl should be connected tothe diode voltage in the actual reference as shown in Fig. 4.

A single-pole folded-cascode CMOS op amp configura-tion for Al and Az is shown in Fig. 7. Two amplifiers areidentical and designed to meet the following requirements:

1) moderate gain for each stage (100 to 300);2) single dominant pole per stage;3) inherent zero systematic offset voltage; and4) capacitor driving capability (15 pF for one stage and

100 pF for two stages).Transistors Mlp – M21 form a bias string for the ampli-

fier. The replica bias circuit formed by transistors Mlq – MITperforms a level shift and a differential to single-endedconversion, and reduces the inherent systematic offset. Inorder to limit the gain of each stage, the lower partcomposed of transistors J4d– Mj is not cascoded while theupper part Iv&– Mg is. The class-A source follower stagesformed by transistors Al10- M13 are added to meet thecapacitor driving capability. In the offset-storage modes,each op amp is stabilized by connecting a frequency com-

M,91 1

I k I I 4 i

Me M12 M9 M13

UI ~111M,e

I

[

I

M6 M, I

‘ ‘ ‘“iii’”K5W‘2FF+P+

v Ss

Fig. 7. Amplifierconfigurationfor Al and A~.

pensation capacitor between the high impedance node andthe ac ground ~,. When the two op amps are cascaded andthe feedback loop closed around the composite amplifier, aMiller capacitance is switched in from the high impedancenode of the second stage to the same node of the first stageto achieve a pole-splitting compensation.

C. Base Current Cancellation

In the CMOS process used, the current gain of substratep-n-p transistors is often limited and highly variable.Therefore, to compensate for the difference between thecollector current and the emitter current, the base currenthas to be returned to the emitter as shown in Fig. 8(a).However, a simpler approach is to replicate the base cur-rent and allow it to flow into the emitter as shown in Fig.8(b). The base current is cancelled with an accuracy ofabout 90 percent because the base currents typically matcheach other within 10 percent for the adjacent transistors ona single chip.

D. Base Resistance Cancellation

The effective series base resistance of the bipolar transis-tors consists of that produced by lateral flow in the baseregion under the emitter, and the extrinsic base resistancebetween the base contact and the active base. The former isbias dependent and difficult to predict, while the latter ismore straightforward to predict given device geomet~. Theapproach taken here is to include a lumped resistor R ~O~Pmade of the same n ‘-well diffusion material so as toachieve approximate tracking with temperature and pro-cess variations. The value of Rcompin Fig. 9 should be

‘-=(+3-+ (16)

For the process used here, the magnitude of the extrinsiccompensation resistance is about one quarter of the mea-sured intrinsic base resistance of p-n-p transistors with thesame geometry.

640 IEEEJOURNALOF SOLID-STATECIRCUITS,VOL.SC-18,NO.6, DECEMBER1983

~. i J

(a) (b)

Fig. 8. Basecurrent cancellationschemes.(a) lB returning. (b) ZBrepli-cation.

Intrinsic Base Resiseh

rbi

+,.

INTRINSIC RESISTANCE

~

- p._.__J.— ?‘~?

1“+

Extrinsic Compensation Resistance“- w,,,

~.

%iw = %,—b= rbl – rb,lA COMPENSATION RESISTANCE

(a) (b)

Fig. 9. Base resistance cancellation. (a) Extrinsic compensation resis-tance R .Omp. (b) llifference between intrinsic base resistance andextrinsic compensation resistance.

V. EXPERIMENTAND DISCUSSIONS

The experimental prototype circuit implementing theproposed reference was fabricated employing a self-alignedsingle-poly Si-gate CMOS process on a 20-30 0. cmboron-doped p-type (100) substrate. The gate oxide is 0.07pm thick and the drawn minimum feature is 6 pm. Fig. 10shows the microphotograph of the prototype chip and Fig.11 shows its output waveform as well as output sync pulse.

Experimental daka were gathered from seven representa-tive samples from one wafer. Every experimental chipcontains three types of reference voltages. The Type 1reference has no curvature compensation, no base currentcancellation. no base resistance cancellation. and no offsetcancellation, and amplification is performed by a resistorratio. The Type 1[ reference which uses a capacitor-ratioamplification has the cancellations of offset, base currentand base resistance, but no curvature compensation. How-ever, the Type 111[reference which also uses a capacitorratio amplification has all components of the Type IIreference plus curvature compensation.

Following the procedure described in Section IV and theAppendix, one sample was adjusted to give a minimumtemperature drift and the other six samples were trimmed

Fig. 10. Chip photo of the experimental prototype.

Fig. 11. Waveforms. (a) Output sync clock. (b) Vref.

at room temperature to an output voltage predeterminedfrom the first sample. Statistical data from seven samplesare summarized in Table I for three types of referencevoltages. The optimum values of the PTAT 2 correctionvoltage, the first-order corrected and second-order cor-rected V,,f’s at 250 C were found to be 61 mV, 1.256 and1.192 V, respectively. Estimating from the measured data,the parameters J&l, Vg02, and 4 – n – a necessary forspecifying the prototype bandgap reference were 1.181,1.158, and 2.623 V, respectively.

Note that the offset-cancelled amplification and com-pensation of rb and ~ effects give a factor of 5 improve-ment in temperature stability and its deviation over theapproach without any compensation. By curvature com-

SONGANDGRAY:PREC1S1ONCURVATURE-COMPENSATEDCMOSBANDGAPREFERENCE 64I

TABLE ISTATISTICSOFMEASUREDTEMPERATURECOEFFICIENTS

OF7 SAMPLES(ppm” C)

Standardoto70°c: Mean Deviation Minimum Maximum

Type I 105 43 42 167Type II 22.3 10.8 11.1 42T~e III 13.1 7.1 5.6 25.7

–55 to 125° C:

TWe I 185 56.5 107 273Type II 35.1 18.8 17.6 66.7Type III 25.6 10.5 12.1 39.9

0

AVre,

[mV)-5

~p:

Type I

1 I I

50 0 50 I00TEMPERATURE (“C )

Fig. 12. Typicaf measured temperature variations of three types ofreferences when they are optimally compensated.

TABLE IIPERFORMANCESUMMARY

V,ef 1.192V*lmVat25° CTC SeeTable IPower 12 mW with + 5 V supplyLoad 100 pF capacitorCycle time 5 ps+ PSRR 50 dB (de)– PSRR 60 dB (de)Clock RR 75 dBOutput noise 400 pV (500 kHz)

pensation, a factor of 2 further improvement was obtained.Fig. 12 compares graphically those three types of optim-ally-compensated bandgap references. The experimentalresults are summarized in Table II. To improve the powersupply rejection ratio (PSRR), the base of all p-n-p transis-tors should be biased at a constant voltage relative to thenegative supply line, Otherwise, the base width modulation(Early effect) will limit the PSRR of the reference,

The critical aspect of the design is the substrate p-n-ptransistor because the n ‘-well in CMOS processes usuallyhas a relatively high resistivity. In order to minimize theintrinsic base spreading resistance, the base contact sur-rounds the emitter junction as shown in Fig. 13, Theemitter junction and the base contact plug are separated by9 pm. By the surrounding base, the intrinsic base resistanceis reduced by a factor of 6 when compared to the parallelcontact of emitter and base. For the process used here, theestimated rb of this geometry is about 1.5 kfl. With thisgeometry, the observed emitter area reduction due to thebase crowding is insignificant over the 1 to 100 PA emitter

(a)

1I

\

I I i t

I I I I I I I

UB=rL

(b)

Fig. 13. Substrate p-n-p transistor. (a) A unit cell. (b) Drawn dime]sions of a unit cell (~m).

n-

current range. The current gain ~ is also relatively constantwithin this range. However, in the emitter current rangeover 100 p A, the base crowding effect is severe. Also, inthe emitter current range below 1 PA, the current gain ~decreases due to space charge recombination in theemitter-base junction. The unit cells of Fig. 13 were con-nected in parallel to obtain a multiple-emitter device. Thecurrent gain /3 is minimum at –550 C and the averagevalue at room temperature is 175. Temperature data for thep-n-p transistors and p+ diffused resistors in the n--well inthe particular technology used here are listed in Table III.The temperature coefficients of diffused resistors matcheach other within 1.2 percent.

One potential problem in the use of the substrate p-n-ptransistor is the fact that the dc collector current flows intothe substrake. If this current gives rise to a large enoughohmic drop in the substrate, it could initiate latchup. Tominimize the likelihood of this, each n ‘-well (base) wassurrounded by the p+ diffusion (collector) as shown in Fig.13. No latchup was observed during experimental measure-ments even under transient conditions.

VI. CONCLUSION

A precision curvature-compensated switched-capacitor

CMOS bandgap reference is reported whose monolithicprototype exhibits average temperature drifts of 13.1 and25.6 ppm/ 0 C over the commercial and military tempera-

IEEEJOURNALOFSOLID-STATECIRCUJTS,VOL.SC-18,NO. 6, DECEMBER1983

TABLE IIITEMPERATUJWDATAOFDIFFUSEDFWSISTORSAND p-n-p TRANSISTORS

(-55 to125”c)

StandardDiffused Resistors: Mean Deviation Minimum Maumum

Sheet resistance (Q/square) 68.9 3.1 64.6 72.1TCor R* 886 27.9 849 917Ratio of 6R /R** 5.952 0.02 5.9304 5.9794TC of 6R/R* 10.6 2,2 8.9 13.6

p-n-p Transistors:

Current gain /? at IE = 30 pA 175 83 91 273TCoffl* 6503 872 5471 7792

*TC unrt is ppm/ 0 C.**R and 6R are composedOf 40 and 240 squares of 6 pm-wide p + diffusion.

ture ranges, respectively, employing a straightforward room A. First-Order Temperature Compensationtemperature trim procedure without thin-film resistor andlaser trim. The design features second-order temperaturecompensation, simple room temperature trim up to 12-bitaccuracy and complete cancellation of the offset and long-term offset drift of CMOS op amps. A reference voltage isobtained by systematically adding first-order and second-order correction voltages to the emitter-base potential ofthe substrate p-n-p transistor. Each correction voltage isindividually trimmable to minimize temperature drift. Theproposed reference is compatible with a standard digitalCMOS process and is applicable to high-resolution mono-lithic CMOS data acquisition systems.

APPENDIX

BGR TEMPERATURECOMPENSATIONTECHNIQUES

Employing (6) and neglecting higher orders, the for-ward-biased diode voltage is given by [10]

V~~=Vg– V~[(4–n –a)ln T–ln EG]+HV~– LV~

(17)

where Vgis the bandgap of silicon which is a function ofbase doping [13] and temperature [11], [12], n and a areparameters illustrated in (8), E and G are the parameterswhose magnitude are insignificant in the temperature anal-ysis [10], and H and L are defined from (6)

H=T 1 dRORdTTO

and (18)

(19)

That is, if the bias current variation and the silicon band-gap curvature discussed in Sections II and III are included,the V~~in (17) is the actual diode voltage whose tempera-ture variation is to be compensated to give a temperaturestable reference voltage. In the next two subsections, first-and secondl-order temperature compensation techniquesare discussed in more detail.

If only the linear temperature variation of V~~in (17) iscompensated by adding the first-order correction voltageKVT to V~~, the reference output V,cfis

Vre.= VBE+ KVT

=Vg– V~(4–n–a)ln T

-t(K+H+h13G)vT– LV;. (20)

By equating the derivative of fi,f at TO to zero andeliminating the unknown constants, we obtain

dVg

- ‘+vT’4-n-a)(l+ln~)“f= ‘g – dT TO

-L++). (21)The first two terms and the last term of (21) result from thenonlinearity of the Si bandgap over temperature and thebias current variation, respectively, and will not disappearuntil higher order temperature variations are compensated.Without these, (21) @identical to (8). Tsividis [12] recentlyexplained the Si bandgap temperature dependence employ-ing equations from Bludau et al.’s [11]. From (21), thenominal voltage at TOis therefore

‘reflTO= Vgol + ‘TO(4– n – ~)+LV~ (22)

where

dVgvgol=vg(To)– ~ To =1.205 V. (23)

To

As commonly called, V,Ol is the linearly-extrapolated Sibandgap voltage at T= O K. Equation (22) indicates thatthe bias variation resulting from the temperature coeffi-cient of diffused resistors causes the nominal voltage differ-ent from a theoretical value.

B. Second-Order Temperature Compensation

If the linear and the quadratic temperature variations of

SONGANDGRAY:PRECISIONCURVATURE-COMPENSATEDCMOSBANDGAPREFERENCE 643

V~~ in (17) are compensated as illustrated in Fig. 3 byadding both the first-order correction voltage KV~ and thesecond-order correction voltage FV~ to V~~, the referenceoutput Vr~fis

~ef = VBE+ KVT + Fv;

=~– V~(4–n–a)ln7’

+( K+ H+ln EG)V~+(F– L)V~. (24)

By equating the first-order and the second-order deriva-tives of V,,f at TO to zero and eliminating the unknownconstants. we obtain

J&f = Vg-

Therefore,

where

d% 1 d2Vg

dT TOT– ~ dT2 ()Tz 1–2;

To

( )

+VT(4–fr-a)ln$++$ . (25)0

the nominal voltage at TOis

~eflTo=vgo2 + ~VT~4– n – (.X) (26)

dVg 1 d2VgJ’&2 = vg(To)– ~ TTo+y~ T: =1.179 V.

. To

(27)

Now Vg02 is the quadratically-extrapolated Si bandgapvoltage at T = O K. The voltage Vg02 is closer to the Sibandgap at T= O K than VgO1of (23). The theoretical valueof Vg(OK) is approximately 1.179 V [12]. The bias currentvariation no longer affects (26) because it is compensatedby the PTAT2 correction voltage.

Only after the PTAT voltage is added, the intermediatevoltage at TOis

1 d2Vg(V,, +KVT)lTO=Vgo2+ ~~ T: - LV;. (28)

To

Correspondingly, the magnitude of the PTAT2 voltageFV~ at TOis obtained by subtracting (28) from (26):

1 d2VgFV;ITO= ;VTO(4– n – a)– –—

2 dT2T:+ LV;. (29)

To

This PTAT2 correction voltage includes the inherent Sibandgap curvature as well as the bias current variation.Other error sources neglected can be included in (29) easilyin the same manner as the bias current variation. Nomatter how many error sources are included, the final V~~fgiven by (25) is independent of these instabilities as far astheir temperature variations are compensated properly.

[1]

[2]

[3]

[4]

[5]

[6]

[7]

[8]

[9]

[10]

[11]

,[12]

[13]

REFERENCES

R. J. Widlar, “New developments in IC voltage regulators,” IEEEJ. Solid-State Circuits, vol. SC-6, pp. 2-7, Feb. 1971.K. E. Kujik, “A precision reference voltage source,” IEEE J.Solid-State Circuits, vol. SC-8, pp. 222-226, June 1973.A. P. Brokaw, “A simple three-terminaf bandgap reference,” IEEEJ. Solid-State Circuits, vol. SC-9, pp. 288-393, Dec. 1974.C. R. Palmer and R. C. Dobkin, “A curvature corrected micro-power voltage reference,” in Proc. Int. Solid-State Circuits Conf.,Feb. 1981, pp. 58-59.G. C, M. Meijer, P. C. Schmafe, and K. van Zalinge, “A newcurvature-corrected bandgap reference,” IEEE J. Solid-State Cir-cuits, vol. SC-17, p . 1139–1143, Dec. 1982.

c?Y. P. Tsividis an R. W. Ulmer, “A CMOS voltage reference,”IEEE J. Solid-State Circuits, vol. SC-13, pp. 774-778, Dec. 1978.E. A. Vittoz and O. Neyroud, “A low-voltage CMOS bandgapreference,” IEEE J. Solid-State Circuits, vol. SC-14, pp. 573–577,June 1979.R. Gregorian, G. A. Wegner, and W. E. Nicholson, Jr., “Anintegrated single-chip PCM voice codec with filters,” IEEE J.Solid-State Circuits, vol. SC-16 p .322-333, Aug. 1981.

~ ‘zW. H. White, D. R. Lam e, F. Blaha, and I. A. Mack, “Char-acterization of surface c annel CCD image arrays at low lightlevels,” IEEEJ. Solid-State Circuits, vol. SC-9, pp. 1-14, Feb. 1974.P. R. Gray and R. G. Meyer, Ana@ris and Design of AnalogIntegrated Circuits. New York: Wiley, 1977, pp. 256.W. Bludau, A. Onton, and W. Heinke, “Temperature dependenceof the band~ap in Si,” J. Appl. Phys., vol. 45, pp. 1846-1848, 1974.Y, P. Tsividls, “Accurate anafysis of temperature effects in Ic – V~Fcharacteristics with application to bandgap reference source,; IEEEJ. Solid-State Circuits, vol. SC-15, pp. 1076-1084, Dec. 1980.J. W. Slotboom Wd H. C. DeGraaf, “Measurements of bandgapnarrowing m Si bipolar tranwstors,” Solid-State Electron., vol. 19,pp. 857-862, 1976.

~,,,/,,.~$:, Bang-Sup Song (S’79) was born in Kunsan,,,, ,$~<’; Korea. He received the B.S. degree in electronicengineeringfrom the Seoul National University,

: Korea, in 1973, the M.S. degree in electrical~, ‘,’ engineering from the Korea Advanced Institute+ ,,,,: of Science, Korea, in 1975, and the Ph.D. degree~ .,%

... in electrical engineering from the University of

1

%<,r California, Berkeley, in 1983.From 1975 to 1978, he was a member of a

..—..., research staff in the Electronics and Communica-tions Division of the Agency for Defense Devel-

opment, Korea. During 1979, he was a graduate student at the Universityof Texas, Austin. At present, he is working at Bell Laboratones, MurrayHill, NJ. His interest is in MOS integrated circuit design.

Paul R. Crav (S’65–M69–SM76–F’80) was bornin Jonesbo;o; AK, on December 8,’1942. Hereceived the B.S., MS., and Ph.D. degrees fromthe University of Arizona, Tucson, AZ, in 1963,1965, and 1969, respectively.

In 1969 he joined the Research and Develop-ment Laboratory, Fairchild Semiconductor, PaloAlto, CA, where he was involved in the applica-tion of new technologies for analog integratedcircuits, including power integrated circuits anddata conversion circuits. In 1971 he joined the

Department of Electrical Engineering and Computer Sciences, Universityof California, Berkeley, where he is now a Professor. His research interestsduring this period have included bipolar and MOS circuit design, electro-thermal interactions in integrated circuits, device modeling, telecommuni-cations circuits, and analog-digital interfaces in VLSI systems. He is thecoauthor of a college textbook on anrdog integrated circuits. He has beencorecipient of Best Paper Awards at the Intemationaf Solid-State CircuitsConference, the European Solid-State Circuits Conference, and was core-cipient of the IEEE R. W. G. Baker Prize in 1980. He served as Editor ofthe IEEE JOURNALOF SOLID-STATECIRCUITSfrom 1977 through 1979,and as Program Chairman of the 1982 Intemationaf Sotid-State CircuitsConference.