ECE 4430 Project -1

Beta Multiplier and Bandgap Reference Design

Aneesh Pravin Kulkarni

Fall 2014

“I have neither given nor received any unauthorized assistance on this project”

Beta Multiplier - Design Procedure

• Given: Vref = 1.5V, Iref = 20uA, TSMC 0.18um process, VDD = 2.5V

• If we use the usual cascode topology and take Vref = VGS1, then even if we assume zero overdrive, we get VDDmin = Vthn + Vthp+ Vref = 0.37 + 0.38 + 1.5 = 2.25 V.

• This value is quite high as compared to the nominal value of VDD that is 2.5V.

• Hence we take Vref from the gate of the upper NMOS, that is Vref = VGS1 + VGS2. Also, let VGS1 = VGS2 = VGS, then VGS = Vref/2 = 0.75V.

• Now VGS = 0.75V and ID = 20uA gives (W/L)1 = 1.116.

• On plotting the ID v/s VDS characteristics we find that actually the required (W/L) is 1.39.

• If we take L1 = 2*Lmin = 0.36 um, then W1 = 0.50 um.

• In order to reduce the power consumption, we make the size of the upper left PMOS K times that of the upper right PMOS. Hence the current in the right branch is 1/K times that in the left branch. The size of the two bottom NMOS’s is the same, but difference in the currents causes a difference in their VGS which is dropped across R.

• R = 2*(K-sqrt(K))/(Beta1(VGS-Vthn)). Putting values, we get R = 104.7 kohms. This is tuned further in simulations.

• The W/L ratios of the MOS transistors are made large to reduce VDDmin. At the same time, the L of each of these transistors should be large to reduce the sensitivity to VDD. For the startup, both transistors are long so as to reduce the current drawn by the startup, as well as to increase VDDmax.

• Finally, TCR is chosen from Baker Table 4.1 so as to minimize sensitivity to temperature. The best choice is TCR = 3800ppm.

Beta Multiplier – Circuit Diagram

Beta Multiplier – Temperature Sweep and Temperature Coefficient

Temperature Sweep from -20 to 100 C:

Vref changes by 70mV over 120C

Iref changes by 4uA over 120C

Temperature Coefficient:

TC(Vref) = 380 ppm/C

TC(Iref) = 680 ppm/C

Beta Multiplier – Supply Sweep and Supply Sensitivity

VDDmin = 2.0V, VDDmax = 4.5V Sensitivity to VDD:

S(Vref, VDD) = 800ppm at 2.5V

S(Iref, VDD) = 3640 ppm

Beta Multiplier – Start up delay and PSRR

Pulse of 2.5V applied to VDD at 0 sec.

Observed start up delay = 0.8s

For frequency sweep from 1 Hz to 100 MHz:

Best PSRR = -68.25dB (At low frequencies upto 500Hz)

Worst PSRR = -3.7 dB (At 100 MHz)

Beta Multiplier – Summary

Parameter Target Actual (Simulated Value)

Supply (V) 2.5 2.5

Vref (V) 1.5 1.5004

Max Supply Sensitivity (ppm) within ±10% of VDD 500 860

Max Temp Sensitivity (ppm @ 'C) 50 @ 26 380ppm/C = 9980ppm

Max Power consumption (uW) 55 56.42

Iref (uA) 20 20.0366

∆Iref (uA) with ∆VTHn = 10% and ∆VTHp = 10% - 0.0731, -0.0077

∆Iref(uA) with ∆R= 10% around nominal value - 5.09

∆Iref (uA) with ∆VDD = 10% around nominal value - 0.0077

∆Vref (mV) with ∆VTHn = 10% and DVTHp = 10% - -78, -0.007

∆Vref (mV) with ∆R= 10% around nominal value - 66

∆Vref (mV) with ∆VDD = 10% around nominal value - 1

Min/Max Supply Voltage that the circuit is still working - 2.0, 4.45

TCIref (ppm/C) and TCVref (ppm/C) - 680, 380

Resistor Value (Ohm) and TCR1 - 93.6k, 3800ppm/C

Bandgap Reference- Design Procedure

• Given: Vref = 1.5V, Iref = 20uA, TSMC 0.18um process, VDD = 2.5V

• If we use the usual cascode topology, the value of Vref is fixed to around 1.2 V. Therefore, we modify the topology to include an extra resistor branch to generate PTAT + CTAT current, which is then mirrored and passed through a resistor (N*R). Since the value of N is variable, we have control over Vref.

• In order to reduce power consumption, we make size of M3T and M4T equal to 1/P times size of M1. Let P = 10. So the current through M3T and M4T is only 2uA.

• For this topology, the current through M3T and M4T is I = {n*VT*ln(K)/R} + VD/(L*R). And, Iref = P*I and Vref = N*R*Iref

• Using above equations, and taking K =8, the value of L which gives dVref/dT = 0 is L = 9.052.

• Substituting this value in the expression for I gives R = 60.17 kohms

• Now, N = Vref/(R*Iref) gives N = 12.5

• Hence the calculated values of resistors are R = 60.17 kohms; LR = 544.6 kohms; NR = 75.21 kohms. These values are tuned in simulations to get TC(Vref) = 0.

• The W/L ratios of the MOS transistors are made large to reduce VDDmin. At the same time, the L of each of these transistors should be large to reduce the sensitivity to VDD. For the startup, both transistors are long so as to reduce the current drawn by the startup, as well as to increase VDDmax.

• Finally, TCR’s are chosen from Baker Table 4.1 so as to minimize sensitivity to temperature.

Bandgap Reference – Circuit Diagram

Beta Multiplier – Temperature Sweep and Temperature Coefficient

Temperature Coefficient:

TC(Vref) = 2.63 ppm/C

TC(Iref) = -3800 ppm/C

Beta Multiplier – Supply Sweep and Supply Sensitivity

VDDmin = 2.0V, VDDmax = 3.75V Sensitivity to VDD:

S(Vref, VDD) = 640*2.5 =1589ppm at 2.5V

S(Iref, VDD) = 640*2.5= 1600 ppm at 2.5V

Beta Multiplier – Start up delay and PSRR

Pulse of 2.5V applied to VDD at 0 sec.

Observed start up delay = 1s

For frequency sweep from 1 Hz to 100 MHz:

Best PSRR = -73.44dB (At low frequencies upto 500Hz)

Worst PSRR = -0.297 dB (At 100 MHz)

Beta Multiplier – Summary

Parameter Target

Actual (Simulated

Value)

Supply (V) 2.5 2.5

Vref (V) 1.5 1.508

Max Supply Sensitivity (ppm) within ±10% of VDD 500 1800

Max Temp Sensitivity (ppm @ 'C) 50 @ 26 2.63ppm/C = 68.4ppm

Max Power consumption (uW) 55 62.5

Iref (uA) 20 19.978

∆Iref (uA) with ∆VTHn = 10% and ∆VTHp = 10% - 0.1762, 0.085

∆Iref(uA) with ∆R1*= 10% around nominal value - 0.6

∆Iref (uA) with ∆VDD = 10% around nominal value - 0.003

∆Vref (mV) with ∆VTHn = 10% and ∆VTHp = 10% - 0.06, 2

∆Vref (mV) with ∆R1*= 10% around nominal value - 60

∆Vref (mV) with ∆VDD = 10% around nominal value - 1

Min/Max Supply Voltage that the circuit is still working - 2.0V, 3.75V

TCIref (ppm/C) and TCVref (ppm/C) - 3800, 2.63

Resistor Value (Ohm) and TCR1 -

60.17k, 3300ppm/C

552k, 3800 ppm/C

552k, 3800ppm/C

* Changing only R1

Design Challenges

• Since Vref = 1.5V which is a significant fraction of VDD (2.5V), this leaves a small headroom for all the upper transistors in the cascode.

• ince this is a 180nm process, short channel effects cannot be neglected. Also, the value of the output resistance of the transistors is lower. This makes the Vref and Iref more sensitive to supply voltage variations. To counteract this, we need to increase the L of the transistors. However, the W/L ratio also needs to be large to keep Vdd,min at a reasonable value. In effect this requires an increase in the W as well as L.

• In the beta multiplier, for the given specifications, we would need a TCR of over 5000 ppm to get TC(Vref) = 0. However, this is not available to us in Baker P88. Therefore, we reduce the VGS1 and take Vref from the gate of the upper transistor. (This also reduces the VDD,min) Now the TCR required is 4300 ppm, which is a better match to the available 3800 ppm.

• In the beta multiplier, the power consumption can be further reduced by increasing the value of K (that is decreasing the current through the right branch further). But this increases the resistor value beyond 150kohms.

• The value of VDD,max can be increased further but this requires the sourcing transistor in the start up to be very long.