ECE 4430 Fall 2016

Op-Amp Circuit Design Project

Group One

Patrick Goley

December 6th 2016

Honor Pledge: I have neither given nor received any unauthorized assistance on this project.

ECE 4430 Fall 20162

Ref-Gen Detailed Schematic

All branch currents are 10 uA

11 Branches total, Pdis ~ 110 uW

Robust topology with good VDD

flexibility

Project Spec: VDD = 1.2 V

BMR

generates

Vbiasp

Circuit

to use

Vbiaspto

create

other

biases

ECE 4430 Fall 20163

Dif-Amp Detailed Schematic

PMOS Diff-Amp

Itail = 31 uA

Topology Summary: Parallel PMOS and NMOS Folded Cascode OTA with Class AB

Push-Pull Output Stage

NMOS Diff-Amp

Itail = 31 uA

Folded Cascode

ID(center 4) = 18 uA

ID(top 2 & bottom 2) = 33.5 uA

Class AB

Push-Pull Output

Buffer

ID = 85 uA

(50/2) (50/2)

W/L values are labeled for each device.

For physical values scale by 50 nm.

(100/2) (100/2)(300/2)

(150/2)

(150/2)

(300/2)

(200/2) (200/2)

(400/2) (400/2)

(600/2)

(1200/2)

(85/2)(85/2)

(170/2) (170/2)

(25/2)

(25/2)(50/2) (50/2)

ECE 4430 Fall 20164

Dif-Amp Design

Selected Parallel PMOS/NMOS Folded Cascode OTA to meet ICMR requirement

ICMR requirement is 0.2V to 1.2V

NMOS folded cascode OTA and meet upper requirement but cant quite meet lower requirement

VC,min(NMOS, FC OTA) = 1VGS + 2VGS,SAT

To make VC,MIN < 0.2 the I would have to use devices of unreasonably large widths

To avoid this I choose to meet the ICMR requirements by using adopting the parallel

NMOS/PMOS topology (which can give better than rail-to-rail ICMR)

Sizes of the bottom and top devices have been scaled as

Selected Class AB Push Pull Output stage to save power, add a small amount of gain, and act as

a buffer so I can drive a load which is not purely capacitive (100K Ohms // 5 pF)

Needed to scale the width (and therefore the bias current) in the AB output stage to meet my

slew rate requirement. I optimized this scaling by looking at the derivative of Vout, with respect to

time, across the heavy load during a large pulse input.

Tried to increase CMRR and (reduce power) by keeping tail current bias currents as low as

possible while still meeting slew rate requirement, since ro, tail is proportional to 1/ID,tail and ICMR

prop. to Ro,tail

ECE 4430 Fall 2016

Transient

Simulations

Open Loop

Gain

CMRR

Simulations

5

Virtuoso Testbench Circuits

PSRR

Simulations

Power Supply

And Input

Voltage

ECE 4430 Fall 20166

Open-Loop gain (with load)

AOL = 67.1 dB

f-3dB = 44kHz

fun = 117MHz

PM = 45.8o

ECE 4430 Fall 20167

Open-Loop gain (no load)

AOL = 67.4 dB

f-3dB = 44kHz

fun = 102MHz

PM = 79.0o

ECE 4430 Fall 20168

CMRR and CM-Gain

CMRR = 93.4 dB

f-3dB(CMRR) = 1.26MHz

ACM = -26.0 dB

ECE 4430 Fall 20169

Step Transient Response

511.6 ns 524.9 ns 551.7 ns 564.9 ns

trise = 13.3 ns (10% to 90%)

tfall = 13.2 ns (90% to 10%)

tsettle = 28.5 ns (99.9% of Vfinal)

ECE 4430 Fall 201610

Slew Rate

This is the time

derivative of Vout

from the previous

slide

Positive SR = 127 V/us then 80 V/us

Negative SR = 192 V/us then 88 V/us

ECE 4430 Fall 201611

Power Consumption

Total current pulled

from VDD during

previously shown pulse

response

This current

includes the

power to the

BMR (114 uA)

Pdis(zero input) = (267-114)uA*1.2V = 183.6 uW

Requirement = 200uW

ECE 4430 Fall 201612

ICMR

Sweep of VCM

versus Vout with no

small signal input

ICMR = 0V 1.2 V

ECE 4430 Fall 201613

Min and Max VDD

VDD(min) = 0.6 V

VDD(max) = 2.5 V

Sweep of VDD

versus Vout with no

small signal input

Vout

VCM

ECE 4430 Fall 201614

Output Voltage Swing

Transient

Response with

unity-gain FB and

Vdi = 800 mV

sinusoid @ 10kHz

(VCM = 600 mV)

Vout Swing = 70 uV 1.19 V

ECE 4430 Fall 201615

PSRR

vout / v+

vout / v-

PSRR+ = 67dB (-5 dB) = 72 dB

PSRR1 = 67dB (-0 dB) = 67 dB

ECE 4430 Fall 201616

Input Referred Noise

ECE 4430 Fall 201617

THD for Full Output Swing

1st 5 Harmonics

Vcm = 600 mV

|Vout(ac)| = 600mV @ 10kHz

THD = 0.12%, -58dB

ECE 4430 Fall 201618

Specifications Summary 2

Specification Target Simulation Comments

Dif-Amp Topology N/A Dual-Folded Cas OTA+AB -

Ref-Gen Topology N/A BMR -

Min VDD N/A 640 mV @ VCM = 600 mV

Max VDD N/A 2.5 V @ VCM = 600 mV

Differential Gain 100 dB 67 dB With Load

CMRR 150 dB 93.4 dB -

Ref-Gen Power Consumption N/A 137.3 uW -

Op-Amp Power Consumption 1 200 uW 183.6 uW With zero input

Op-Amp Power Consumption 2 N/A 376.8 uW With no load (max)

Total Power Consumption N/A 513.6 uW With no load (max)

Positive Slew Rate 80 V/us 127 V/us, 80 V/us 1st peak, 2nd peak

Negative Slew Rate 80 V/us 192 V/us, 86 V/us 1st peak, 2nd peak

ICMR [V] 0.2 1.2 0 1.2 -

Output Swing 0.1 1.1V 70 uV 1.19 V -

ECE 4430 Fall 2016 19

Specifications Summary 2

Specification Target Simulation Comments

VDD PSRR N/A 72 dB -

GND PSRR N/A 67 dB -

Nominal Output Voltage N/A 599.984 mV VCM = 600 mV, w/ Load

Input Offset Voltage N/A 18 uV With Load

Unloaded Bandwidth N/A 44 kHz -

Loaded Bandwidth 35 kHz 44 kHz -

Gain-Bandwidth Product N/A 117 MHz / 102 MHz With / Without Load

Compensation Cap N/A 490 fF and 245 fF -

Phase Margin 45.0o 45.8o / 79.0o With / Without Load

Rise Time N/A 13.3 ns 10% to 90%

Fall Time N/A 13.2 ns 90% to 10%

Settling Time N/A 28.5 ns 99.9% of Vfinal

Input Referred Noise N/A 315nV/sqrt(Hz) @ 1kHz

THD for full swing output N/A 0.12%, -58dB |Vout|= 600 mV, 1st 5 Har

ECE 4430 Fall 201620

Challenges & Possible Improvements

Challenges:

Open Loop Gain was the biggest challenge (100dB target)

Tried using gain enhancement. Used a variety of different topologies for drain

regulation in the folded cascode structure (simple diff amp, simply OTA, cascode OTA)

Simple Diff amp and OTA degraded CMRR and increased power consumption, and

only increasing the gain slightly

Cascode OTA gave me about 99 dB gain and 110 CMRR I thought this might work

then I saw this the output occulated for small step inputs I did not have enough time

to fully debug this issue (spent several days on it).

Ultimately decided against drain regulation because the trade-offs were not worth it.

Possible Improvements:

I would like to continue to debugging the oscillation issue described about. I would like to

see if I can use drain regulation to increase the open loop gain.

If I can use drain regulation to increase the gain without also increasing the common mode

gain, (as I was nearly able to do with the cascode OTA) then the CMRR would also increase

by the same amount - providing a path to increase both AOL and CMRR.