53011785 Vlsi Lab Manual

EX. 1 IMPLEMENTATION OF BASIC LOGIC GATES IN FPGA

AIM: To design, synthesize, simulate, implement and program the basic logic gates in FPGA.

TOOLS REQUIRED: SOFTWARE:

XILINX ISE 9.1iHARDWARE:

XILINX - Spartan kit XC3S400TQ144, Power supply Adapter, Parallel port cable, FRC connector, GPIO card - II

ALGORITHM:1. Start the program.2. Declare the input and output variables.3. Declare the output as register data type.4. Use PROCEDURAL construct statements (behavioral modeling) for Verilog code.5. Write the functionality of the gates.6. Terminate the program.

THEORY:AND GATE:

The AND gate performs logical multiplication which is most commonly known as the AND junction. The operation of AND gate is such that the output is high only when all its inputs are high and when any one of the inputs is low the output is low.

Y = a & bOR GATE:

The OR gate performs logical addition which is most commonly known as the OR junction. The operation of OR gate is such that the output is high only when any one of its input is high and when both the inputs are low the output is low.

Y = a | bNOT GATE:

The Inverter performs a basic logic gate function called Inversion or Complementation. The purpose of an inverter is to change one logic level to opposite level. When a high level is applied top an inverter, the low level will appear at the output and vice versa.

Y = ~aNAND GATE:

The term NAND is derived from the complement of AND. It implies the AND junction with an inverted output. The operation of NAND gate is such that the output is low only when all its inputs are high and when any one of the inputs is low the output is high.

Y = ~(a & b)NOR GATE:

The term NOR is derived from the complement of OR. It implies the OR junction with an inverted output. The operation of NOR gate is such that the output is high only when all its inputs are low and when any one of the inputs is high the output is low.

Y = ~(a | b)

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EX-OR GATE:The output is high only when the inputs are at opposite level.

Y = a ^ bEX-NOR GATE:

The output is high only when the inputs are at same level.Y = ~(a ^ b)

PROGRAM:

Verilog Code for basic logic gates

module allgates(A, B, not1, or2, and3, nor4, nand5, xor6, xnor7);input A;input B;output not1;output or2;output and3;output nor4;output nand5;output xor6;output xnor7;

reg not1;reg or2;reg and3;reg nor4;reg nand5;reg xor6;reg xnor7;

always@(A or B)begin

not1 = ~ A;or2 = A | B;and3 = A & B;nor4 = ~ (A | B);nand5 = ~ (A & B);xor6 = (A ^ B);xnor7 = ~ (A ^ B);

end

endmodule

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UCF file (User constraint file)

NET "A" LOC = "p74" ;NET "and3" LOC = "p86" ;NET "B" LOC = "p76" ;NET "nand5" LOC = "p89" ;NET "nor4" LOC = "p87" ;NET "not1" LOC = "p84" ;NET "or2" LOC = "p85" ;NET "xnor7" LOC = "p92" ;NET "xor6" LOC = "p90" ;

PROCEDURE:

Software part

1. Click on the Xilinx ISE9.1i or Xilinx Project navigator icon on the desktop of PC. 2. Write the Verilog code by choosing HDL as top level source module.3. Check syntax, view RTL schematic and note the device utilization summary by double

clicking on the synthesis in the process window.4. Perform the functional simulation using Xilinx ISE simulator.5. Open a new UCF file and lock the pins of the design with FPGA I/O pins.6. Implement the design by double clicking on the implementation tool selection.7. Create programming file (i.e., bit file) for downloading into the specified device.

Hardware part

1. Connect the power supply cable to the FPGA kit using power supply adapter.2. Connect FPGA board to parallel port of PC using parallel port cable.3. Connect FRC1 of FPGA board with the switches (i/ps) of GPIO card - II using FRC

cable.4. Connect FRC2 of FPGA board with the LEDs (o/ps) of GPIO card - II using FRC

cable.

SYNTHESIS REPORT:

Device Utilization Summary (estimated values)

Logic Utilization Used Available UtilizationNumber of Slices 4 3584 0%Number of 4 input LUTs 7 7168 0%Number of bonded IOBs 9 97 9%

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RTL Schematic Representation – Top Level

RTL Schematic Representation – Gate Level

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SIMULATION REPORT:

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RESULT:

Thus the basic logic gates were designed using Verilog HDL and it was simulated, synthesized, implemented and programmed in the FPGA device.

EX. 2 IMPLEMENTATION OF HALF ADDER AND FULL ADDER IN FPGA

AIM:

To design, synthesize, simulate, implement and program the Half adder and Full adder in FPGA.

TOOLS REQUIRED:

SOFTWARE:XILINX ISE 9.1i

HARDWARE:XILINX - Spartan kit XC3S400TQ144, Power supply Adapter, Parallel port cable, FRC connector, GPIO card - II

ALGORITHM:

1. Start the program.2. Declare the input and output variables.3. Declare the output as register data type.4. Use PROCEDURAL construct statements (behavioral modeling) for Verilog code.5. Terminate the program.

THEORY:

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HALF ADDER:

The half adder consists of two input variables designated as Augends and Addend bits. Output variables produce the Sum and Carry. The ‘carry’ output is 1 only when both inputs are 1 and ,sum’ is 1 if any one input is 1. The Boolean expression is given by, sum = x ^ y

carry = x & y

FULL ADDER:

A Full adder is a combinational circuit that focuses the arithmetic sum of three bits. It consists of 3 inputs and 2 outputs. The third input is the carry from the previous Lower Significant Position. The two outputs are designated as Sum (S) and Carry (C). The binary variable S gives the value of the LSB of the Sum. The output S=1 only if odd number of 1’s are present in the input and the output C=1 if two or three inputs are 1.

sum = x ^ y ^ zcarry= (x & y) | (y & z) | (x & z)

PROGRAM:Verilog code for half adder

module halfadder(a, b, sum, carry);

input a;input b;output sum;output carry;

reg sum,carry; always@(a or b)

begin sum=a^b;

carry=a&b; end

endmodule


NET "a" LOC = "p74" ;NET "b" LOC = "p76" ;

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NET "carry" LOC = "p85" ;NET "sum" LOC = "p84" ;

SYNTHESIS REPORT:





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SIMULATION REPORT

PROCEDURE:

Software part

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Hardware part



cable.

PROGRAM:

Verilog code for full adder

module fulladder(a, b, cin, sum, cout);

input a;input b;input cin;output sum;output cout;

reg sum,cout;

always@(a or b or cin)

begin sum=a^b^cin;

cout=(a&b)|(b&cin)|(cin&a); end

endmodule


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NET "a" LOC = "p74" ;NET "b" LOC = "p76" ;NET "cin" LOC = "p77" ;NET "cout" LOC = "p85" ;NET "sum" LOC = "p84" ;

PROCEDURE:

- follow the Half adder procedure

SYNTHESIS REPORT:





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SIMULATION REPORT

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RESULT:

Thus the half adder and full adder were designed using Verilog HDL and it was simulated, synthesized, implemented and programmed in the FPGA device.

EX. 3 IMPLEMENTATION OF 4:1MUX AND 1:4 DEMUX IN FPGA

AIM:To design, synthesize, simulate, implement and program 4:1 multiplexer and 1:4

demultiplexer in FPGA.

TOOLS REQUIRED:



ALGORITHM:1. Start the program.2. Declare the input and output variables.3. Declare the output as register data type.4. Use PROCEDURAL construct statements (behavioral modeling) for Verilog code.5. Terminate the program.

THEORY:

MULTIPLEXER

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A Multiplexer is a Combinational circuit that selects binary information from one of many input lines and directs it to a single output line. The set of selection of a particular line is controlled by selection lines. Normally there are 2n input lines and n selection lines whose bit combinations determine which input is selected.

The 4:1 MUX has four inputs I0, I1, I2 and I3 and select lines S0 and S1. The select lines s0 and s1 are decoded to select a particular AND gate. The outputs of the AND gates are applied to a single OR gate that provides the one line output Y.

DEMULTIPLEXER

A Demultiplexer is a Combinational circuit that selects binary information from one of input line and directs it to many output line. The set of selection of a particular output is controlled by selection lines. Normally there are 1 input line and 2n selection lines whose bit combinations determine the output.

The 1:4 DEMUX has one input and select lines S0 and S1. The select lines s0 and s1 are decoded to select a particular AND gate. The outputs of the AND gates provides the various line output Y1, Y2, Y3 and Y4.

PROGRAM:

Verilog code for 4 to 1 Multiplexer

module mux(en, a, y,sel);

input en;input [3:0] a;input[1:0] sel;output y;

reg y;

always@(en or a)

beginif(!en)y=1'b0;else case(sel)

2'b00 : y = a[3];2'b01 : y = a[2];2'b10 : y = a[1];2'b11 : y = a[0];

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endcase

end

endmodule


NET "a[0]" LOC = "p79" ;NET "a[1]" LOC = "p78" ;NET "a[2]" LOC = "p82" ;NET "a[3]" LOC = "p80" ;NET "en" LOC = "p74" ;NET "sel[0]" LOC = "p77" ;NET "sel[1]" LOC = "p76" ;NET "y" LOC = "p84" ;

Verilog code for 1 to 4 Demultiplexer

module demux(a, en, y, sel);

input a;input en;output [3:0] y;input [1:0] sel;

reg [3:0]y;

always@(a or en)

beginif(!en)y = 4'b0000;elsecase(sel)

2'b00 : beginy[3]=a;y[2:0]=3'b0;end

2'b01 : begin

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y[2]=a;y[3]=1'b0;y[1:0]=2'b0;end

2'b10 : beginy[1]=a;y[3:2]=2'b0;y[0]=1'b0;end

2'b11 : beginy[0]=a;y[3:1]=3'b0;end

endcase

end

endmodule


NET "a" LOC = "p79" ;NET "en" LOC = "p74" ;NET "sel[0]" LOC = "p77" ;NET "sel[1]" LOC = "p76" ;NET "y[0]" LOC = "p87" ;NET "y[1]" LOC = "p86" ;NET "y[2]" LOC = "p85" ;NET "y[3]" LOC = "p84" ;

PROCEDURE: (SAME FOR BOTH MUX & DEMUX)

Software part



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Hardware part



cable.

SYNTHESIS REPORT: (FOR MUX)Device Utilization Summary (estimated values)



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SYNTHESIS REPORT: (FOR DEMUX)Device Utilization Summary (estimated values)



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SIMULATION REPORT: (FOR MUX)

SIMULATION REPORT: (FOR DEMUX)

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RESULT:

Thus the 4:1 mux and 1:4 demux were designed using Verilog HDL and it was simulated, synthesized, implemented and programmed in the FPGA device.

EX. 4 IMPLEMENTATION OF ENCODER AND DECODER IN FPGA

AIM: To design, synthesize, simulate, implement and program the encoder and decoder in FPGA.

TOOLS REQUIRED:



ALGORITHM:1. Start the program.2. Declare the input and output variables.3. Declare the output as register data type.

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4. Use PROCEDURAL construct statements (behavioral modeling) for Verilog code.5. Terminate the program.

THEORY:

ENCODER

An Encoder is a digital circuit that has 2n (or fewer) input lines and n output lines. The output lines generate the binary the binary code corresponding to the input value. In encoder it is assumed that only one input has a value of 1 at any given time.

DECODER

Discrete quantities of information are represented in digital systems by binary codes. A binary code of n bits is capable of representing up to 2n distinct elements of coded information. A decoder is a combinational circuit that converts binary information from n input lines to a maximum of 2n unique output lines. If the n bit coded information unused combinations. The decoder may have fewer than 2n outputs.

The decoder are also called ‘n’ to ‘m’ line decoders, where is less than or equal to 2n. Their purpose is to generate the 2n (or fewer) minterms of input variables. The name decoder is also used in conjunction with other code converters such as BCD to SEVEN SEGMENT decoder.

PROGRAM:

Verilog code for Encoder

module encoder(a, en, y);

input [3:0] a;input en;output [1:0] y;

reg[1:0] y;

always@(en or a)

beginif (!en)y = 2'b0;elsecase (a)

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4'b0001 : y = 2'b00;4'b0010 : y = 2'b01;4'b0100 : y = 2'b10;4'b1000 : y = 2'b11;

endcase

end

endmodule


NET "a[3]" LOC = "p76" ;NET "a[2]" LOC = "p77" ;NET "a[1]" LOC = "p79" ;NET "a[0]" LOC = "p78" ;NET "en" LOC = "p74" ;NET "y[0]" LOC = "p85" ;NET "y[1]" LOC = "p84" ;

Verilog code for Decoder

module decoder(a, en, y);

input[1:0] a;input en;output[3:0] y;

reg[3:0] y;

always@(en or a)

beginif(!en)y= 4'b0000;elsecase(a)

2'b00 : y = 4'b0001;2'b01 : y = 4'b0010;

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2'b10 : y = 4'b0100;2'b11 : y = 4'b1000;default :y = 4'b0000;

endcase

end

endmodule


NET "a[0]" LOC = "p77" ;NET "a[1]" LOC = "p76" ;NET "en" LOC = "p74" ;NET "y[0]" LOC = "p87" ;NET "y[1]" LOC = "p86" ;NET "y[2]" LOC = "p85" ;NET "y[3]" LOC = "p84" ;

SYNTHESIS REPORT :( FOR ENCODER)Device Utilization Summary (estimated values)

Logic Utilization Used Available UtilizationNumber of Slices 2 3584 0%Number of Slice Flip Flops 2 7168 0%Number of 4 input LUTs 3 7168 0%Number of bonded IOBs 7 97 7%


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SYNTHESIS REPORT :( FOR DECODER)




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SIMULATION REPORT: (FOR ENCODER)

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SIMULATION REPORT: (FOR DECODER)

PROCEDURE: (FOR ENCODER & DECODER)

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Software part



Hardware part



cable.

RESULT:

Thus the encoder and decoder were designed using Verilog HDL and it was simulated, synthesized, implemented and programmed in the FPGA device.

EX. 5 IMPLEMENTATION OF 4 – BIT COUNTER IN FPGA

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AIM:

To design, synthesize, simulate, implement and program the 4 – bit counter in FPGA.

TOOLS REQUIRED:



ALGORITHM:


THEORY:

4 - BIT COUNTER

This is a device for counter operation. It consists of a single user Flip Flop and a 3 bit Asynchronous Counter. This arrangement is for flexibility. Synchronous ones can also be used. It can be used as Module 8 Counter using only the 3 bit counter operation portion. It also provides gate reset inputs. This done can be configured as a decode counter by asynchronous recycling by using the gate reset inputs for the partial decoding.

PROGRAM:

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Verilog code for 4-bit counter

module counter(clk, reset, count);input clk;input reset;output [3:0] count;reg[3:0] count;integer timer_count1 = 0,timer_count2 = 0;reg clk_msec,clk_sec;

always@(posedge clk)begin

if(timer_count1==3999)begin

timer_count1=0;clk_msec=1'b1;

endelsebegin

timer_count1=timer_count1+1;clk_msec=1'b0;

endendalways@(posedge clk_msec)begin


timer_count2=0;clk_sec=1'b1;

endelsebegin

timer_count2=timer_count2+1;clk_sec=1'b0;

endendalways@(posedge clk_sec)begin

if(~reset)count = 4'b0000;

elsecount = count+1;

endendmoduleUCF file (User constraint file)

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NET "clk" LOC = "p52";NET "count[0]" LOC = "p87" ;NET "count[1]" LOC = "p86" ;NET "count[2]" LOC = "p85" ;NET "count[3]" LOC = "p84" ;NET "reset" LOC = "p74";

PROCEDURE

Software part


clicking on the synthesis in the process window.4. Perform the functional simulation using ModelSim XE simulator.5. Open a new UCF file and lock the pins of the design with FPGA I/O pins.6. Implement the design by double clicking on the implementation tool selection.7. Create programming file (i.e., bit file) for downloading into the specified device.

Hardware part



cable.

SYNTHESIS REPORT:


Logic Utilization Used Available UtilizationNumber of Slices 47 3584 1%Number of Slice Flip Flops 70 7168 0%Number of 4 input LUTs 87 7168 1%Number of bonded IOBs 6 97 6%Number of GCLKs 2 8 25%


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Verilog code for 4 – bit counter (Simulation only)

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module count(clk,reset,count); input clk, reset; output [3:0] count; reg[3:0] count; always@ (posedge clk) begin if(~reset) count=4'b0000; else count=count+1; end endmodule

SIMULATION REPORT: (Using ModelSim)

RESULT:

Thus the 4 – bit counter were designed using Verilog HDL and it was simulated, synthesized, implemented and programmed in the FPGA device.

EX.6 DESIGN AND IMPLEMENTATION OF SERIAL AND PARALLEL

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ADDER IN FPGA

AIM: To design, synthesize, simulate pipelined serial and parallel adder to add 8 numbers of 12bit size each in 2’s complement and to implement and program the same in FPGA.

TOOLS REQUIRED:


HARDWARE:XILINX - Spartan kit XC3S400TQ144, Power supply Adapter, Parallel port cable, FRC connector, AU card - I

THEORY:

SERIAL ADDER:

Serial Adder uses a simple adder and constructs the sum sequentially. At a time t, the Sun is calculated and the carry is stored in a register. At time t+1, the sum uses carry[t] to calculate a new sum.

Carry [ t + 1] = A [ t +1].B[ t + 1 ] . ( A [ t + 1 ] + B [ t + 1 ] )Sum [ t + 1 ] = Carry [ t + 1 ] . ( A [ t + 1 ] + B [ t + 1 ] + c [ t ] )

+ A [ t + 1 ] . B [ t + 1 ] . c [ t ] The two inputs to the adder are stored in a n-bit register. Sum bit is stored in a

n-bit register. Addition is commenced by clearing the carry register. Then the operands are serially applied to the inputs of the adder. The sum and carry array are advantageous because these delays determine the fastest clock frequency at which the adder can operate.

Bit serial architecture has been used widely for a variety of signal processing applications, especially with technologies in the 2-5 micro range. Reasons for using bit serial architecture include reduced signal routing, reduced module sizes and higher speed operation.

PARALLEL ADDER:

An n-bit parallel adder may be constructed by cascading ‘n’ 1-bit adders. This is called Ripple Carry Adder. The inputs are n bit A and B values. The carry signal of stage ‘i’ is fed to the C signal of the stage i+1 and the sum signal forms the n bit output. The nth bit of the sum indicates whether overflow has occurred. Because the carry output signal is used in the generation of the sum, the sum will be delayed with respect to the carry. In case of n-bit parallel adder, the carry delay has to be minimized because the delay associated the adder is

Tn = nTc

Where Tn is the Total Add Time, n is the number of stages and Tc is the delay of one carry stage. To optimize the Carry delay, the inverter at the output of the carry gate can be omitted. In this case, every other stage operates on complement data.

PROGRAM:

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Verilog code for serial adder

module serial_adder(clk,addr,load,clear,data_in,calc,result);input clk,clear,calc,load;input [2:0]addr;input [11:0]data_in;output reg [11:0]result;reg [11:0]ram[7:0];reg [11:0]temp;always@(negedge clk)

beginif(clk)

temp = ram[0] + ram[1]; temp = (temp + ram[2]);

temp = (temp + ram[3]); temp = (temp + ram[4]); temp = (temp + ram[5]); temp = (temp + ram[6]); temp = (temp + ram[7]);

endalways@(posedge clk)

beginif(~clear)begin

ram[0]=12'b0;ram[1]=12'b0;ram[2]=12'b0;ram[3]=12'b0;ram[4]=12'b0;ram[5]=12'b0;ram[6]=12'b0;ram[7]=12'b0;

endelse if(~load)begin

result=data_in;ram[addr] = data_in;

endelse if(~calc)

result = temp;else

result = ram[addr];end

endmoduleVerilog code for parallel adder

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module parallel_adder(clk,addr,load,clear,data_in,calc,result);

input clk,clear,calc,load;input [2:0]addr;input [11:0]data_in;output reg [11:0]result;reg [11:0]ram[7:0];wire [11:0]temp;

always@(posedge clk)beginif(~clear)begin

ram[0]=12'b0;ram[1]=12'b0;ram[2]=12'b0;ram[3]=12'b0;ram[4]=12'b0;ram[5]=12'b0;ram[6]=12'b0;ram[7]=12'b0;

end

else if(~load)ram[addr]=data_in;

end

assign temp=ram[0]+ram[1]+ram[2]+ram[3]+ram[4]+ram[5]+ram[6]+ram[7];

always@(posedge clk)

beginif(~load)

result=data_in;else if(~calc)result=temp;

elseresult=ram[addr];

end

endmodule


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NET "addr<0>" LOC = "p80" ;NET "addr<1>" LOC = "p82" ;NET "addr<2>" LOC = "p78" ;NET "calc" LOC = "p130" ;NET "clear" LOC = "p137" ;NET "clk" LOC = "p52" ;NET "data_in<0>" LOC = "p92" ;NET "data_in<10>" LOC = "p89" ;NET "data_in<11>" LOC = "p90" ;NET "data_in<1>" LOC = "p96" ;NET "data_in<2>" LOC = "p74" ;NET "data_in<3>" LOC = "p76" ;NET "data_in<4>" LOC = "p77" ;NET "data_in<5>" LOC = "p79" ;NET "data_in<6>" LOC = "p84" ;NET "data_in<7>" LOC = "p85" ;NET "data_in<8>" LOC = "p86" ;NET "data_in<9>" LOC = "p87" ;NET "load" LOC = "p83" ;NET "result<7>" LOC = "p28" ;NET "result<10>" LOC = "p63" ;NET "result<11>" LOC = "p69" ;NET "result<6>" LOC = "p31" ;NET "result<5>" LOC = "p33" ;NET "result<4>" LOC = "p44" ;NET "result<3>" LOC = "p46" ;NET "result<2>" LOC = "p47" ;NET "result<1>" LOC = "p50" ;NET "result<0>" LOC = "p51" ;NET "result<8>" LOC = "p57" ;NET "result<9>" LOC = "p59" ;

PROCEDURE:

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Software part

1. Click on the Xilinx ISE9.1i or Xilinx Project navigator icon on the desktop of PC.

2. Write the Verilog code, check syntax, view RTL schematic and note the device

utilization summary by double clicking on the synthesis in the process window.

3. Perform the functional simulation using ModelSim XE Verilog simulator.

4. Open a new UCF file and lock the pins of the design with FPGA I/O pins.

5. Implement the design by double clicking on the implementation tool selection.

6. Create programming file (i.e., bit file) for downloading into the device.

Hardware part

Connect the power supply cable to the FPGA kit using power supply adapter.

Connect the FPGA kit to the parallel port of the PC through the cable provided

along with the kit.

Connect FRC1 of main board to CN8 of AU card - I using FRC cable.






Working

1. Download the program into the FPGA and connect the FRC connectors as specified.

2. On AU card – I, load the 12 bit data by using the specified switches (SW0-SW11) and

selection of 8 numbers are made one by one by selecting the assigned lines A0, A1 and

A2.

3. After selecting each 12 bit numbers by pressing the LOAD switch, the values are

assigned to concerned memory locations.

4. After loading all values, keep pressing CALC switch in AU card – I for verifying the

result in LED’s on card – I.

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SYNTHESIS REPORT: (FOR SERIAL ADDER)Device Utilization Summary (estimated values)




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SYNTHESIS REPORT: (FOR PARALLEL ADDER)Device Utilization Summary (estimated values)




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OBSERVATION:

Location 12-bit Input Data Location 12-bit Input Data000 0000 0000 0000 100 0000 0000 0100001 0000 0000 0001 101 0000 0000 0101010 0000 0000 0010 110 0000 0000 0110011 0000 0000 0011 111 0000 0000 0111

Result = 0000 0001 1100

RESULT:

Thus the serial adder and parallel adder were designed using Verilog HDL for 8 datas, each of 12 – bit size and it was simulated, synthesized, implemented and programmed in the FPGA device.

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EX.7 DESIGN AND IMPLEMENTATION OF MULTIPLIER IN FPGA

AIM: To design, synthesize, simulate pipelined multiplier to multiply two 8 bit signed numbers in 2’s complement and to implement and program the same in FPGA.

TOOLS REQUIRED:



THEORY:

MULTIPLIER:

In many digital signal processing applications such as correlations, convolutions, filtering and frequency analysis, one needs to perform multiplication. Multiplication algorithms will be used to illustrate methods of designing different cells so they fit into a larger structure. In order to introduce these designs, simple serial and parallel multipliers will be introduced. The appropriate tests should be consulted for more definite system architecture. The most basic form of multiplication consists of forming the products of two positive binary numbers. This may be accomplished through the traditional technique of Successive Addition and shifts in which each additive is conditional on one of the multiplier bits. The multiplication process may be viewed to consist of the following steps:

1. Evaluation of Partial Products,2. Accumulation of the shifted partial products

It should be noted that binary multiplication is equal to partial AND operations. Thus evaluation of partial products consists of the logical AND of the Multiplicand and the relevant Multiplier bit. Each column of partial products must then be added and if necessary any carry values is passed to the next column. There are a number of techniques that may be used to perform multiplication. In general the choice is based on the factors such as speed, throughput, numerical accuracy and area. As a rule, multiplication may be classified by the format, in which the words are accessed namely,

1. Serial Form2. Serial / Parallel Form3. Parallel Form

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PROGRAM:

Verilog code for multiplier

module multiplier(clk,addr,load,clear,data_in,calc,result);

input clk,clear,calc,load;input addr;input [7:0]data_in;output reg [15:0]result;reg [7:0]ram[1:0];

always@(posedge clk)beginif(~clear)begin

ram[0]=8'b0;ram[1]=8'b0;

endelse if(~load)

ram[addr]=data_in;end

always@(posedge clk)beginif(~load)

result={8'b0,data_in};else if(~calc)

result= multiply_8x8_2sC (ram[0],ram[1]);else

result={8'b0,ram[addr]};end

function[15:0] multiply_8x8_2sC;input[7:0] a,b;reg[7:0] a_mag,b_mag;reg[14:0] y_mag;reg[14:0] y_neg;begincase (a[7])

0: a_mag = a[6:0];1: a_mag = 128 - a[6:0]; // max(a_mag) = 128, thus 8 bits

endcasecase (b[7])

0: b_mag = b[6:0];

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1: b_mag = 128 - b[6:0];endcasey_mag = a_mag * b_mag; // max(y_mag) = 16384, thus 15 bitsif ((a[7] ^ b[7]) & (y_mag != 0)) // if (a * b) is -ve AND non-zerobegin

// y_mag >=1, <= 16256, thus need only 14 bitsy_neg = 32768 - y_mag[13:0]; // max(y_neg) = 32767, thus need 15 bitsmultiply_8x8_2sC = {1'b1,y_neg};

endelse

multiply_8x8_2sC = y_mag;end

endfunctionendmodule

UCF file(User constraint file)NET "addr" LOC = "p80" ;NET "calc" LOC = "p130" ;NET "clear" LOC = "p137" ;NET "clk" LOC = "p52" ;NET "data_in<0>" LOC = "p92" ;NET "data_in<1>" LOC = "p96" ;NET "data_in<2>" LOC = "p74" ;NET "data_in<3>" LOC = "p76" ;NET "data_in<4>" LOC = "p77" ;NET "data_in<5>" LOC = "p79" ;NET "data_in<6>" LOC = "p84" ;NET "data_in<7>" LOC = "p85" ;NET "load" LOC = "p83" ;NET "result<0>" LOC = "p51" ;NET "result<10>" LOC = "p63" ;NET "result<11>" LOC = "p69" ;NET "result<12>" LOC = "p68" ;NET "result<13>" LOC = "p73" ;NET "result<14>" LOC = "p70" ;NET "result<15>" LOC = "p20" ;NET "result<1>" LOC = "p50" ;NET "result<2>" LOC = "p47" ;NET "result<3>" LOC = "p46" ;NET "result<4>" LOC = "p44" ;NET "result<5>" LOC = "p33" ;NET "result<6>" LOC = "p31" ;NET "result<7>" LOC = "p28" ;NET "result<8>" LOC = "p57" ;NET "result<9>" LOC = "p59" ;

43

PROCEDURE:

Software part




3. Perform the functional simulation using ModelSim - XE Verilog simulator.




Hardware part



along with the kit.







Working

1. Download the program into the FPGA and connect the FRC connectors as

specified.

2. On AU card – I, load two 8 - bit data by using the specified switches (SW0-SW7) in

address location 0 and 1.

3. By pressing the LOAD switch in AU card - I, the two values are assigned to

concerned memory locations.

4. After loading all values, keep pressing CALC switch in AU card – I for verifying

the result in LED’s on card – I.

44

SYNTHESIS REPORT:


Logic Utilization Used Available UtilizationNumber of Slices 50 3584 1%Number of Slice Flip Flops 32 7168 0%Number of 4 input LUTs 95 7168 1%Number of bonded IOBs 29 97 29%Number of 18X18s 1 16 6%Number of GCLKs 1 8 12%



45

OBSERVATION:

Location 8-bit Input Data 16-bit Result

0 0000 00011111 1111 1000 0001

1 1000 0001

46

RESULT:

Thus the 8 – bit multiplier was designed using Verilog HDL and it was simulated, synthesized, implemented and programmed in the FPGA device.

EX.8 DESIGN AND IMPLEMENTATION OF REAL TIME CLOCK IN FPGA

AIM:

To design a Real Time Clock (2 digits, 7 segment LED displays each for Hours, Minutes and Seconds) and demonstrate its working on the FPGA Board.

TOOLS REQUIRED:



PROGRAM:

Verilog Code for Real Time Clock

module real_time_clk_verilog (clk,clear,hour1,hour2,minute1,minute2,second1,second2, hour_A2, min_A1, sec_A0, load, data_in);

input clk,clear;output reg [6:0]hour1,hour2,minute1,minute2,second1,second2;input load;input hour_A2,min_A1,sec_A0;input [7:0]data_in;reg clk_sec,clk_msec;reg [7:0]sec,min,hr;integer timer_count1=0,timer_count2=0;

always@(posedge clk)

47

beginif(timer_count1==3999)begin

timer_count1=0;clk_msec=1'b1;

endelsebegin

timer_count1=timer_count1+1;clk_msec=1'b0;

endend

always@(posedge clk_msec)begin


timer_count2=0;clk_sec=1'b1;

endelsebegin

timer_count2=timer_count2+1;clk_sec=1'b0;

endend

always@(negedge clk_sec)begin

if(~clear)begin

sec=0;min=0;hr=0;

endelse

if(~load)begin

if(hour_A2)begin

if(hr[7:4] == 4'b0010)begin

if(hr[3:0] < 4'b0100)hr = data_in;

end

48

else if(hr[7:4] < 4'b0010)hr = data_in;elsehr = 8'b0;

end

if(min_A1)begin

if(min[7:4] < 4'b0110)min = data_in;elsemin = 8'b0;

end

if(sec_A0)begin

if (sec[7:4] < 4'b0110)sec = data_in;elsesec = 8'b0;

endend

else

beginif(sec[3:0]==4'b1001)begin

sec[3:0]=4'b0;if(sec[7:4]==4'b0101)begin

sec[7:4]=4'b0;if(min[3:0]==4'b1001)begin

min[3:0]=4'b0;if(min[7:4]==4'b0101)begin

min[7:4]=4'b0;if(hr==8'b00100011)hr=0;else if(hr[3:0]==4'b1001)begin

hr[3:0]=4'b0;hr[7:4]=hr[7:4]+1;

endelse

49

hr[3:0]=hr[3:0]+1; //hours count completedendelse

min[7:4]=min[7:4]+1;endelse

min[3:0]=min[3:0]+1; // minutes count completed

endelse

sec[7:4]=sec[7:4]+1;endelse

sec[3:0]=sec[3:0]+1; //seconds count completedend

end

always@(sec)begin

case (sec[3:0])4'b0000: second1=7'b1111110;4'b0001: second1=7'b0110000;4'b0010: second1=7'b1101101;4'b0011: second1=7'b1111001;4'b0100: second1=7'b0110011;4'b0101: second1=7'b1011011;4'b0110: second1=7'b1011111;4'b0111: second1=7'b1110000;4'b1000: second1=7'b1111111;4'b1001: second1=7'b1111011;default: second1=7'b0;endcase

end

always@(sec)begin

case(sec[7:4])4'b0000: second2=7'b1111110;4'b0001: second2=7'b0110000;4'b0010: second2=7'b1101101;4'b0011: second2=7'b1111001;4'b0100: second2=7'b0110011;4'b0101: second2=7'b1011011;4'b0110: second2=7'b1011111;4'b0111: second2=7'b1110000;4'b1000: second2=7'b1111111;

50

4'b1001: second2=7'b1111011;default: second2=7'b0;endcase

end

always@(min)begin

case(min[3:0])4'b0000: minute1=7'b1111110;4'b0001: minute1=7'b0110000;4'b0010: minute1=7'b1101101;4'b0011: minute1=7'b1111001;4'b0100: minute1=7'b0110011;4'b0101: minute1=7'b1011011;4'b0110: minute1=7'b1011111;4'b0111: minute1=7'b1110000;4'b1000: minute1=7'b1111111;4'b1001: minute1=7'b1111011;default: minute1=7'b0;endcase

end

always@(min)begin

case(min[7:4])4'b0000: minute2=7'b1111110;4'b0001: minute2=7'b0110000;4'b0010: minute2=7'b1101101;4'b0011: minute2=7'b1111001;4'b0100: minute2=7'b0110011;4'b0101: minute2=7'b1011011;4'b0110: minute2=7'b1011111;4'b0111: minute2=7'b1110000;4'b1000: minute2=7'b1111111;4'b1001: minute2=7'b1111011;default: minute2=7'b0;endcase

end

always@(hr)begin

case(hr[3:0])4'b0000: hour1=7'b1111110;4'b0001: hour1=7'b0110000;4'b0010: hour1=7'b1101101;4'b0011: hour1=7'b1111001;

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4'b0100: hour1=7'b0110011;4'b0101: hour1=7'b1011011;4'b0110: hour1=7'b1011111;4'b0111: hour1=7'b1110000;4'b1000: hour1=7'b1111111;4'b1001: hour1=7'b1111011;default: hour1=7'b1111110;endcase

end

always@(hr)begin

case(hr[7:4])4'b0000: hour2=7'b1111110;4'b0001: hour2=7'b0110000;4'b0010: hour2=7'b1101101;default: hour2=7'b1111110;endcase

end

end module

UCF File(User Constraint File)

NET "clear" LOC = "p137" ;NET "clk" LOC = "p52" ;NET "data_in<0>" LOC = "p92" ;NET "data_in<1>" LOC = "p96" ;NET "data_in<2>" LOC = "p74" ;NET "data_in<3>" LOC = "p76" ;NET "data_in<4>" LOC = "p77" ;NET "data_in<5>" LOC = "p79" ;NET "data_in<6>" LOC = "p84" ;NET "data_in<7>" LOC = "p85" ;NET "hour1<0>" LOC = "p95" ;NET "hour1<1>" LOC = "p97" ;NET "hour1<2>" LOC = "p98" ;NET "hour1<3>" LOC = "p99" ;NET "hour1<4>" LOC = "p104" ;NET "hour1<5>" LOC = "p125" ;NET "hour1<6>" LOC = "p122" ;NET "hour2<0>" LOC = "p112" ;

NET "minute1<1>" LOC = "p15" ;NET "minute1<2>" LOC = "p17" ;NET "minute1<3>" LOC = "p18" ;NET "minute1<4>" LOC = "p21" ;NET "minute1<5>" LOC = "p23" ;NET "minute1<6>" LOC = "p24" ;NET "minute2<0>" LOC = "p129" ;NET "minute2<1>" LOC = "p132" ;NET "minute2<2>" LOC = "p135" ;NET "minute2<3>" LOC = "p140" ;NET "minute2<4>" LOC = "p1" ;NET "minute2<5>" LOC = "p12" ;NET "minute2<6>" LOC = "p13" ;NET "sec_A0" LOC = "p80" ;NET "second1<0>" LOC = "p32" ;NET "second1<1>" LOC = "p35" ;NET "second1<2>" LOC = "p36" ;NET "second1<3>" LOC = "p40" ;

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NET "hour2<1>" LOC = "p116" ;NET "hour2<2>" LOC = "p119" ;NET "hour2<3>" LOC = "p118" ;NET "hour2<4>" LOC = "p123" ;NET "hour2<5>" LOC = "p131" ;NET "hour2<6>" LOC = "p93" ;NET "hour_A2" LOC = "p78" ;NET "load" LOC = "p83" ;NET "min_A1" LOC = "p82" ;NET "minute1<0>" LOC = "p14" ;

NET "second1<4>" LOC = "p41" ;NET "second1<5>" LOC = "p56" ;NET "second1<6>" LOC = "p60" ;NET "second2<0>" LOC = "p26" ;NET "second2<1>" LOC = "p27" ;NET "second2<2>" LOC = "p6" ;NET "second2<3>" LOC = "p7" ;NET "second2<4>" LOC = "p8" ;NET "second2<5>" LOC = "p11" ;NET "second2<6>" LOC = "p10" ;

PROCEDURE:

Software part







Hardtware part



along with the kit.







Working:

53

Connections are made as above and implement the design into the FPGA device and

the REAL TIME clock is ON, all 7 segments displays will be in ON position and starts

counting, the time can be set by the switches SW0 – SW7 using A2, A1, A0 switches in

card - I and the RESET pin RESETS the clock.

SYNTHESIS REPORT:




54

RESULT:

Thus the real time clock was designed using verilog code and its working was demonstrated in FPGA board.

EX.9 IMPLEMENTATION OF TRAFFIC LIGHT CONTROLLER IN FPGA

AIM:

To design a Traffic Light Controller using Verilog code and to test its working on the FPGA Board.

TOOLS REQUIRED:


HARDWARE:

55

XILINX - Spartan kit XC3S400TQ144, Power supply Adapter, Parallel port cable, FRC connector, AU card - II

PROGRAM:

Verilog Code for Traffic Light Controller

module traffic_verilog(seg_1,seg_2,R1,R2,R3,G1,G2,G3,Y1,Y2,Y3,PR,PG,clk,rst);output reg R1,R2,R3,G1,G2,G3,Y1,Y2,Y3,PR,PG;output reg [6:0]seg_1,seg_2;input clk,rst;integer timer_count1 = 0,timer_count2 = 0;reg clk_msec,clk_sec;reg [7:0]count;reg [1:0]state = 2'b0;

always@(posedge clk)begin

if(timer_count1==3999) begin timer_count1=0; clk_msec=1'b1; end else begin timer_count1=timer_count1+1; clk_msec=1'b0; end

end

always@(posedge clk_msec)begin

if(timer_count2==999) begin timer_count2=0; clk_sec=1'b1; end else begin timer_count2=timer_count2+1; clk_sec=1'b0; end

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end always@(posedge clk_sec)beginif(~rst)begin R1 = 1'b1; G1 = 1'b0; Y1 = 1'b0;

R2 = 1'b1; G2 = 1'b0; Y2 = 1'b0;R3 = 1'b1; G3 = 1'b0; Y3 = 1'b0;

state=2'b00;endelse begin case(state) 2'b00://SIGNAL AT SIGNAL LIGHTS ONE begin

if(count==8'b00100101) begin

G1 = 1'b0; R1 = 1'b0;

Y1 = 1'b1; R3 = 1'b0; Y3 = 1'b0; G3 = 1'b0;

end if(count==8'b00101001) begin G1 = 1'b1;

Y1 = 1'b0; R3 = 1'b1;

state=2'b01; end else state=2'b00; end 2'b01://SIGNAL AT SIGNAL LIGHTS TWO begin if(count==8'b00100101) begin Y1 = 1'b1;

G1 = 1'b0;R3 = 1'b1;R2 = 1'b0; Y2 = 1'b1;

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G2 = 1'b0; end if(count==8'b00101001) begin R1 = 1'b1;

Y1 = 1'b0;Y2 = 1'b0; G2 = 1'b1;state = 2'b10;

end else state=2'b01; end 2'b10://SIGNAL AT SIGNAL LIGHTS THREE begin if(count==8'b00100101) begin Y2 = 1'b1;

G2 = 1'b0;R3 = 1'b0; Y3 = 1'b1; G3 = 1'b0;

end if(count==8'b00101001) begin R2 = 1'b1;

Y2 = 1'b0;Y3 = 1'b0; G3 = 1'b1;

state = 2'b11; end else state=2'b10; end 2'b11://ALL SIGNAL HIGH TO ALLOW PEDESTRIALS TO CROSS begin

if(count==8'b00100101) begin

Y1= 1'b0; Y3 = 1'b1;

G3 = 1'b0; end if(count==8'b00101001) begin

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Y1 =1'b0; R3 = 1'b1;

Y3 = 1'b0;state = 2'b00;

end else state=2'b11; end endcase endend

always@(count,state)begin if((state==2'b00)&&(count<=8'b00101001)) begin PR = 1'b1;

PG = 1'b0; end else begin PR = 1'b0;

PG = 1'b1; endend

always@(posedge clk_sec)begin

if(rst==1'b0) count=8'b00000000; else if(clk_sec) begin if(count[3:0]==4'b1001) begin count[3:0]=4'b0000;

if(count[7:4]==4'b0010) count[7:4]=4'b0000; else

count[7:4]=count[7:4]+1; end

else count[3:0]=count[3:0]+1; endend

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always@(count)begin

case(count[3:0]) 4'b0000:seg_1 = 8'b1111110; //0

4'b0001:seg_1 = 8'b0110000; //14'b0010:seg_1 = 8'b1101101; //24'b0011:seg_1 = 8'b1111001; //34'b0100:seg_1 = 8'b0110011; //44'b0101:seg_1 = 8'b1011011; //54'b0110:seg_1 = 8'b1011111; //64'b0111:seg_1 = 8'b1110000; //74'b1000:seg_1 = 8'b1111111; //84'b1001:seg_1 = 8'b1111011; //9default:seg_1 = 8'b0000000; //off

endcase

case(count[7:4]) 4'b0000:seg_2 = 8'b1111110; //0

4'b0001:seg_2 = 8'b0110000; //14'b0010:seg_2 = 8'b1101101; //24'b0011:seg_2 = 8'b1111001; //34'b0100:seg_2 = 8'b0110011; //44'b0101:seg_2 = 8'b1011011; //54'b0110:seg_2 = 8'b1011111; //64'b0111:seg_2 = 8'b1110000; //74'b1000:seg_2 = 8'b1111111; //84'b1001:seg_2 = 8'b1111011; //9default:seg_2 = 8'b0000000; //off

endcaseendendmoduleUCF file (User Constraint File)

NET "clk" LOC = "p52" ;NET "G1" LOC = "p97" ;NET "G2" LOC = "p98" ;NET "G3" LOC = "p125" ;NET "PG" LOC = "p132" ;NET "PR" LOC = "p135" ;NET "R1" LOC = "p93" ;NET "R2" LOC = "p104" ;NET "R3" LOC = "p129" ;NET "rst" LOC = "p78" ;NET "seg_1<6>" LOC = "p27" ;NET "seg_1<5>" LOC = "p26" ;

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NET "seg_1<4>" LOC = "p24" ;NET "seg_1<3>" LOC = "p23" ;NET "seg_1<2>" LOC = "p21" ;NET "seg_1<1>" LOC = "p18" ;NET "seg_1<0>" LOC = "p17" ;NET "seg_2<6>" LOC = "p15" ;NET "seg_2<5>" LOC = "p14" ;NET "seg_2<4>" LOC = "p13" ;NET "seg_2<3>" LOC = "p12" ;NET "seg_2<2>" LOC = "p1" ;NET "seg_2<1>" LOC = "p83" ;NET "seg_2<0>" LOC = "p80" ;NET "Y1" LOC = "p95" ;NET "Y2" LOC = "p99" ;NET "Y3" LOC = "p122" ;

PROCEDURE:

Software part







61

Hardware part



along with the kit.

Connect FRC1 of main board to CN2 of AU card - II using FRC cable.



Working:

1. Connections are made as above and implement the design into the FPGA device and

the Traffic Light Controller (AU card – II) will be ON.

2. Initially, the Pedestrians on all the three signals will be in GREEN for 30 seconds to

allow the Pedestrians to pass through.

3. After 30 seconds, the pedestrian goes to RED and the GREEN in signal1 goes ON for

25 seconds.

4. After 25 seconds, the YELLOW will be ON for 5 seconds and then it goes to RED,

simultaneously the GREEN in signal2 will be ON.

5. Similar procedure is repeated for all the signals. Then the procedure is repeated again

by switching the GREEN in all the Pedestrians.

SYNTHESIS REPORT:




62

RESULT:

Thus the traffic light controller was designed using verilog code and its working was tested in FPGA board.EX. 10 DESIGN AND TESTING ONBOARD SWITCHES AND LED’S IN FPGA

AIM:

To simulate and test onboard switches and LED’s using Verilog code and to implement the same in FPGA.

TOOLS REQUIRED:


HARDWARE:

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XILINX - Spartan kit XC3S400TQ144, Power supply Adapter, Parallel port cable, FRC connector, GPIO card - II

ALGORITHM:


THEORY:

TESTING ON BOARD LED’S AND SWITCHES:

XC3S400 is an array of Configurable Logic Blocks (CLB’s) and is embedded within a set of horizontal and vertical channels that contain Routing that can be personalized to interconnect CLB’s. The configuration of the interconnect is achieved by turning ON ‘n’ channel pass transistors. The state that determines a given interconnect pattern is held in the Static RAM cells distributed across the chip close to the controlled elements. The CLB’s and routing channels are surrounded by a set of programmable Inputs / Outputs.

PROGRAM:

Verilog Code for Testing Onboard Switches and LEDs in FPGA

module buffer(a, y);

input [7:0] a;output [7:0] y;reg [7:0]y;

always@(a)begin

y=a;end

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endmodule

UCF file(User constraint file)

NET "a[0]" LOC = "p83" ;NET "a[1]" LOC = "p80" ;NET "a[2]" LOC = "p82" ;NET "a[3]" LOC = "p78" ;NET "a[4]" LOC = "p79" ;NET "a[5]" LOC = "p77" ;NET "a[6]" LOC = "p76" ;NET "a[7]" LOC = "p74" ;NET "y[0]" LOC = "p96" ;NET "y[1]" LOC = "p92" ;NET "y[2]" LOC = "p90" ;NET "y[3]" LOC = "p89" ;NET "y[4]" LOC = "p87" ;NET "y[5]" LOC = "p86" ;NET "y[6]" LOC = "p85" ;NET "y[7]" LOC = "p84" ;

PROCEDURE:

Software part



Hardware part

65



cable.

SYNTHESIS REPORT:


Logic Utilization Used Available UtilizationNumber of Slices 0 3584 0%Number of bonded IOBs 16 97 16%

RTL Schematic Representation

SIMULATION REPORT:

66

RESULT:

Thus the onboard switches and LEDs were designed using Verilog HDL and it was simulated and tested in the FPGA device.

EX. 11 DESIGN AND IMPLEMENTATION OF HALF SUBTRACTOR AND FULL SUBTRACTOR USING SCHEMATIC ENTRY IN FPGA

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AIM:

To design half subtractor and full subtractor using schematic entry and to synthesize, simulate, implement the same in FPGA.

TOOLS REQUIRED:



THEORY:

HALF SUBRACTOR:

The Half subtractor consist of two input variables, the output variables produce the Difference (d) and Borrow (bo). The output ‘bo’ is 1 only when the input ‘a’ is at low level and other input ‘b’ is at higher level. The output‘d’ is 1 only when only one of the inputs is 1. The Boolean expression for half subtractor is given by,

d = a ^ bbo = a’b

FULL SUBTRACTOR:

A full subtractor is a multiple output combinational logical network which performs a subtraction between two binary bits considering that a ‘1’ might have been borrowed by a lower significant stage. Along with the minuend ‘a’ and the subtrahend ‘b’, the third input is the borrow bit ‘c’, from the previous stage of subtraction. The combinational logic network of the full subtractor thus has three inputs and two outputs. The two outputs produced are the difference bit output‘d’ and a final borrow ‘bo’ respectively. The Boolean expression for full subtractor is given by,

d = a ^ b ^ c bo = a’b + a’c + bc

HALF SUBTRACTOR DESIGN USING SCHEMATIC ENTRY

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FULL SUBTRACTOR DESIGN USING SCHEMATIC ENTRY

PROCEDURE: (SAME FOR HALF SUBTRACTOR AND FULL SUBTRACTOR)

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Software part


2. Draw the half subtractor and full subtractor circuit by choosing schematic as top level

source module.

3. Check syntax, view RTL schematic and note the device utilization summary by double

clicking on the synthesis in the process window.

4. Perform the functional simulation using Xilinx ISE simulator.



7. Create programming file (i.e., bit file) for downloading into the specified device.

Hardware part

1. Connect the power supply cable to the FPGA kit using power supply adapter.

2. Connect FPGA board to parallel port of PC using parallel port cable.

3. Connect FRC1 of FPGA board with the switches (i/ps) of GPIO card - II using FRC

cable.

4. Connect FRC2 of FPGA board with the LEDs (o/ps) of GPIO card - II using FRC

cable.

SYNTHESIS REPORT: (FOR HALF SUBTRACTOR)

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SYNTHESIS REPORT: (FOR FULL SUBTRACTOR)

71





SIMULATION REPORT: (FOR HALF SUBTRACTOR)

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SIMULATION REPORT: (FOR FULL SUBTRACTOR)

RESULT:

Thus the half subtractor and full subtractor were designed using schematic entry and it was simulated, synthesized, implemented and programmed in the FPGA device.

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53011785 Vlsi Lab Manual

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