Vlsi Modified Lab Manual

8/12/2019 Vlsi Modified Lab Manual

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PROCEDURE TO CODE A DESIGN AND VERIFY THE RESULT USINGXILINX ISE SIMULATOR WITH SPARTAN3 FPGA/COLD Implementt!"n#

Step$%

F!leNew Project

Enter the Project Name

Top level Source type: HDL

Click Next

Step&%

Ne' P(")e*t W!+(, - P(")e*t P("pe(t!e.window open

Select the De!*eand the De.!0n 1l"'!or the Project:

P(",2*t Cte0"( % "ll

Fm!l % Spartan#

De!*e % $C#S%&&

P*40e % 'T%()

Spee, % *+

Snt5e.!. T""l % $ST ,-HDL.-erilo/0

S!m2lt"( % 1SE Simulator ,-HDL.-erilo/0Click Next

Ne' P(")e*t W!+(,2C(ete Ne' S"2(*e3indow open

Click on New Source

SelectVHDL M",2leand enter the !ile name4 ee that "dd to Project i elected4

Click Next

New Source 3i5ard 2 Dei/n module window open

Enter the port name and elect the direction appropriately

Click NextF!n!.5Ne6tNe6tF!n!.57

Step3%

To enter the lo/ic in the pro/ram6 click the moue at the place where the lo/ic need to 7e entered4

8o to E,!tLn020e Templte.Snt5e.!. C"n.t(2*t.C",!n0 E6mple.88

Select the dei/n you are codin/4

"!ter election click E,!tU.e !n F!le

Save the Pro/ram4


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Step9% T" .nt5e.!+e t5e De.!0n

Dou7le click C5e*4 Snt6in Snt5e.!+e - XSTin Procee window

"!ter checkin/ yntax dou7le click Snt5e.!+e - XST

Dou7le clickV!e' Te*5n"l"0 S*5emt!*to view the Schematic dia/ram o! the dei/n4

Step:% T" Implement t5e De.!0n

Dou7le click Implement De.!0nin Procee window4

Step;% T" /!e' t5e '/e 1"(m.7

Cl!*4 P(")e*tNe' S"2(*e

Ne' S"2(*e W!+(, - Sele*t S"2(*eType window open4

Select Te.t


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3ave!orm with delay appear on the window4

StepC% T" ,2mp t5e *",e "nt" t5e Sp(tn3 4!t%

Dou7le click Gene(te P("0(mm!n0 F!lein procee window4

Dou7le click C"n1!02(e De!*e !MPACT!MPACTwindow open4

Select C"n1!02(e ,e!*e 2.!n0 >"2n,(B.*n TAGand click F!n!.57

A..!0n ne' *"n1!02(t!"n 1!lewindow open4 Select 7>!t!ile and click open4

'or the next ..!0n ne' *"n1!02(t!"nwindow click >p..7

;i/ht click the XC3S& FPGAand clickp("0(m7

P("0(mm!n0 p("pe(t!e.window open4 Click O@7

P("0(m .2**ee,e,

"ppear on the creen and the lead on the partan# kit /low indicatin/ the ucce o! the dei/n4

Step$%

-eri!y the reult 7y connectin/ the di/ital trainer kit to the pin elected4


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EXPERIMENTB$

AIM%To implement "ND /ate u

THEORY%The "ND /ate per!orm l

/ate can have any num7er o! inpu

H18H only when all o! the input

TRUTH TA

a "ND !unction4 "nd

te i uch that output i

the output i L


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AIM%To implement


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c : out STD@Lehavioral o! or/ate i

7e/in

c B= a or 7?end >ehavioral?

TIMING WAVEFORM%


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V

AIM%To implement N"ND /ate

THEORY% The term N"ND i

complemented output4 1t i a uni

output occur only when all inputTRUTH TA


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VHDL CODE%

li7rary 1EEE?

ue 1EEE4STD@L


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VHDL CODE FOR NOR GATE

AIM%To implement N


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PROGRAM CODE%

li7rary 1EEE?

ue 1EEE4STD@L


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VHDL CODE FOR XOR GATE

AIM%To implement $


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PROGRAM CODE%

li7rary 1EEE?

ue 1EEE4STD@L


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AIM%To implement $N


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PROGRAM CODE%

Li7rary 1EEE?

ue 1EEE4STD@L


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VHDL CODE FOR NOT GATE

AIM%To implement N


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PROGRAM CODE%

li7rary 1EEE?

ue 1EEE4STD@L


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EXPERIMENTB&

VHDL CODE FOR HALF ADDER

AIM%To dei/n and imulate hal! adder uin/ -HDL4

TRUTH TA


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PROGRAM CODE%

li7rary 1EEE?

ue 1EEE4STD@L


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EXPERIMENTB3

VHDL CODE FOR &69 DECODER

AIM%To dei/n a %x+ decoder and to imulate in -HDL4

THEORY%" decoder i a com7inational circuit with multiple input6 multiple output lo/ic circuit that

convert coded input to coded output6 where the input are leer in num7er than output code4 Theinput code i /enerally ha !ewer 7it than the output code6 there i one*to*one mappin/ !rom input

code word into output code word4 in a one*to*one mappin/6 each input code word produce a

di!!erent output code word4

The /eneral tructure o! a decoder circuit can 7e hown a !ollow4 The ena7le input6 i!

preent mut 7e aerted !or the decoder to per!orm it normal mappin/ !unction4


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7e/in

proce ,x0 i

7e/in

cae x i

when &&=I d B=A&&&?when &A=I d B=&A&&?

when A&=I d B=&&A&?

when other=I d B=&&&A?

end cae?

end proce?

end 7ehavioral?

TECHNOLOGY SCHEMATIC DIAGRAM FOR &69 DECODER%


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SIMULATION FOR &69 DECODER%

RESULT: 2X4 Decoder internal structure is simulated and verified using VHDL.


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EXPERIMENTB9 VHDL CODE FOR DECODER 9X$; USING &X9

AIM%To dei/n a +$A) decoder uin/ %x+ decoder and to imulate in -HDL4

PROGRAM CODE%

li7rary 1EEE?

ue 1EEE4STD@L


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dAB= ,,not p0 and ,not 90 and e0?

d%B= ,,not p0 and ,90 and e0?

d#B= ,p and ,not 90 and e0?

d+B= ,p and 9 and e0?

end >ehavioral?

S!m2lt!"n (e.2lt "1 De*",e( 9X$;


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TECHNOLOGY SCHEMATIC DIAGRAM FOR 9X$; DECODER%

RESULT: 4X16 MULTIPLEXER internal structure is simulated and verified using VHDL.


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EXPERIMENTB: VHDL CODE FOR %$ MULTIPLEXER

AIM%To dei/n a G:A multiplexer and to imulate in -HDL4

PROGRAM CODE%

li7rary 1EEE?

ue 1EEE4STD@L


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SCHEMATIC DIAGRAM OF

TIMING DIAGRAM OF %$ M

RESULT: 8X1 MULTIPLE

%$ MULTIPLEXER%

ULTIPLEXER%

ER internal structure is simulated and verified using VHDL.


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EXPERIMENTB; VHDL CODE FOR $;X$ MULTIPLEXER

AIM%To dei/n a A)xA multiplexer and to imulate in -HDL4

PROGRAM CODE%li7rary 1EEE?

ue 1EEE4STD@L


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when AAAA =I o B=i,A(0?

when other =I o B= i,&0?

end cae?

end i!?

end proce?end >ehavioral?

TECHNOLOGY SCHEMATIC FOR $;X$ MULTIPLEXER%


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SIMULATION FOR $;X$ MULTIPLEXER%

RESULT: 16X1 MULTIPLEXER internal structure is simulated and verified using VHDL.


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EXPERIMENTB? VHDL CODE FOR PRIORITY ENCODER

AIM%To dei/n a priority encoder and to imulate in -HDL4

PROGRAM CODE%

li7rary 1EEE?

ue 1EEE4STD@Lehavioral o! priorityencoder i

7e/in

code B= &&& when el,&0 = A ele

&&A when el,A0 = A ele

&A& when el,%0 = A ele

&AA when el,#0 = A ele

A&& when el,+0 = A ele

A&A when el,(0 = A ele

AA& when el,)0 = A ele

AAA when el,F0 = A ele

***?

end >ehavioral?


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TECHNOLOGY SCHEMATIC DIAGRAM FOR 9X$; DECODER%

SIMULATOIN RESULTS OF PRIORITY ENCODER%

Re.2lt%Hence priority encoder output i veri!ied uin/ -HDL4


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EXPERIMENTB

VHDL CODE FOR DBFLIP FLOP

AIM%To implement ne/ative ed/e D !ilp !lop uin/ xilinx procedure4

THEORY%


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end >ehavioral?

CIRCUIT DIAGRAM%

TIMING WAVEFORM%


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AIM%To implement poitive ed

PROGRAM CODE%

li7rary 1EEE?

ue 1EEE4STD@L

ue 1EEE4STD@Lue 1EEE4STD@L

entity Poitive d!!

Port , a : in ST

7 : in STD

c : out ST

end Poitive d!!?

architecture >eha

7e/in

proce ,a0

7e/in

i! aevent a

c B= 7?

end i!?

end proce

end >ehavioral?

CIRCUIT DIAGRAM%

TIMING WAVEFORM%

e D !lip !lop uin/ -HDL4

81C@AA)+4"LL?

81C@";1TH4"LL?81C@NS18NED4"LL?

i

@L


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EXPERIMENTB

VHDL CODE FOR @ FLIPBFLOP TB FLIPBFLOP

AIM%To dei/n and implement O* !ilp !lop uin/ -HDL4

PROGRAM CODE%

li7rary 1EEE?ue 1EEE4STD@Lehavioral?

TECHNOLOGY SCHEMATIC DIAGRAM FOR B@ FLIP FLOP%


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AIM%To dei/n and implement T* !lip !lop uin/ -HDL4

PROGRAM CODE%

li7rary 1EEE?

ue 1EEE4STD@L


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EXPERIMENTB$

VHDL CODE FOR DECADE COUNTER

AIM%To dei/n a decade counter and to imulate in -HDL4

THEORY% " ,modulo*A&0 decade counter i one that count num7er !rom & to J4thi can 7e

contructed !rom a modulo*A) counter 7y reettin/ the counter at the A&thpule4

1t i hown in 7elow ta7le4we ee that each 7inary num7er i uni9ue and it uni9uene can 7e ued !or

reettin/ the counter at the deired level4 thi i illutrated 7elow conider the M column o! ta7le

reettin/ o! the counter at any deired level i done 7y takin/ output !rom the !lip!lop terminal noted

in the ta7le6 and ue them to drive a uita7le N"ND /ate !or clearin/4 Thu !or the modulo*A& decade

counter we connect output terminal D and > to a N"ND /ate and connect the output o! the N"ND

/ate to the CL; terminal o! all the T*''

TRUTH TA


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architectur

i/nal 9:t

7e/in

proce,cl

7e/ini!,rt=A o

9B=&&&&

ele i!,clk=

i!,9=A&&

9B=&&&&

ele

9B=9A?

end i!?

end i!?

end i!?

end proce

9outB=9?

end >ehav

CIRCUIT DIAGRAM%

e >ehavioral o! decadecounter i

@lo/ic@vector,# downto &0?

6 rt0

r cnt=A&A&0then

?

A and clkevent0then

0then

?

?

ioral?


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SIMULATION RESULTS FOR DECADE COUNTER%

RESULT%Decade counter out put i veri!ied and imulated uin/ -HDL4


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EXPERIMENTB$$

VHDL CODE FOR SERIAL IN SERIAL OUT SHIFT REGISTER

AIM%To dei/n a erial in erial out hi!t re/iter imulate in -HDL4

THEORY% Shi!t re/iter are ued in di/ital ytem !or temporary in!ormation tora/e and !or data

manipulation or tran!er there are two way to hi!t data into re/iter i4e46 erial or parallel6 and imilarly

two way o! hi!t data out o! re/iter4

1n thi type o! hi!t re/iter6 data i tored into the re/iter one 7it at a time,erial0 and taken

out erially 4they delay data 7y one clock time !or each ta/e they will tore a 7it o! data !or each

re/iter4 " erial in erial out hi!t re/iter may 7e A to )+ 7it in len/th6 lon/er i! re/iter or packa/e

are cacaded4

TRUTH TA


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i!,rt=A0then

9B=&&&&?

ele i!,clkevent and clk=A0

then

9,#0B=i?9,%0B=9,#0?

9,A0B=9,%0?

9,&0B=9,A0?

outB=9,&0?

end i!?

end i!?

end proce?

pB=9?

end io?

TECHNOLOGY SCHEMATIC%

SIMULATION RESULTS%


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VHDL CODE FOR SERIAL IN PARALLEL OUT SHIFT REGISTER

AIM%To dei/n a erial in parallel out hi!t re/iter and to imulate in -HDL and veri!y experimentally

in di/ital 1C La74

THEORY% hi!t re/iter are ued in di/ital ytem !or temporary in!ormation tora/e and !or data

manipulation or tran!er there are two way to hi!t data into re/iter i4e46 erial or parallel6 and imilarlytwo way o! hi!t data out o! re/iter4

1n thi type o! hi!t re/iter6 data i tored into the re/iter one 7it at a time,erial0 and taken

out in parallel it make all the internal ta/e availa7le a output4 1! !our 7it are hi!ted in 7y !our

clock pule via a in/le wire 6the data 7ecome availa7le imultaneouly on !our output4

TRUTH TA


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VHDL CODE FOR SERIAL IN SERIAL OUT SHIFT REGISTER

AIM%To dei/n a erial in erial out hi!t re/iter and to imulate in -HDL4

VHDL CODE%

li7rary ieee?

ue ieee4td@lo/ic@AA)+4all?ue ieee4td@lo/ic@arith4all?

entity pio i

/eneric,x : inte/er := G0?

port,

din: in td@lo/ic@vector,x*A downto &0?

clk6ld6r6dir@r6e: in td@lo/ic?

o: out td@lo/ic 0?

end pio?

architecture rtl o! pio i

i/nal pre@9 : td@lo/ic@vector,,x*A0 downto &0 := ,other =I x0?

7e/in

hi!t@re/iter@proce: proce,clk6r0

7e/in

i! ,r = A0 then

pre@9 B= ,other =I &0?

eli! ,clkevent and ,clk = A0 and ,clklat@value = &00 then

i! ,ld = A0 then

pre@9 B= din?

eli! ,e = A0 and ,dir@r = A0 then

pre@9,x*A0 B= &?

pre@9,,x*%0 downto &0 B= pre@9,,x*A0 downto A0?

eli! ,e = A0 and ,dir@r = &0 thenpre@9,,x*A0 downto A0 B= pre@9,,x*%0 downto &0?

pre@9,&0 B= &?

end i!?

end i!?

end proce hi!t@re/iter@proce?

o B= pre@9,&0 when dir@r = A ele

pre@9,x*A0 when dir@r = & ele x?

end rtl?


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TECHNOLOGY SCHEMATI

SIMULATION RESULTS%

%


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VHDL CODE FOR SERIAL/PARALLEL IN SERIAL/PARALLEL OUT SHIFT REGISTER

AIM%To dei/n a erial.parallel in erial.parallel out hi!t re/iter and to imulate in -HDL4

VHDL CODE%

li7rary ieee?

ue ieee4td@lo/ic@AA)+4all?ue ieee4td@lo/ic@arith4all?

entity pipo i

/eneric,x : inte/er := G0?

port, din: in td@lo/ic@vector,,x*A0 downto &0?

dout: out td@lo/ic@vector,,x*A0 downto &0?

clk6ld6r6dir@r6e6i: in td@lo/ic?

o: out td@lo/ic 0?

end pipo?

architecture rtl o! pipo i

i/nal pre@9 : td@ulo/ic@vector,,x*A0 downto &0 := ,other =I x0?

7e/in

hi!t@re/iter@proce: proce,clk6r0

7e/in

i! ,r = A0 then

pre@9 B= ,other =I &0?

eli! ,clkevent and ,clk = A0 and ,clklat@value = &00 then

i! ,ld = A0 then

pre@9 B= din?

eli! ,e = A0 and ,dir@r = A0 then

pre@9,,x*A00 B= i?

pre@9,,x*%0 downto &0 B= pre@9,,x*A0 downto A0?

eli! ,e = A0 and ,dir@r = &0 thenpre@9,,x*A0 downto A0 B= pre@9,,x*%0 downto &0?

pre@9,&0 B= i?

end i!? end i!?

end proce hi!t@re/iter@proce?

dout B= pre@9?

o B= pre@9,&0 when dir@r = A ele

pre@9,,x*A00 when dir@r = & ele x?

end rtl?


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TECHNOLOGY SCHEMATIC%

SIMULATION RESULTS%

;ESLT: -eri!ied the output o! erial.parallel in erial.parallel out hi!t re/iter uin/ -HDL4


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SIMULATION RESULTS%

RTL S*5emt!*


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EXPERIMENTB$3

STATE MACHINE WITH MOORE OUTPUT:

AIM%To implement the tate machine with melay output uin/ -HDL4

PROGRAM CODE%

li7rary ieee?

ue ieee4td@lo/ic@AA)+4all?

entity !m i

port,x6clk : in td@lo/ic? y : out td@lo/ic0?

end !m?

architecture moore@cae o! !m i

type tate@type i,reet6 /otA6 /otA&6 /otA&A0?

i/nal tate:tate@type:=reet?7e/in

proce,clk0

7e/in

i! ,clk=&0 then

cae tate i

when reet =I

i! x=& then

tateB=reet? ele

tateB=/otA?

end i!?

when /otA =I

i! x=& then

tateB=/otA&? ele

tateB=/otA?

end i!?

when /otA& =I

i! x=& then

tateB=reet? ele

tateB=/otA&A?

end i!?

when /otA&A =I

i! x=& then

tateB=/otA&? ele

tateB=/otA?


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end i!?

end cae?

end i!?

i! tate=/otA&A then yB=A?

ele yB=&?end i!?

end proce?

end moore@cae?

SIMULATION RESULTS%

RESULT: 'inite tate machine melay and moore output are veri!ied uin/ -HDL


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EXPERIMENTB$:

RAM $;69B?9$

AIM%To Simulate 1nternal tructure o! A)$+ ;"Q,1C F+AGJ0 uin/ -HDL and

-eri!y it operation4

APPARATUS%

S7NO COMPONENT UANTITY

A4 1C F+AGJ A

%4 Di/ital Trainer >oard A

SOFTWARE USED% $ilinx 1SE Suite A#4% verion


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$;69 RAM DETAILS%

TRUTH TA


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F!0% S!m2lt!"n Re.2lt. "1 RAM $;69

RESULT% $;69 RAM internal tructure i imulated and veri!ied uin/ xilinx So!tware4

Vlsi Modified Lab Manual

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