VLSI Lab Mannual1

7/27/2019 VLSI Lab Mannual1

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SL.NO NAME OF THE EXPERIMENT PAGE NO

1 Simulation and realization of all logic gates. 2-6

2 Write a HDL code to describe the functions of half adder,half subtractor and Full subtractor.

7-9

3 Write HDL codes for the following combinational

circuits.a) 2 to 4 decoderb) 8 to 3 encoderc) 8 to 1 multiplexerd) 4 bit binary to gray convertere) Multiplexerf) De-multiplexerg) 1 bit comparatorh) 4 bit comparator

10-22

4 Write HDL code to describe the functions of a full Adder

Using three modeling styles.

23-27

5 Write a model for 32 bit ALU using the schematicdiagram shown below.

28-29

6 Develop the HDL code for the following flip flop: T, D,SR, JK.

30-35

7 Design 4 bit Binary, BCD Counter (Synchronous resetand Asynchronous reset and any sequence counters.

36-40

8 Simulation and realization of Ring counter. 41-57


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Experiment No. 1AIM: Simulation and realization of all logic gates.

COMPONENTS REQUIRED: FPGA board, FRCs, jumper and power supply.

Truth table with symbols


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Black Box

ca d

e

fb g

hi

Truth table Basic gates:

VHDL CODE VERILOG CODE

library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOG IC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity gates isPort ( a,b : in std_logic;

c,d,e,f,g,h,i : out std_logic);end gates;

architecture dataflw of gates is

beginc


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3)Now click the waveform and zoom it to view the result.Modelsim Output

Output (c to i)

PROCEDURE TO DOWNLOAD ONTO FPGA

1) Create a UCF (User Constraints File).2) Click on UCF file and choose assign package pins option as shown in the figure

below.


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3)Assign the package pins as shown in fig below

3) save the file.4) Click on the module and choose configure device option.5) The following icon will be displayed.


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6) Right click on the icon and select program option.7) Program succeeded message will be displayed.8) Make connections to main board and daughter boards( before configuring ) , give

necessary inputs from DIP SWITCH and observe the output on LEDs.

NET "a" LOC = "p74" ;

NET "b" LOC = "p75" ;NET "c" LOC = "p84" ;NET "d" LOC = "p114" ;NET "e" LOC = "p113" ;NET "f" LOC = "p115" ;NET "g" LOC = "p117" ;NET "h" LOC = "p118" ;NET "i" LOC = "p121" ;

Repeat the above Procedure to all the Programs.

RESULT: The logic gates design has been realized and simulated using HDL codes.


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Experiment No. 2AIM: Write a HDL code to describe the functions of half adder, half subtractor and Fullsubtractor.


(a)HALF ADDERTRUTH TABLE BASIC GATES

BOOLEAN EXPRESSIONS:

S=A B

C=A B


library IEEE;

use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOG IC_ARITH.ALL;useIEEE.STD_LOGIC_UNSIGNED.ALL;entity HA isPort ( a, b : in std_logic;

s, c : out std_logic);end HA;

architecture dataflow of HA is

begins


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(b)HALF SUBTRACTOR

TRUTH TABLE BOOLEAN EXPRESSIONS:

D = A B

Br = BA

_

BASIC GATES


library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOG IC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;entity hs is

Port ( a, b : in std_logic;d, br : out std_logic);

end hs;

architecture dataflow of hs is

begind


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(C)FULL SUBTRACTOR

TRUTH TABLE BOOLEAN EXPRESSIONS:

D= A B C

Br=_

A B + B Cin +_

A Cin

BASIC GATES


library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOG IC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;entity fs isPort ( a, b, c : in std_logic;

d, br : out std_logic);end fs;

architecture dataflw of fs isbegind


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Experiment No. 3AIM: Write HDL codes for the following combinational circuits.


a)

2 TO 4 DECODER

BLACK BOX

Y0Sel 0Sel 1 Y1

Y2E Y4

Truth Table of 2 to 4 decoder

E Sel1 Sel0 Y3 Y2 Y1 Y01 0 0 0 0 0 11 0 1 0 0 1 01 1 0 0 1 0 01 1 1 1 0 0 00 X X 0 0 0 0

DATA FLOW


library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity dec2_4 isport (a, b, en :in std_logic ;

y0, y1, y2, y3:out std_logic);end dec2_4;

architecture data flow of dec2_4 isbegin

y0


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NET "e" LOC = "p74";NET "sel" LOC = "p75";NET "sel" LOC = "p76";NET "y" LOC = "p112";NET "y" LOC = "p114";

NET "y" LOC = "p113";NET "y" LOC = "p115";

Simulation is done using ModelsimWaveform window : Displays output waveform for verification.

Output

b) 8 TO 3 ENCODER WITH PRIORITY

i7Z3

Z1

Z0

enxi0 V

en

Truth tableEn I7 I6 I5 I4 I3 I2 I1 I0 Z2 Z1 Z0 enx V1 X X X X X X X X 1 1 1 1 10 1 1 1 1 1 1 1 1 1 1 1 1 00 1 1 1 1 1 1 1 0 1 1 1 0 10 1 1 1 1 1 1 0 X 1 1 0 0 10 1 1 1 1 1 0 X X 1 0 1 0 10 1 1 1 1 0 X X X 1 0 0 0 10 1 1 1 0 x X X X 0 1 1 0 10 1 1 0 X X X X X 0 1 0 0 10 1 0 X X X X X X 0 0 1 0 10 0 X X X X X X X 0 0 0 0 1

8:3

ParityEncoder


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library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity encoder8_3 isPort ( i : in std_logic_vector(7 downto 0);

en : in std_logic;enx,V : out std_logic;z : out std_logic_vector(2 downto 0));

end enco2;

architecture behavioral of encoder8_3 isbegin

end behavioral ;

module enc8_3 (I, en, y, v);input [7:0]I;input en;output v;

output [2:0]y;sig y; sig v;always @ (en, I)beginif(en= =0)

v=0;else

v=1;endif ( I[7]= =1 & en= =1)y=3b111;

else if ( I[6]==1 & en==1) y=3b110;else if ( I[5]==1 & en==1) y=3b101;else if ( I[4]==1 & en==1) y=3b100;else if ( I[3]==1 & en==1) y=3b011;else if ( I[2]==1 & en==1) y=3b010;else if ( I[1]==1 & en==1) y=3b001;else if ( I[0]==1 & en==1) y=3b000;else y=3b000;endend module

#PACE: Start of Constraints generated by PACE#PACE: Start of PACE I/O Pin AssignmentsNET "en" LOC = "p84";NET "i" LOC = "p85";NET "i" LOC = "p86";NET "i" LOC = "p87";NET "i" LOC = "p93";

NET "i" LOC = "p94";NET "i" LOC = "p95";NET "i" LOC = "p100";NET "i" LOC = "p74";NET "enx" LOC = "p112";NET "V" LOC = "p114";NET "z" LOC = "p113";NET "z" LOC = "p115";NET "z" LOC = "p117";


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Output

c) 8 TO 1 MULTIPLEXER

a

bcd Zefgh

sel(2 to 0)

Truth tableSel2 Sel1 Sel0 Z0 0 0 A0 0 1 B0 1 0 C0 1 1 D

1 0 0 E1 0 1 F1 1 0 G1 1 1 H

8:1Mux


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entity mux8_1 isport(I: in std_logic_vector (7 downto 0);

S: in std_logic_vector (2 downto 0);en: in std_logic; y: out std_logic);

end mux8_1;architecture behavioral of mux8_1 is

beginprocess (I,s,en) is

beginif en=1 then

if S=000 then y


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d) 4-BIT BINARY TO GRAY COUNTER CONVERTERBlack Box

clken q(3 downto 0)

rst

Truth table

Rst Clk En B3 B2 B1 B0 G3 G2 G1 G0

1 X 0 0 0 0 0 0 0 0 00 1 1 0 0 0 1 0 0 0 10 1 1 0 0 1 0 0 0 1 10 1 1 0 0 1 1 0 0 1 00 1 1 0 1 0 0 0 1 1 00 1 1 0 1 0 1 0 1 1 10 1 1 0 1 1 0 0 1 0 10 1 1 0 1 1 1 0 1 0 00 1 1 1 0 0 0 1 1 0 00 1 1 1 0 0 1 1 1 0 1

0 1 1 1 0 1 0 1 1 1 10 1 1 1 0 1 1 1 1 1 00 1 1 1 1 0 0 1 0 1 00 1 1 1 1 0 1 1 0 1 10 1 1 1 1 1 0 1 0 0 10 1 1 1 1 1 1 1 0 0 0

4 bitBinary to

gray


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entity bintogray isPort ( rst,clk : in std_logic;

g : inout std_logic_vector(3 downto 0));

end bintogray;

architecture Behavioral of bintogray issignal b: std_logic_vector( 3 downto 0);beginprocess(clk,rst)begin

if rst='1' then b


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e) MULTIPLEXER(4 TO 1)Black Box

a

b Zc

dsel (1 to 0)

Truth TableSel1 Sel0 Z0 0 a0 1 b1 0 c

1 1 d


entity mux1 isPort ( en,I : in std_logic;

sel:in std_logic_vector(1downto 0);y : out std_logic);

end mux1;architecture dataflow of mux1 isbegin

z


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f) DE-MULTIPLEXER ( 1 TO 4)

Black Box

aen Y(3 downto 0)

sel(1 downto 1)

Truth tablea En Sel1 Sel0 Y3 Y2 Y1 Y01 0 0 0 0 0 0 11 0 0 1 0 0 1 01 0 1 0 0 1 0 01 0 1 1 1 0 0 00 1 X X 0 0 0 0


entity demux isPort ( I,en : in std_logic;sel: in std_logic_vector(1 downto 0);

y:outstd_logic_vector(3downto0));end demux;architecture dataflow of demux issignal x: std_logic_vector( 1 downto 0);beginx


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output

NET "a" LOC = "p84";NET "en" LOC = "p85";NET "sel" LOC = "p86";NET "sel" LOC = "p87";NET "y" LOC = "p112";

NET "y" LOC = "p114";NET "y" LOC = "p113"; NET "y" LOC = "p115";

Output

g) 1-BIT COMPARATOR (STRUCTURAL)Black Box

a L

Eb

G

1bitComparat

or


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Truth table

A B L E G0 0 0 1 00 1 1 0 01 0 0 0 11 1 0 1 0


entity b_comp1 isport( a, b: in std_logic;

L,E,G: out std_logic);end;

architecture structural of b_comp1 iscomponent not_2 is

port( a: in std_logic;b: out std_logic);

end component;

component and_2 isport( a, b: in std_logic;

c: out std_logic);end component;

component xnor_2 isport( a, b: in std_logic;

c: out std_logic);end component;signal s1,s2: std_logic;begin

X1: not_2 port map (a, s1);X2: not_2 port map (a, s2);X3: and_2 port map (s1, b, L);X4: and_2 port map (s2, a, G);X5: xnor_2 port map (a, b, E);end structural;

module b_comp1 (a, b, L, E,G);input a, b; output L, E, G;wire s1, s2;not X1(s1, a);not X2 (s2, b);and X3 (L,s1, b);and X4 (G,s2, a);xnor X5 (E, a, b);end module


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outputNET "a" LOC = "p74" ;NET "b" LOC = "p75" ;NET "E" LOC = "p86" ;

NET "G" LOC = "p85" ;NET "L" LOC = "p84" ;

1-BIT COMPARATOR (DATA FLOW)


entity bcomp isport( a, b: in std_logic;

c, d, e: out std_logic);end bcomp;

architecture dataflow of bcomp isbegin

c


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entity compart4bit isPort ( a,b : in std_logic_vector(3 downto 0);

aeqb,agtb,altb: out std_logic);

end compart4bit;

architecture Behavioral ofcompart4bit isbegin

process (a,b)begin

if a > b then aeqb


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Experiment No. 4AIM: Write HDL code to describe the functions of a full Adder Using three modeling styles.


DATA FLOWBlack box

Truth table

INPUTS OUTPUTS

a B cin SUM Cout

0 0 0 0 0

0 0 1 1 0

0 1 0 1 0

0 1 1 0 1

1 0 0 1 0

1 0 1 0 1

1 1 0 0 1

1 1 1 1 1


entity fulladder isPort ( a,b,c : in std_logic;

s,cout : out std_logic);end fulladr;

architecture data of fulladr isbegin

sum


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BEHAVIORAL STYLE


entity fulladder beh isPort ( a,b,c : in std_logic;

sum,carry : out std_logic);end fulladrbeh;

architecture Behavioral of fulladrbeh isbeginprocess( a,b,c)begin

if(a='0' and b='0' and c='0') then sum


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STRUCTURAL STYLE


entity fullstru is

Port ( a,b,cin : in std_logic;sum,carry : out std_logic);

end fullstru;

architecture structural of fullstru is

signal c1,c2,c3:std_logic;component xor_3

port(x,y,z:in std_logic;u:out std_logic);

end component;

component and_2port(l,m:in std_logic;

n:out std_logic);end component;

component or_3port(p,q,r:in std_logic;s:out std_logic);

end component;

beginX1: xor_3 port map ( a, b, cin,sum);A1: and_2 port map (a, b, c1);A2: and_2 port map (b,cin,c2);A3: and_2 port map (a,cin,c3);O1: or_3 port map (c1,c2,c3,carry);

end structural;

module fa (x,y,z,cout,sum);

input x,y,z;output cout,sum;wire P1,P2,P3;

HA HA1 (sum(P1),cout(P2),a(x), b(y));HA HA2 (sum(sum),carry(P3),a(P1),b(Z));OR1 ORG (P2,P3, Cout);

endmodule


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Supporting Component Gates for Stuctural Full Adder

//and gate//library IEEE;use IEEE.STD_LOGIC_1164.ALL;

entity and2 isPort ( l,m : in std_logic;

n : out std_logic);end and2;architecture dataf of and2 isbeginn


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Full adder data flow i/o pins

NET "a" LOC = "P74";

NET "b" LOC = "P75";NET "cin" LOC = "P76";NET "cout" LOC = "P84";NET "sum" LOC = "P85";

Sum output carry output

RESULT: Three modeling styles of full adder have been realized and simulated using HDL.codes.


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Experiment No. 5

AIM: Write a model for 32 bit ALU using the schematic diagram shown below.

COMPONENTS REQUIRED:FPGA/CPLD board, FRCs, jumper and power supply.

OPCODE ALU OPERATION

1 A+B2 A-B3 A Complement4 A*B5 A and B6 A or B7 A nand B8 A xor B9 Right shift

10 Left Shift11 Parallel load

Black box

A1(3 to 0)

B1(3 to 0)Zout (7 downto 0)

opcode (2 to 0)

Truth tableOperation Opcode A B ZoutA+B 000 1111 0000 00001111A-B 001 1110 0010 00001100A or B 010 1111 1000 00001111A and B 011 1001 1000 00001000Not A 100 1111 0000 11110000A1*B1 101 1111 1111 11100001A nand B 110 1111 0010 11111101A xor B 111 0000 0100 00000100

ALU


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entity alunew isPort( a1,b1:in std_logic_vector(3 downto 0);

opcode : in std_logic_vector(2 downto 0);zout : out std_logic_vector(7 downto 0));

end alunew;

architecture Behavioral of alunew issignal a: std_logic_vector( 7 downto 0);signal b: std_logic_vector( 7 downto 0);begin

a


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Experiment No. 6

AIM: Develop the HDL code for the following flip flop: T, D, SR, JK.


T FLIPFLOP

Black Box

tclk q

rst qb


entity tff isPort ( t,clk : in STD_LOGIC;

q,qb : out STD_LOGIC);end tff;

architecture Behavioral of tff issignal clkd:std_logic_vector(21 downto 0);begin

process(clkd)beginif rising_edge(clk) thenclkd


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Truth tableRst T Clk q1 0 1 q1 1 1 qb1 X No +ve edge Previous state

0 X X 0

Rising edgeOutput

D FLIP-FLOP

Black Box

dq

clk qb


entity dff isPort ( d,clk : in STD_LOGIC;q,qb : out STD_LOGIC);end dff;architecture Behavioral of dff issignal clkd:std_logic_vector(21 downto 0);beginprocess(clkd)beginif rising_edge(clk) thenclkd


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Truth tableclk D Q qbX 1 1 01 1 1 0

1 0 0 1

Output at rising edge

NET "clk" LOC = "P18";NET "d" LOC = "P74";NET "q" LOC = "P84";

NET "qb" LOC = "P85";

SR FLIP FLOP

Black Box

clk

s qr

rst qb

pr

Truth tableRst pr Clk s r q qb1 X X X X 0 10 1 X X X 1 00 0 1 0 0 Qb Qbprevious0 0 1 0 1 0 1

0 0 1 1 0 1 00 0 1 1 1 1 1

SR FF


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entity srff isPort ( s,r,rst,clk : in STD_LOGIC;

q,qb : out STD_LOGIC);end srff;

architecture Behavioral of srff is

signal clkd:std_logic_vector(21 downto 0);beginprocess(clkd)beginif rising_edge(clk) thenclkd temp1:='0'; temp2:='1';

when "10"=> temp1:='1'; temp2:='0';when "11"=> temp1:='1'; temp2:='1';

when others=> null;end case;end if;else temp1:='0'; temp2:='1';end if;q


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JK FLIPFLOP

Black Box

jk q

clk qb

rst

VHDL CODE VERILOG

entity jkff isPort ( j,k,rst,clk : in STD_LOGIC;

q,qb : out STD_LOGIC);end jkff;

architecture Behavioral of jkff issignal clkd:std_logic_vector(21 downto 0);beginprocess(clkd)beginif rising_edge(clk) thenclkd temp:='0';

when "10"=> temp:='1';when "11"=> temp:=not temp;when others=> null;

end case;end if;else temp:='0';end if;q


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Truth tableRst Clk J K Q Qb1 1 0 0 Previous state1 1 0 1 0 11 1 1 0 1 01 1 1 1 Qb Q1 No+ve egde - - Previous state0 - - - 0 1

Output (when input 00 and rising edge)

NET "clk" LOC = "p18";NET "j" LOC = "p84";NET "k" LOC = "p85";NET "rst" LOC = "p86";

NET "q" LOC = "p112";NET "qb" LOC = "p114";

RESULT: Flip-flop operations have been realized and simulated using HDL codes


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Experiment No. 7

AIM: Design 4 bit Binary, BCD Counter (Synchronous reset and Asynchronous reset andany sequence counters.


a) BCD COUNTERBlack Box

clkq(3 downto 0)

rst

Truth tableRst Clk Q1 X 00000 1 00010 1 00100 1 0011

0 1 01000 1 01010 1 01100 1 011100

11

10001001

BCDcounter


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entity bcd is

Port ( clr,clk,dir : in STD_LOGIC;q : inout STD_LOGIC_VECTOR (3

downto 0);tc : out STD_LOGIC);

end bcd;architecture Behavioral of bcd issignal clkd:std_logic_vector(21 downto 0);beginprocess(clk)beginif rising_edge(clk) then

clkd


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b) GRAY COUNTERBlack Box

clken q(3 downto 0)rst


entity gray isPort ( clr,clk : in STD_LOGIC;

q : out STD_LOGIC_VECTOR (2downto 0));end gray;architecture Behavioral of gray issignal clkd:std_logic_vector(21 downto 0);

beginprocess(clk)beginif rising_edge(clk) thenclkd temp:="001";when "001"=> temp:="011";when "011"=> temp:="010";when "010"=> temp:="110";when "110"=> temp:="111";when "111"=> temp:="101";when "101"=> temp:="100";when "100"=> temp:="000";when others => null;

end case;end if;else temp:="000";end if;q


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Truth tableRst Clk En B3 B2 B1 B0 G3 G2 G1 G01 X 0 0 0 0 0 0 0 0 00 1 1 0 0 0 1 0 0 0 10 1 1 0 0 1 0 0 0 1 10 1 1 0 0 1 1 0 0 1 00 1 1 0 1 0 0 0 1 1 00 1 1 0 1 0 1 0 1 1 10 1 1 0 1 1 0 0 1 0 10 1 1 0 1 1 1 0 1 0 00 1 1 1 0 0 0 1 1 0 00 1 1 1 0 0 1 1 1 0 10 1 1 1 0 1 0 1 1 1 10 1 1 1 0 1 1 1 1 1 00 1 1 1 1 0 0 1 0 1 00 1 1 1 1 0 1 1 0 1 10 1 1 1 1 1 0 1 0 0 1

0 1 1 1 1 1 1 1 0 0 0

c) BINARY COUNTER(UP/DOWN)Black Box

clk

qout(3 dt 0)rst

Truth tableClk Rst QoutX 1 00001 0 00011 0 00101 0 00111 0 01001 0 01011 0 01101 0 0111

1 0 10001 0 10011 0 10101 0 10111 0 11001 0 11011 0 11101 0 1111

Binarycounter


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VHDL CODE VERILOG

entity bin_as isPort ( dir,clr,clk : in STD_LOGIC;

q : out STD_LOGIC_VECTOR (3downto 0));end bin_as;

architecture Behavioral of bin_as issignal clkd:std_logic_vector(21 downto 0);beginprocess(clk)beginif rising_edge(clk) thenclkd


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Experiment No. 8

AIM: Simulation and realization of Ring counter.


RING COUNTER

Implement design Configure device (impact)after switching on power supply

Select the slave serial mode Select the source file Right click on xilinx and select program

Connect input port to dip switch and output port to leds. Vary the inputsand view the corresponding outputs.


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SL.

NO.

Infrastructure Requirement

AICTE/University

Norms

Actually

provided Cost/

Amount

Year of

purchase

4.2.0VHDL LAB

4.2.1Multi-Vendor Universal Demo

Board(kit includes motherboard

along with downloading Cables)

Power supply, Xilinx FPGA-100kgate density Xilinx CPLD.Interfacing cards VTU interface-1& VTU interface-2along with above motherboards toperform all experiments ofVHDL lab as per revised VTUsyllabus

10 12 20000/240000

1-02-05

4.2.2CM 640 Chipmax

Pattern generator cum LogicAnalyzer-64 channel

04 06 40000/240000

1-02-05

4.2.3Chipscope Pro-logic

Analyzer from AGILENTTechnologies for on-chipdebugging and real-time analysisof XilinxFPGAs

01 01 20000/20000

1-02-05

4.2.4 SiMS-VLSI Universal VLSITrainer/Evaluation KitJ Tag Cable 1NoPower Supply 1NoOperation Manual 1No

02 02 38,270.40 19-07-04

4.2.5 SiMS PLD (Spartan-II, CPLDcool runner, SPROM)(3 Nos)

1 set each 1 set each 9,954.00 19-07-04

4.2.6 SiMS-GPIO General purposeIntegrated Interface module

01 01 4,725.00 19-07-04

4.2.7 Foundation Express: XILINX6.1i Version: ISE

01 01 42,000.00

Inclusive of all taxes Grand Total: 5,44,949.40

SL.

NO.

Infrastructure Requirement

AICTE/University

Norms

Actually

provided Cost/

Amount

Year of

purchase


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entity bcd isPort ( clr,clk,dir : in STD_LOGIC;

q : inout STD_LOGIC_VECTOR (3 downto 0);tc : out STD_LOGIC);

end bcd;architecture Behavioral of bcd issignal clkd:std_logic_vector(21 downto 0);

beginprocess(clk)beginif rising_edge(clk) thenclkd


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variable temp:std_logic_vector(3 downto 0):="0010";begin

if rising_edge(clkd(21)) thenif (clr='0') thenif (dir='1') thentemp:=temp+'1';else

temp:=temp-'1';end if;else temp:="0000";end if;end if;q


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architecture Behavioral of gray issignal clkd:std_logic_vector(21 downto 0);

beginprocess(clk)beginif rising_edge(clk) thenclkd temp:="001";when "001"=> temp:="011";when "011"=> temp:="010";when "010"=> temp:="110";when "110"=> temp:="111";when "111"=> temp:="101";when "101"=> temp:="100";when "100"=> temp:="000";when others => null;end case;end if;else temp:="000";end if;q


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end process;

end Behavioral;

entity ring is

Port ( clk,clr,l : in STD_LOGIC;

q : inout STD_LOGIC_VECTOR (3 downto 0));end ring;

architecture Behavioral of ring issignal clkd:std_logic_vector(21 downto 0);



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4'd9:y={4'd0,(~a^b)};default:begin endendcaseend

elsey=8'd0;end

endmodulemodule bcd(clr,clk,dir, tc, q);input clr,clk,dir;output reg tc;output reg[3:0] q;

always@(posedge clk,posedge clr)beginif(clr==1)q=4'd0;else

beginif (dir==1)q=q+1;

else if(dir==0)q=q-1;if(dir==1 & q==4'd10)

beginq=4'd0;tc=1'b1;endelse if(dir==0 & q==4'd15)

beginq=1'd9;tc=1'b1;endelse tc=1'b0;endend

endmodulemodule bin_as(clk,clr,dir, temp);

input clk,clr,dir;output reg[3:0] temp;

always@(posedge clk,posedge clr)beginif(clr==0)

beginif(dir==0)temp=temp+1;else temp=temp-1;endelse

temp=4'd0;end

endmodule

module binary(clk,clr,dir, temp);input clk,clr,dir;output reg[3:0]temp;

always@(posedge clk)beginif(clr==0)


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beginif(dir==0)temp=temp+1;else temp=temp-1;endelsetemp=4'd0;end

endmodule

module gray(clr,clk, q);input clr,clk;output reg[2:0] q;

reg temp=3'd0;always@(posedge clk,posedge clr)

beginif(clr==0)

begincase(temp)3'd0:q=3'd1;3'd1:q=3'd3;3'd2:q=3'd6;3'd3:q=3'd2;3'd6:q=3'd7;3'd7:q=3'd5;3'd5:q=3'd4;3'd4:q=3'd0;endcaseendelse q=3'd0;end

endmodule

module jhonson(clk,clr, q);input clk,clr;output reg[3:0] q;


q={(~q[0]), q[3:1]};end

endmodulemodule ring(clk,clr,l, q);input clk,clr,l;output reg[3:0] q;


begin


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if (l==1)q=4'd8;elseq={q[0], q[3:1]};endend

endmodule

entity bcd isPort ( clr,clk,dir : in STD_LOGIC;

q : inout STD_LOGIC_VECTOR (3 downto 0);tc : out STD_LOGIC);

end bcd;architecture Behavioral of bcd issignal clkd:std_logic_vector(21 downto 0);



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clkd


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end Behavioral;entity gray is

Port ( clr,clk : in STD_LOGIC;q : out STD_LOGIC_VECTOR (2 downto 0));

end gray;

architecture Behavioral of gray issignal clkd:std_logic_vector(21 downto 0);

beginprocess(clk)beginif rising_edge(clk) thenclkd temp:="001";when "001"=> temp:="011";when "011"=> temp:="010";when "010"=> temp:="110";when "110"=> temp:="111";when "111"=> temp:="101";when "101"=> temp:="100";when "100"=> temp:="000";when others => null;end case;end if;else temp:="000";end if;

q


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if (clr='1') then q


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beginprocess(clkd)beginif rising_edge(clk) thenclkd null;end case;end if;else temp:='0';end if;q


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end Behavioral;entity srff is

Port ( s,r,rst,clk : in STD_LOGIC;q,qb : out STD_LOGIC);

end srff;

architecture Behavioral of srff is

signal clkd:std_logic_vector(21 downto 0);beginprocess(clkd)beginif rising_edge(clk) thenclkd temp1:='0'; temp2:='1';

when "10"=> temp1:='1'; temp2:='0';when "11"=> temp1:='1'; temp2:='1';when others=> null;end case;end if;else temp1:='0'; temp2:='1';end if;

q


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if rising_edge(clk) thenif (t='1') thentemp:=not temp;elsetemp:=temp;end if;end if;q


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always@(posedge clk,posedge rst)begin

sr={s,r};if(rst==0)

begincase (sr)2'd1:q=1'b0;2'd2:q=1'b1;

2'd3:q=1'b1;default: begin endendcaseend

elsebegin

q=1'b0;end

qb=~q;end

endmodulemodule tff(t,clk,rst, q,qb);

input t,clk,rst;output q,qb;

reg q,qb;reg temp=0;always@(posedge clk,posedge rst)

begin

if (rst==0) beginif(t==1) begintemp=~ temp;end

elsetemp=temp;

end

q=temp;qb=~temp;end

endmodule

module alu1(a,b,s,en,y);input [3:0] s,a,b;

input en;output reg [7:0] y;always@(a,b,s,en,y)

beginif(en==1)

begincase(s)4'd0:y=a+b;4'd1:y=a-b;4'd2:y=a*b;


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4'd3:y={4'd0,~a};4'd4:y={4'd0,(a&b)};4'd5:y={4'd0,(a|b)};4'd6:y={4'd0,(a^b)};

4'd7:y={4'd0,~(a&b)};4'd8:y={4'd0,~(a|b)};

4'd9:y={4'd0,(~a^b)};default:begin end

endcaseendelse

y=8'd0;end

endmodule

VLSI Lab Mannual1

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