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CMOS Fabrication...Or What Lies Beneath...
Anurup Mitra
BITS Pilani
January 2007
Anurup Mitra CMOS Fabrication
![Page 2: 3 Fabrication](https://reader033.fdocuments.us/reader033/viewer/2022051017/563dbb3a550346aa9aab5a74/html5/thumbnails/2.jpg)
Wire Bonding
Anurup Mitra CMOS Fabrication
![Page 3: 3 Fabrication](https://reader033.fdocuments.us/reader033/viewer/2022051017/563dbb3a550346aa9aab5a74/html5/thumbnails/3.jpg)
Fabrication Process
A chip consists of layers of different materials which are electricallyisolated from each other.
To make an electrical contact betweenunlike layers, a contact or via is used.
The fabrication sequence consists of a series of steps in whichlayers of the chip are defined through photolithography.Photolithography uses ‘masks’ to transfer the patterns for eachlayer one at a time.
Since many entire chips are printed at once, the cost isproportional to the area rather than the number of devices beingused in the chip/s.
Anurup Mitra CMOS Fabrication
![Page 4: 3 Fabrication](https://reader033.fdocuments.us/reader033/viewer/2022051017/563dbb3a550346aa9aab5a74/html5/thumbnails/4.jpg)
Fabrication Process
A chip consists of layers of different materials which are electricallyisolated from each other. To make an electrical contact betweenunlike layers, a contact or via is used.
The fabrication sequence consists of a series of steps in whichlayers of the chip are defined through photolithography.Photolithography uses ‘masks’ to transfer the patterns for eachlayer one at a time.
Since many entire chips are printed at once, the cost isproportional to the area rather than the number of devices beingused in the chip/s.
Anurup Mitra CMOS Fabrication
![Page 5: 3 Fabrication](https://reader033.fdocuments.us/reader033/viewer/2022051017/563dbb3a550346aa9aab5a74/html5/thumbnails/5.jpg)
Fabrication Process
A chip consists of layers of different materials which are electricallyisolated from each other. To make an electrical contact betweenunlike layers, a contact or via is used.
The fabrication sequence consists of a series of steps in whichlayers of the chip are defined through photolithography.
Photolithography uses ‘masks’ to transfer the patterns for eachlayer one at a time.
Since many entire chips are printed at once, the cost isproportional to the area rather than the number of devices beingused in the chip/s.
Anurup Mitra CMOS Fabrication
![Page 6: 3 Fabrication](https://reader033.fdocuments.us/reader033/viewer/2022051017/563dbb3a550346aa9aab5a74/html5/thumbnails/6.jpg)
Fabrication Process
A chip consists of layers of different materials which are electricallyisolated from each other. To make an electrical contact betweenunlike layers, a contact or via is used.
The fabrication sequence consists of a series of steps in whichlayers of the chip are defined through photolithography.Photolithography uses ‘masks’ to transfer the patterns for eachlayer one at a time.
Since many entire chips are printed at once, the cost isproportional to the area rather than the number of devices beingused in the chip/s.
Anurup Mitra CMOS Fabrication
![Page 7: 3 Fabrication](https://reader033.fdocuments.us/reader033/viewer/2022051017/563dbb3a550346aa9aab5a74/html5/thumbnails/7.jpg)
Fabrication Process
A chip consists of layers of different materials which are electricallyisolated from each other. To make an electrical contact betweenunlike layers, a contact or via is used.
The fabrication sequence consists of a series of steps in whichlayers of the chip are defined through photolithography.Photolithography uses ‘masks’ to transfer the patterns for eachlayer one at a time.
Since many entire chips are printed at once, the cost isproportional to the area rather than the number of devices beingused in the chip/s.
Anurup Mitra CMOS Fabrication
![Page 8: 3 Fabrication](https://reader033.fdocuments.us/reader033/viewer/2022051017/563dbb3a550346aa9aab5a74/html5/thumbnails/8.jpg)
CMOS Technologies
The main CMOS technologies are :
n-well The pMOS transistors are placed in the n-well andthe nMOS transistors are created on the substrate
p-well Guess!
twin-well This technology allows optimisation of eachtransistor type
triple-well This process permits excellent isolation betweenanalog and digital circuitry in a mixed signal chip
Anurup Mitra CMOS Fabrication
![Page 9: 3 Fabrication](https://reader033.fdocuments.us/reader033/viewer/2022051017/563dbb3a550346aa9aab5a74/html5/thumbnails/9.jpg)
CMOS Technologies
The main CMOS technologies are :
n-well The pMOS transistors are placed in the n-well andthe nMOS transistors are created on the substrate
p-well Guess!
twin-well This technology allows optimisation of eachtransistor type
triple-well This process permits excellent isolation betweenanalog and digital circuitry in a mixed signal chip
Anurup Mitra CMOS Fabrication
![Page 10: 3 Fabrication](https://reader033.fdocuments.us/reader033/viewer/2022051017/563dbb3a550346aa9aab5a74/html5/thumbnails/10.jpg)
CMOS Technologies
The main CMOS technologies are :
n-well The pMOS transistors are placed in the n-well andthe nMOS transistors are created on the substrate
p-well Guess!
twin-well This technology allows optimisation of eachtransistor type
triple-well This process permits excellent isolation betweenanalog and digital circuitry in a mixed signal chip
Anurup Mitra CMOS Fabrication
![Page 11: 3 Fabrication](https://reader033.fdocuments.us/reader033/viewer/2022051017/563dbb3a550346aa9aab5a74/html5/thumbnails/11.jpg)
CMOS Technologies
The main CMOS technologies are :
n-well The pMOS transistors are placed in the n-well andthe nMOS transistors are created on the substrate
p-well Guess!
twin-well This technology allows optimisation of eachtransistor type
triple-well This process permits excellent isolation betweenanalog and digital circuitry in a mixed signal chip
Anurup Mitra CMOS Fabrication
![Page 12: 3 Fabrication](https://reader033.fdocuments.us/reader033/viewer/2022051017/563dbb3a550346aa9aab5a74/html5/thumbnails/12.jpg)
Photolithography
The primary method for defining areas of interest (i.e. where wewant materials to be absent or present) on a wafer is by the use ofphotoresists.
The wafer is coated with the photoresist and subjected to selectiveillumination by the photomask or reticle.
Anurup Mitra CMOS Fabrication
![Page 13: 3 Fabrication](https://reader033.fdocuments.us/reader033/viewer/2022051017/563dbb3a550346aa9aab5a74/html5/thumbnails/13.jpg)
Photolithography
The primary method for defining areas of interest (i.e. where wewant materials to be absent or present) on a wafer is by the use ofphotoresists.
The wafer is coated with the photoresist and subjected to selectiveillumination by the photomask or reticle.
Anurup Mitra CMOS Fabrication
![Page 14: 3 Fabrication](https://reader033.fdocuments.us/reader033/viewer/2022051017/563dbb3a550346aa9aab5a74/html5/thumbnails/14.jpg)
...contd.
A photomask is created with chromium (chrome) covered quartzglass.
An ultraviolet light source is used to expose the photoresist.The UV light floods the mask from the backside of the mask andpasses through the clear sections of the mask to expose the PRthat has been coated on the wafer.
A developer solvent is then used to dissolve the soluble unexposedPR, leaving islands of insoluble exposed photoresist. This, by theway, is known as a negative photoresist.
A positive resist is initially insoluble and becomes soluble afterexposure to UV.
Positive resists provide higher resolutions than negative resists butare however, less sensitive to light. As feature sizes shrink, PR’s aremade smaller and this in turn makes them more prone to failure.
Anurup Mitra CMOS Fabrication
![Page 15: 3 Fabrication](https://reader033.fdocuments.us/reader033/viewer/2022051017/563dbb3a550346aa9aab5a74/html5/thumbnails/15.jpg)
...contd.
A photomask is created with chromium (chrome) covered quartzglass. An ultraviolet light source is used to expose the photoresist.The UV light floods the mask from the backside of the mask andpasses through the clear sections of the mask to expose the PRthat has been coated on the wafer.
A developer solvent is then used to dissolve the soluble unexposedPR, leaving islands of insoluble exposed photoresist. This, by theway, is known as a negative photoresist.
A positive resist is initially insoluble and becomes soluble afterexposure to UV.
Positive resists provide higher resolutions than negative resists butare however, less sensitive to light. As feature sizes shrink, PR’s aremade smaller and this in turn makes them more prone to failure.
Anurup Mitra CMOS Fabrication
![Page 16: 3 Fabrication](https://reader033.fdocuments.us/reader033/viewer/2022051017/563dbb3a550346aa9aab5a74/html5/thumbnails/16.jpg)
...contd.
A photomask is created with chromium (chrome) covered quartzglass. An ultraviolet light source is used to expose the photoresist.The UV light floods the mask from the backside of the mask andpasses through the clear sections of the mask to expose the PRthat has been coated on the wafer.
A developer solvent is then used to dissolve the soluble unexposedPR, leaving islands of insoluble exposed photoresist.
This, by theway, is known as a negative photoresist.
A positive resist is initially insoluble and becomes soluble afterexposure to UV.
Positive resists provide higher resolutions than negative resists butare however, less sensitive to light. As feature sizes shrink, PR’s aremade smaller and this in turn makes them more prone to failure.
Anurup Mitra CMOS Fabrication
![Page 17: 3 Fabrication](https://reader033.fdocuments.us/reader033/viewer/2022051017/563dbb3a550346aa9aab5a74/html5/thumbnails/17.jpg)
...contd.
A photomask is created with chromium (chrome) covered quartzglass. An ultraviolet light source is used to expose the photoresist.The UV light floods the mask from the backside of the mask andpasses through the clear sections of the mask to expose the PRthat has been coated on the wafer.
A developer solvent is then used to dissolve the soluble unexposedPR, leaving islands of insoluble exposed photoresist. This, by theway, is known as a negative photoresist.
A positive resist is initially insoluble and becomes soluble afterexposure to UV.
Positive resists provide higher resolutions than negative resists butare however, less sensitive to light. As feature sizes shrink, PR’s aremade smaller and this in turn makes them more prone to failure.
Anurup Mitra CMOS Fabrication
![Page 18: 3 Fabrication](https://reader033.fdocuments.us/reader033/viewer/2022051017/563dbb3a550346aa9aab5a74/html5/thumbnails/18.jpg)
...contd.
A photomask is created with chromium (chrome) covered quartzglass. An ultraviolet light source is used to expose the photoresist.The UV light floods the mask from the backside of the mask andpasses through the clear sections of the mask to expose the PRthat has been coated on the wafer.
A developer solvent is then used to dissolve the soluble unexposedPR, leaving islands of insoluble exposed photoresist. This, by theway, is known as a negative photoresist.
A positive resist is initially insoluble and becomes soluble afterexposure to UV.
Positive resists provide higher resolutions than negative resists butare however, less sensitive to light. As feature sizes shrink, PR’s aremade smaller and this in turn makes them more prone to failure.
Anurup Mitra CMOS Fabrication
![Page 19: 3 Fabrication](https://reader033.fdocuments.us/reader033/viewer/2022051017/563dbb3a550346aa9aab5a74/html5/thumbnails/19.jpg)
...contd.
A photomask is created with chromium (chrome) covered quartzglass. An ultraviolet light source is used to expose the photoresist.The UV light floods the mask from the backside of the mask andpasses through the clear sections of the mask to expose the PRthat has been coated on the wafer.
A developer solvent is then used to dissolve the soluble unexposedPR, leaving islands of insoluble exposed photoresist. This, by theway, is known as a negative photoresist.
A positive resist is initially insoluble and becomes soluble afterexposure to UV.
Positive resists provide higher resolutions than negative resists butare however, less sensitive to light.
As feature sizes shrink, PR’s aremade smaller and this in turn makes them more prone to failure.
Anurup Mitra CMOS Fabrication
![Page 20: 3 Fabrication](https://reader033.fdocuments.us/reader033/viewer/2022051017/563dbb3a550346aa9aab5a74/html5/thumbnails/20.jpg)
...contd.
A photomask is created with chromium (chrome) covered quartzglass. An ultraviolet light source is used to expose the photoresist.The UV light floods the mask from the backside of the mask andpasses through the clear sections of the mask to expose the PRthat has been coated on the wafer.
A developer solvent is then used to dissolve the soluble unexposedPR, leaving islands of insoluble exposed photoresist. This, by theway, is known as a negative photoresist.
A positive resist is initially insoluble and becomes soluble afterexposure to UV.
Positive resists provide higher resolutions than negative resists butare however, less sensitive to light. As feature sizes shrink, PR’s aremade smaller and this in turn makes them more prone to failure.
Anurup Mitra CMOS Fabrication
![Page 21: 3 Fabrication](https://reader033.fdocuments.us/reader033/viewer/2022051017/563dbb3a550346aa9aab5a74/html5/thumbnails/21.jpg)
Well and Channel Formation
Varying proportions of donor and acceptor impurities can beachieved by using epitaxy, desposition, or implantation.
Epitaxy Can produce a layer of silicon with fewer defects.Foundries provide a choice of epi or non-epi wafers.
Deposition Places dopant material on Si surface and drives it inwith thermal diffusion to create deep junctions. CVDcan be alternatively be used to lay down thin films ofmaterials.
Implantation Ion implantation impinges the Si substrate withhighly accelerated donor or acceptor atoms. It is thestandard method for well and source/drain formationtoday.
Anurup Mitra CMOS Fabrication
![Page 22: 3 Fabrication](https://reader033.fdocuments.us/reader033/viewer/2022051017/563dbb3a550346aa9aab5a74/html5/thumbnails/22.jpg)
Well and Channel Formation
Varying proportions of donor and acceptor impurities can beachieved by using epitaxy, desposition, or implantation.
Epitaxy Can produce a layer of silicon with fewer defects.Foundries provide a choice of epi or non-epi wafers.
Deposition Places dopant material on Si surface and drives it inwith thermal diffusion to create deep junctions. CVDcan be alternatively be used to lay down thin films ofmaterials.
Implantation Ion implantation impinges the Si substrate withhighly accelerated donor or acceptor atoms. It is thestandard method for well and source/drain formationtoday.
Anurup Mitra CMOS Fabrication
![Page 23: 3 Fabrication](https://reader033.fdocuments.us/reader033/viewer/2022051017/563dbb3a550346aa9aab5a74/html5/thumbnails/23.jpg)
Well and Channel Formation
Varying proportions of donor and acceptor impurities can beachieved by using epitaxy, desposition, or implantation.
Epitaxy Can produce a layer of silicon with fewer defects.Foundries provide a choice of epi or non-epi wafers.
Deposition Places dopant material on Si surface and drives it inwith thermal diffusion to create deep junctions. CVDcan be alternatively be used to lay down thin films ofmaterials.
Implantation Ion implantation impinges the Si substrate withhighly accelerated donor or acceptor atoms. It is thestandard method for well and source/drain formationtoday.
Anurup Mitra CMOS Fabrication
![Page 24: 3 Fabrication](https://reader033.fdocuments.us/reader033/viewer/2022051017/563dbb3a550346aa9aab5a74/html5/thumbnails/24.jpg)
Well and Channel Formation
Varying proportions of donor and acceptor impurities can beachieved by using epitaxy, desposition, or implantation.
Epitaxy Can produce a layer of silicon with fewer defects.Foundries provide a choice of epi or non-epi wafers.
Deposition Places dopant material on Si surface and drives it inwith thermal diffusion to create deep junctions. CVDcan be alternatively be used to lay down thin films ofmaterials.
Implantation Ion implantation impinges the Si substrate withhighly accelerated donor or acceptor atoms. It is thestandard method for well and source/drain formationtoday.
Anurup Mitra CMOS Fabrication
![Page 25: 3 Fabrication](https://reader033.fdocuments.us/reader033/viewer/2022051017/563dbb3a550346aa9aab5a74/html5/thumbnails/25.jpg)
Silicon Dioxide
Various thicknesses of SiO2 are required. While thin oxides areused for transistor gates, thick oxides are used for high voltagedevices. Even thicker oxides are used for device isolation.
Oxidation is achieved by heating Si wafers in an oxidisingatmosphere. A variety of processes are used:
Wet Ox This is when the oxidising atmosphere contains watervapour. It is a rapid process. It is used for fox.
Dry Ox Here, the oxidising atmosphere is pure oxygen. Thisforms better quality oxides and are used for thinox.
ALD Atomic Layer Deposition is a process in which a thinchemical layer is attached to a surface and a second(different) chemical layer is used to react with thefirst and produce a thin layer of the required product.
Anurup Mitra CMOS Fabrication
![Page 26: 3 Fabrication](https://reader033.fdocuments.us/reader033/viewer/2022051017/563dbb3a550346aa9aab5a74/html5/thumbnails/26.jpg)
Silicon Dioxide
Various thicknesses of SiO2 are required. While thin oxides areused for transistor gates, thick oxides are used for high voltagedevices. Even thicker oxides are used for device isolation.
Oxidation is achieved by heating Si wafers in an oxidisingatmosphere. A variety of processes are used:
Wet Ox This is when the oxidising atmosphere contains watervapour. It is a rapid process. It is used for fox.
Dry Ox Here, the oxidising atmosphere is pure oxygen. Thisforms better quality oxides and are used for thinox.
ALD Atomic Layer Deposition is a process in which a thinchemical layer is attached to a surface and a second(different) chemical layer is used to react with thefirst and produce a thin layer of the required product.
Anurup Mitra CMOS Fabrication
![Page 27: 3 Fabrication](https://reader033.fdocuments.us/reader033/viewer/2022051017/563dbb3a550346aa9aab5a74/html5/thumbnails/27.jpg)
Silicon Dioxide
Various thicknesses of SiO2 are required. While thin oxides areused for transistor gates, thick oxides are used for high voltagedevices. Even thicker oxides are used for device isolation.
Oxidation is achieved by heating Si wafers in an oxidisingatmosphere. A variety of processes are used:
Wet Ox This is when the oxidising atmosphere contains watervapour. It is a rapid process. It is used for fox.
Dry Ox Here, the oxidising atmosphere is pure oxygen. Thisforms better quality oxides and are used for thinox.
ALD Atomic Layer Deposition is a process in which a thinchemical layer is attached to a surface and a second(different) chemical layer is used to react with thefirst and produce a thin layer of the required product.
Anurup Mitra CMOS Fabrication
![Page 28: 3 Fabrication](https://reader033.fdocuments.us/reader033/viewer/2022051017/563dbb3a550346aa9aab5a74/html5/thumbnails/28.jpg)
Silicon Dioxide
Various thicknesses of SiO2 are required. While thin oxides areused for transistor gates, thick oxides are used for high voltagedevices. Even thicker oxides are used for device isolation.
Oxidation is achieved by heating Si wafers in an oxidisingatmosphere. A variety of processes are used:
Wet Ox This is when the oxidising atmosphere contains watervapour. It is a rapid process. It is used for fox.
Dry Ox Here, the oxidising atmosphere is pure oxygen. Thisforms better quality oxides and are used for thinox.
ALD Atomic Layer Deposition is a process in which a thinchemical layer is attached to a surface and a second(different) chemical layer is used to react with thefirst and produce a thin layer of the required product.
Anurup Mitra CMOS Fabrication
![Page 29: 3 Fabrication](https://reader033.fdocuments.us/reader033/viewer/2022051017/563dbb3a550346aa9aab5a74/html5/thumbnails/29.jpg)
Wafer
A bare Si wafer is chosen
The type will be n or p depending upon the technology
Anurup Mitra CMOS Fabrication
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Oxidation of Wafer
The wafer is oxidised at a high temperature
This must be patterned to define the n-well
Anurup Mitra CMOS Fabrication
![Page 31: 3 Fabrication](https://reader033.fdocuments.us/reader033/viewer/2022051017/563dbb3a550346aa9aab5a74/html5/thumbnails/31.jpg)
PR deposition
The photoresist is deposited throughout the wafer
The PR has to be patterned to allow formation of the well
Anurup Mitra CMOS Fabrication
![Page 32: 3 Fabrication](https://reader033.fdocuments.us/reader033/viewer/2022051017/563dbb3a550346aa9aab5a74/html5/thumbnails/32.jpg)
n-well Mask
The PR is exposed through the n-well mask
The softened PR is is removed to expose the oxide
Anurup Mitra CMOS Fabrication
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Oxide Etch
The oxide is etched with HF acid where unprotected by PR
The wafer is now exposed to the n-well area
Anurup Mitra CMOS Fabrication
![Page 34: 3 Fabrication](https://reader033.fdocuments.us/reader033/viewer/2022051017/563dbb3a550346aa9aab5a74/html5/thumbnails/34.jpg)
PR removal
The remaining PR is removed via piranha etch
The well is ready to be formed
Anurup Mitra CMOS Fabrication
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n-well Formation
The diffusion process can make the the n-well
Ion implantation can also form the same
Anurup Mitra CMOS Fabrication
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Oxide Removal
The remaining oxide is stripped with HF acid
This leaves the exposed wafer with the n-well formed
Anurup Mitra CMOS Fabrication
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Gate Formation
The gates are made up of polysilicon over thinox
CVD is used to grow the poly (heavily doped) layer
Anurup Mitra CMOS Fabrication
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Poly Patterning
The wafer is now patterned with PR and the poly mask
Finally this leaves the device gates
Anurup Mitra CMOS Fabrication
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Diffusion Pattern
Again, a protective oxide is grown and PR deposited
PR is patterned according to the diffusion mask
Anurup Mitra CMOS Fabrication
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Wafer Exposure for Diffusion
The protective oxide is etched away
The wafer is exposed for S/D/B formation
Anurup Mitra CMOS Fabrication
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n-Diffusion Regions
The n+ diffusion regions are formed
Polysilicon blocks the channel area
Anurup Mitra CMOS Fabrication
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Self-Aligned Process
This is a self-aligned process
S/D are automatically formed adjacent to the gate
Anurup Mitra CMOS Fabrication
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p-Diffusion
The p-diffusion mask is used next
This completes creation of all active regions
Anurup Mitra CMOS Fabrication
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Field Oxide
The field oxide is grown to insulate wafer and metal
It is patterned with the contact mask
Anurup Mitra CMOS Fabrication
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Metal Formation
Al is sputtered over the entire area filling contact cuts too
Metal is patterned with the metal mask
Anurup Mitra CMOS Fabrication
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Multilevel Metallisation - Fig. 1
Anurup Mitra CMOS Fabrication
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Multilevel Metallisation - Fig. 2
Anurup Mitra CMOS Fabrication