05-superscalar 2

8/3/2019 05-superscalar 2

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Nov 2010 ICS311 - superscalar architecture 2 1

Superscalar Processor Architecture(2)


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Super-scalar Processor

basic concept basic operation

Limitations/challenges

Architecture Issue policy Dealing with false dependencies

Other design issues

Operand fetch and update policies Dealing with conditional branches Preserving the sequential consistency of execution


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Register operand fetching, updating


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operand fetch policiesdirect issue

shelved issueissue bound

dispatch bound


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operand fetch policiesConsider the instruction in form of:

add Rd, Rs1, Rs2

E.g. in IA32: add AX, BX, CX

How/when do the values of the source operands reach theexecution unit?

How/when does the computed result get committed to thedestination operand?


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(direct issue)operand fetch policies

I-bufferdecode/issue

EU

reg file

src operands

src reg numbers

opcode, dest

reg nos.


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From decode/issue

register file

VRs1, Rs2, Rd

fetch Rs1, Rs2 (if avail),

reset V-bit of Rd

EU

OC Os1 Os2 Rd

update Rd, set its V-bit

(direct issue)operand fetch policies



shelved issue



I-buffer

decode/issue

shelving-buffer

dispatch

EU

operand fetch policies (shelved issue): issue bound

reg file

src operands

src reg numbers

opcode, destreg nos.

Operands are

fetched at issue



From decode/issue

EU

operand fetch/update (shelved issue): issue bound

register file

V

Rs1, Rs2, Rd


reset V-bit of Rd

Reservation Station

OC Os1 Vs1 Os2 Vs2 Rd


out-of-order dispatch1 instr/cycle



I-buffer

decode/issue

shelving-buffer

dispatch

EU

operand fetch policies (shelved issue): dispatch bound

reg file

src operands

src reg numbers

opcode, dest

reg nos.

operands are fetched

at dispatch



From decode/issue

EU

operand fetch/update (shelved issue): dispatch bound

register file

VRs1, Rs2, Rd


reset V-bit of Rd

Reservation Station

OC Rs1 Rs2 Rd


dispatch

OC Os1 Vs1 Os2 Vs2Rd


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In the case of shelved issue

Compare issue bound vs. dispatch bound


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Dealing with conditional branches:speculative execution:Speculative execution


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Non-speculative executionon encounter of a conditional branch,

suspend fetching and processingdependent instructions: leads to delays

Speculative execution

on encounter of a conditional branch,predict the direction of the branch andcontinue processing along the predictedpath.Avoids delays as long as predictionsare correct.


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Branch prediction

Static branch prediction

Predict never taken

Continue to fetch instructions sequentially until thebranch direction is resolved.

Predict always taken

As soon as the branch target is decoded, startfetching from the target. (Note that the target maybe decoded before the branch condition is evaluatedand branch direction is resolved.)

Speculative execution


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Static branch prediction

Predict by opcode, e.g.

JLE may be typically used for loop

control and the branch is usually taken.JE also used in loop control but is

usually not taken.

Compiler may exploit.


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Dynamic branch prediction

Taken/not taken switch Keep record of the result of the previous

execution of the branch and assume the currentexecution will go the same way.

Branch history table

Maintain recent history of a branchs executions.Use the history to predict direction.


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Branch prediction

what happens if the prediction is wrong?!


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Branch prediction

what happens if the prediction is wrong?!

Need to flush the speculatively issued, dispatched, and

executed instructions from buffers & EUs.

cancel/discard effects of the speculatively executed

instructions


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preserving the sequential consistency ofexecution:ROB


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parallel executioninstructions can finish out of program

order! Need to preserve seq consistency

Definitions:

distinguish

finish: required operation of instruction is

accomplished except writeback complete: last action performed, e.g. wb retire: wb + delete


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preserving sequential consistency of instruction executionusing

Re-order buffer (ROB)


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Re-order buffer (ROB) description & use cyclic buffer holding record of all active

instructions; issued but yet to be retired keeps track of state of instruction; e.g. i, x, f

head: first free slot tail: next instruction to be retired

add new instruction at head on issue an instruction in ROB may complete and retire if

it has finished and all instructions ahead haveretired


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I-buffer

shelving-buffers

dispatch unit

EUs

Preserving sequential consistency: ROB

ROB

completion/r

etire unit

issued

in execution

finished

completed/retired

decode/ issueunit


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Exercise


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Example superscalar pipeline

In-order issue. Non blocking. Issue rate = 1 instructionper cycle

Shelved issue. One 4 entry reservation station. No

bypass. 3 execution units same functions (iadd, isub, imul, idiv)

Possible out-of-order dispatch. Dispatch window = 3.Dispatch rate 1 instruction per cycle.

Execution times: iadd, isub=3cycles; imul, idiv = 6cycles.(EU not pipelined)

Register renaming with very large number of H/Wregisters

Exercise


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Given the following instruction stream

I1: iadd R1, R2, R3

I2: imul R4, R5, R6

I3: iadd R7, R8, R9

I4: iadd R4, R7, R8I5: idiv R10, R8, R3

I6: isub R2, R5, R6

I7: iadd R11, R3,R6

I8: isub R12, R3,R6

I9: .

Exercise

Instruction format:

opcode Rdest, Rsrc1, Rsrc2


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Trace the processing of I1 to I8 assuming that

initially, all the 8 instructions are in the I-buffer

Show contents of the I-buffer, RS and EUs duringeach cycle.

Show contents of the ROB during each cycleDerive the total execution time of the 8

instructions in cycles (from the time I1 is issuedto the time I8 is retired)

Exercise


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Super scalar implementation

Processor hardware requirements: summary


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Multiple pipelined fetch and decode stages,and branch prediction logic.

Logic for determining true datadependencies and mechanisms forcommunicating values to where needed

during execution. Mechanisms for issuing multiple

instructions in parallel.


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Resources for parallel execution of multipleinstructions

Multiple pipelined functional units

Memory hierarchies for simultaneousservicing of multiple references.

Mechanisms for committing the process

state in correct order.


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Recognizing opportunities for parallelprocessing of instructions


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Recognizing opportunities for parallel processing ofinstructions

Processor hardware Processor hardware designed to look for

and recognize opportunities forparallelism.

Implies sophisticated, expensive, bulkyhardware

Compiler support Compiler programmed to look for and

recognize opportunities for parallelism. Then communicate accordingly to the

hardware (machine language must support!)


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Recognizing opportunities for parallel processing of instructions

Programming language support

Programming language allows

programmer to communicateopportunities for parallel processing.

Information communicated to thehardware via the compiler


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Reading assignment:

Intel Pentium II super scalar processorarchitecture. Stalling pp.515-520.

Power PC 601 super scalar processorarchitecture. Stalling pp. 521-526

MPC7450 Microprocessor, Motorola. P. 1-4(attached)

S l A hit t


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Superscalar Architecture

practical assignment

Use the simplescalar simulation tool to demonstrate the

effects of superscalarity of a processor on performance as

measured by instruction throughput.You should be able to come up with a graph illustrating

the relationship between the two variables, i.e. a selected

aspect of superscalarity and instruction throughput.You may use a selected benchmark program in carrying

out the above.Hand in your results including a report on how you

obtained them.Work in groups of no more than four.

Ref: http://www.simplescalar.com


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