© 2010 MIPS Technologies, Inc. All rights reserved It’s The Core & Much More …. Key Success...

© 2010 MIPS Technologies, Inc. All rights reserved

It’s The Core & Much More ….

Key Success Factors to

32-bit MCU Design

Ying-wai Ho

General Manager, MIPS-Shanghai

MCU Technology and Application Forum

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2© 2010 MIPS Technologies, Inc. All rights reserved

The Heritage of the MIPS Architecture

Pioneered by Stanford President John Hennessy in the 1980s

Pure and elegant RISC architecture Clean, fast, efficient Designed for performance

Now the architecture of choice for multimedia, home networking & beyond

Innovation continues by MIPS and licensees including Altera, Broadcom, Cavium, ICT, NEC, RMI Corp., Toshiba and others

Widely used, widely taught architecture withmillions of lines of code written for it

Photo: In 1984, Stanford computer scientists John Shott, John Hennessy and James D. Meindl brainstorm about the MIPS project (Photo: Chuck Painter)

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MIPS-Shanghai - China Engineering Center

China Engineering Center

Dedicated Shanghai-based MIPS design & engineering center—hardware & software

Only leading processor company developing cores in China

New M14K and M14Kc soft cores based on microMIPS ISA

designed and developed entirely in China

Expanding Shanghai engineering teamLeveraging China talent and cost structure

Future plans for expanding operations in China to take on more engineering projects

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A Systematic Philosophy for Design Success

2006 Multi-threading

2007 Superscalar Performance

2008 Coherent multiprocessing

Foundation for Success Built on MIPS’ Legacy of Scalability

Highest performance, synthesizable, licensable 32-bit cores

microMIPS Advanced Code Compression

2005DSP Extensions

2010E

ffici

ency

and

Per

form

ance

2002 Microcontroller-specific cores

1999 MIPS32 and MIPS64 Architectures

2001

Industry’s First 64-bit microprocessor 1991

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Industry’s Most Scalable Processor Architecture

32-bit Microcontrollers

And everything in between 64-bit Networking

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Microcontrollers: Proliferating MIPS Architecture

Microchip—number 1 MCU provider32-bit PIC32 MCUs based on M4K core

Performance and power efficiency leadership

Proliferating MIPS architecture to large community of developers

Expanding family of core products M14K, M14Kc

Addressing MCU design challengesreal time operation, small size, low power

Extending MIPS Architecture microMIPS ISA code size reduction

Over 20 MCU Licensees including:

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Key Success Factors to 32-bit MCU Design

HIGHPERFORMANCE

LOWPOWER

SMALL SIZE

COMPLETETOOLS

LARGEECOSYSTEM

BESTARCHITECTURE

MCUFEATURES

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MIPS Architecture

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Wide Range of MIPS 32-Bit Processor Core Families

1004K

Broad range of synthesizable processorsoptimized for high performance & low power

24KE

24K

4KE

M4K

4KS

74K

Superscalar; 15-stage pipeline>1.5GHz prod, >2.4GHz typ (40nm)>6000 Coremark @ 2.4GHz

34K

Single threaded

perform

ance

Multi-th

reading

Coherent

Multipro

cessing

microMIPS advanced code compression & Enhanced MCU Features

(1-4 cores) Max ~1.5GHz prod (40nm) >12,000 Coremark 10,000 DMIPS @ 1.25 GHz

Coherent

Multipro

cessing

M14Kc

M14K

Mid-Range 8-stage pipeline DSP extensions900MHz prod (65nm)

5-stage pipeline 1.48 DMIPS/MHz 300MHz (65nm LP) 2.6 CoreMark/MHz >30% smaller code size

Smaller & faster than Cortex M3

MCU, Embedded 5-stage pipeline 1.5 DMIPS/MHz Low area & power

1074K

2010 EEPW - BEST IP award2010 EEPW - BEST IP awardMIPS32 M14K & M14KcMIPS32 M14K & M14Kc

Multi-Thread & Mult-Core Processing

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Architecture for Performance – M4K/M14K Family

1.5 DMIPS/MHz

Classic RISC deep pipeline

Single cycle throughput

Single operation instructions

Simple 32-bit addressing modes and 32-bit data bus

Less speculative execution

Efficient branching. No need for branch prediction.

Compatible with 32- and 64- bit architectures.

Many architecture extensions : ASE, UDI, COP, SPRam…

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Microchip PIC32 Performance

+20%

+30%

EEMBC Coremark benchmark scores

MIPS M4K

ARM Cortex-M3

ARM Cortex-M0

80MHz, 2 wait state, PIC32 outperforms other MCU devices operating at 120/100MHz, 0 wait state

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Architecture for Low Power

Elegant architecture Deliver the performance needed with lower frequency and smaller area

Power reducing instructions Software controlled power-down via WAIT instructions Invokes SRAM sleep modes

High code density Instruction sets, microMIPS & MIPS16e Reduce system level memory and overall bus traffic

Registers & handshaking signals for system power control Fully static design

Allows on-the-fly changes

Fine-grain clock gating to reduce dynamic power Automatically shuts down unused logic Clock tree at root shuts down, wake up by external event

Voltage/Frequency scaling support Compatible with major DVFS IP

Low power EDA flow support Reference flow script support for all major EDA vendors physical

design tool chains.

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Power Consumption – M14K

38.7

11.3

180G

130 50

Target Freq (MHz)215 100 310 150

Power(mW)

1.20.34

30.7

6.3

130G

0.73 0.19

13.7

2.5

90G

280 100

0.30 0.08

8.1

2.75

65G

0.23 0.08

Speed Optimized

Area Optimized

Normal Mode Power(Dhrystone tight loop)

Speed Optimized

Area Optimized

Sleep Mode Power

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Architecture for Minimum Code Size

microMIPS ISA – Maintains MIPS32 assembly code structure

Complete Standalone ISA (Instruction Set Architecture) Combines 16- and 32-bit instructions in a single ISA Recoded MIPS32 & MIPS64 instructions Includes 15 new 32-bit and 39 new 16-bit instructions Frequent instructions and macros re-encoded to 16 bits

High Performance Code Size : >30% code size reduction; Functional : MIPS32 level performance; 1.48 DMIPS/MHz, 2.6 CoreMark/MHz

Compatibility Supports MIPS32 and MIPS64® architectures Supports co-existence with legacy MIPS32 decoder Supports all MIPS ASEs

Configurability microMIPS is build time configurable

Development Support SW & HW tools – software toolchain, compiler, debug probe 3rd party ecosystem – RTOS, OS, tools

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microMIPS Code Size Benchmarks

0%10%20%30%40%50%60%70%80%90%

100%

MIPS32 CSiBe Linux Kernel CoreMark Dhrystone

100%

65%73% 73% 70%

microMIPS code size reduction

MIPS32

microMIPS

0%

20%

40%

60%

80%

100%

100%

78%64% 69% 66% 65%

EEMBC v1.1

MIPS32

microMIPS

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MCU Application - Specific optional features

Reduced Interrupt Latency

Enhanced Interrupt Interface Vectored Interrupt & External Interrupt Controller modes with high number of inputs

Multiple Shadow Register Sets Multiple GPR’s for fast Interrupt service & context switching without save & restore

Atomic Bit Instructions Bit-set & Bit-clear for Read-Modify-Write semaphore manipulation.

Flash Access Accelerator Pre-fetch buffer scheme for slow memory access.

Parity Support for on-chip memory Increase system reliability if needed.

Enhanced Debug Capabilities Multiple program/data trace & profiling modes Low overhead, low cost EJTAG

DFT Coverage Compliant with ATPG Scan Test and Memory-BIST to achieve high test coverage

IRQnIRQn+1

10Cycles 7

Prologue ISRn Chaining ISRn+1 Epilogue

4

21 cycles total

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M14K Core Features

microMIPS & MIPS32 Instruction Decoder

5-stage Pipeline1.48 DMIPS/MHz

InstructionPre-fetch

Enhanced iFlowtracePC Sampling

Fast Debug Channel

AHB-Lite

Parity

Reduced latencyEnhanced

Vector/Priority

CorExtend/UDICo-Processor

Multiply DivideUnit

Low PowerAtomic Bit

Instructions

32 GPRsShadow Regs

RetainedFeatures

New/EnhancedFeatures

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M14K vs Cortex-M

•Best Performance

•High Code Compression at MIPS32

performance•Same software platform

•Maintains efficiency

•Best Real-Time Performance

•Fastest Interrupt Response

•Reduced Dev. Time•Fast Time to

Product

•Fast Code Execution•Scalable

•Uses std interfaces•Expandable

•Customizable

FEATURE MIPS M14K ARM Cortex-M3 ARM Cortex-M0Architecture Harvard Harvard Von NeumannPipeline stages 5 3 3

ISAMIPS32

microMIPS Thumb-2 Thumb

Thumb-2 (subset)Legacy 32-bit decoder Y - MIPS32 N NTotal instructions 300+ 155 56DMIPS Performance 1.48 DMIPS/MHz 1.25 DMIPS/MHz 0.9 DMIPS/MHzCoreMark Performance 2.36 1.76 1.6GPRs 32 16 13GPR sets (max) 16 1 1Interrupt control Y - int & ext Y - int NVIC 32Priority levels 8 4 4Interrupt latency 10 cycles 16 cycles 16 cyclesTailchaining Y Y YAtomic bit instructions Y Y NInstruction-only trace Y N NPC sampling Y N NPerfomance counter Y N NFast Debug Channel Y N NMultiply-Divide unit Y Y Multiply onlyLocal Code Ram (max) 4GB 1GB NoneLocal Data Ram (max) 4GB 1GB NoneParity Optional N NFast SRAM interface Y N NFlash memory prefetch Y N NMMU Y - FMT Optional OptionalExternal interface AHB-Lite AHB-Lite AHB-LiteCo-Processor interface Y N NCustom Instruction support Y N N

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Cores: MIPS vs. ARM

M14K can be configured to be equivalent to a Cortex-M3, M1 or M0. ‘3 cores-in-1’

With more features, more options Higher performance, more efficiency Lower power, smaller area Single development system Experience in design

> +

+

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Strategic Ecosystem for Success

Complementary IP and Enabling Technologies

Graphics

Video

Audio

VoIP

Foundries

Design Services

User Interfaces

Security

SoC IPEDA/ESL

Wireless Stacks

The right relationships to speed customers’ SoC development

Industry Orgs

RTOS/OS

Networks Development Tools

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MCU & Embedded Solutions Summary

Efficient Base Architecture

High Performance Small Size Low Power SRAM I/F MIPS32 Release 2 32 GPRs MDU CorExtend/UDI

Development SupportSG++ SysNav SEAD-3

Ecosystem

Reduced Latency microMIPS Flash accelerationAHB-Lite Cache controller TLB MMU Parity

Application-Specific Features

EJTAG iFlowtrace Fast Debug Channel

Debug / Profiling

© 2010 MIPS Technologies, Inc. All rights reserved It’s The Core & Much More …. Key Success...

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Transcript of © 2010 MIPS Technologies, Inc. All rights reserved It’s The Core & Much More …. Key Success...