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Transcript of soongsil - PLDWorld.comDigital IF Processing Baseband Modem 1000 MIPS ~ 50 ~ 1000 MIPS 1000 ~ 2000...
© 2002
How to Implement Digital IFHow to Implement Digital IF
2002. 11. 6School of Electronic EngineeringAdvanced Wireless Communication Systems Lab.Won Cheol Lee
2002. 11. 6School of Electronic EngineeringAdvanced Wireless Communication Systems Lab.Won Cheol Lee
ContentsContentsBackgroundSDR for beyond 3GWhat is Digital IF?ADC & DAC Technology for Digital IFFiltering Technology for Digital IF Digital IF based ChannelizationConclusion
SDR for Beyond 3G SDR for Beyond 3G
International Roaming
International Roaming
Core Technology for 4th Generation
Wireless Comm.
Core Technology for 4th Generation
Wireless Comm.
Horizontal and Vertical
Seamless Roaming
Horizontal and Vertical
Seamless Roaming
Multi-modeMulti-band
Multi-service
Multi-modeMulti-band
Multi-service
Microcell
WirelessAccess link
Evolution of Wireless Comm. SystemsEvolution of Wireless Comm. Systems
Definition of SDR TechnologyDefinition of SDR Technology
DAC
ADC
Network
Software
Processor
“The process of managing complexity whilst maximizing flexibility by using the techniques of non
real time software engineering in hard real time domain.”
Core Technologies for SDR (cont.)
Software
Technical Issues
AdaptabilityAdaptive
SignalProcessing
Features of Software Radio
Flexibility Multi-mode/Multi-band
High PerformanceDigital Signal Processing Devices
(DSP, FPGA, etc.)
Wideband/High speed/High Resolution ADC, DAC
Wideband RF
Software Download
Adaptive Receiving
Software Antenna
Flexible Antenna
Demodulation Technologyfor Multi-Modulation
Downsizing Technology
Low Power ConsumptionTechnology
DeviceTechnology
Signal ProcessingTechnology
ConfigurableDigital Logic
(FPGA) Fast andHigh
ResolutionADC, DAC
HighPerformance
DSP
ASICAlgorithm
SoftwareTechnique Signal Processing
Techniques withH/W Architecture
BasicTechnology
Multi Access / Multi Network Multi-band
PracticalTechnology
Core Technologies for SDR Core Technologies for SDR
Functionalities for SDR-based HandsetFunctionalities for SDR-based Handset
ADC DAC
DSP FPGA
LNA HPA
Mixer
Software-Specific Language
Application Program
Digital Reconfigurable
Processor
BroadbandRF Comp.
Radio Function Library
ADC
DAC
Modem
Download
Reconfigure
Driver, OS
GSM module
IS-95 CDMA module
IMT-2000 module
DAB module
4G module
Vendor 1
Vendor 2
Vendor 3
Vendor 4
Vendor 5
Middleware
APL
Digital IFProcessing
BasebandModem
1000 MIPS ~50 ~ 1000 MIPS
1000 ~ 2000 MIPS10 ~ 50 MIPS (Speech)
1000 MIPS (Video)
- FPGA- Programmable
Dedicated H/W
DSP (with Accelerator)
ChannelCodingSource
Coding
FPGA
Digital Hardware Resources for SDRDigital Hardware Resources for SDR
DSP (with Accelerator)
“More sophisticated signal processing algorithms must be employed to increase throughput over limited frequency resource”
Generic Structure of SDR PlatformGeneric Structure of SDR Platform
PEPE
Tok
en
mem
PE PE
PE
Token
mem
Token mem
Token mem
PEPE
Token mem
SW m
atri
x
PE PE
PE
S W m
atr i
x
SW matrix
SW matrix
FPGA
DSP
PE
SW matrix
kernel
kernel
kernel
kernel kernel
kernel
RF Front-end
DDCADC RF/IF
Antenna
DUCDAC
HierarchicalInterconnection
Network
Pµ
Enhancement of Radio Access by SDREnhancement of Radio Access by SDR
Core Network
HyperLAN2 HyperLAN2
UMTS UMTS
GSM GSM
IS-95 IS-95
SDR based Multimode
Base Station
Present Future
SDR-based Multimode BS and HandsetSDR-based Multimode BS and Handset
DOWNLOAD 1. SMA RTCard 2. Ethernet 3. OTA 4. USB :
Old Connection New Connection
SYSTEM 1. IS-95 2. WCDMA 3. WLAN
:
SERVICE 1. VOICE 2. AUDIO 3. MOVIE
:
I S-95 WCDMAf
WLAN
Multi-FA
4G Systmes
FA FA FA FA
IS-95 WCDMAf
WLAN
Multi-FA
FA FA FA FA
MultimodeBase Station
4G Systmes
Multi-BandMulti-Band
MultimodeHandset
MultimodeHandset
IS-95 W-CDMA
RFinRFout
1st IF Analog 2nd IF DigitalRF
Band Pass Filter
Band PassFilter
Analog LocalOSC
Analog LocalOSC
Digital LocalOSC
WidebandDAC
WidebandADC
Digital Interpolation & Decimation
Filter
DigitalAGC
Digital LocalOSC
Digital Decimation & Interpolation
Filter
Rx Filter Coefficients
Tx Filter Coefficients
ReconfigurableReconfigurable Platform (FPGA, DSP)Platform (FPGA, DSP)What is Digital IF? What is Digital IF?
Blocker Rejection and Digital AGCBlocker Rejection and Digital AGC
Signal
Blocker
RF Input Analog SAWfilter output
Analog AGCoutput
Digital filteroutput
Digital AGCoutput
Analog AGC Output Level
Digital AGC Output Level
Digital ProcessingAnalog Processing
Analog Attenuation
Digital Attenuation
Open Digital IF Architecture for BSOpen Digital IF Architecture for BS
AD
CD
AC
Fast
IP
Inte
rfac
e
RF Modules
Antenna
Feed
up
Tow
er
Open Interface allows third parties to supply just the
RF/amp modules
RTP/UDP/IPv6Digitised IF
Fast IPInterface SDRAM DSP
TCXO PLD FPGA
Iub/IP (Fast Ethernet)
IF card is a modification of the generic processing card design
Evolution of Digital RF/IF TechniqueEvolution of Digital RF/IF Technique
RT
DAC
& A
DC
Channel Selector
Channel SelectorBasebandProcessing IP/Network I/F
R
T
DAC
& A
DC
Channel Selector
Channel SelectorBasebandProcessing IP/Network I/F
RT
DAC
& A
DC
Channel Selector
Channel Selector1st IF
1st IF
BasebandProcessing IP/Network I/F
RT
2nd IF
2nd IF DAC
& A
DC
Channel Selector
Channel Selector1st IF
1st IF
BasebandProcessing IP/Network I/F
RF
RF
RF
RF
RF
RF
RF
RF/IF Type I
RF/IF Type II
RF/IF Type III
RF/IF Type IV
Advantages of Digital IFAdvantages of Digital IFMore digital components in Analog Front End
More digitally tunable components
More strong to adjacent co-channel interference
Easy to adapt sophisticated digital signal processing in IF
(eg., Adaptive pre-distorter, IF bandpass filtering, etc)
Easy to upgrade by software to fit released spec.
More robust to aging problem
Cost effective by reducing analog components
Components for implementing Digital IF Components for implementing Digital IF
ADC,DAC
Digital Filter & RAMFilter
Numerical OscillatorLocal Oscillator
Digital Multiplier & LUTMixer
Digital MultiplierAmplifier
Digital IFAnalog IF
Characterisitics of Analog-to-Digital ConverterCharacterisitics of Analog-to-Digital ConverterSampling Speed− As increasing
Processing bandwidth is widenedProcessing gain for baseband is increasedPower consumption is increased
− As decreasingPower consumption is decreased Suitable for handset with using Zero IF technique
Bit Resolution− It determines dynamic range of ADC (N bit ADC ~ 6*N [dB])− ENOB( Effective Number of Bits)
It is less than 6*N [dB] Dynamic Range due to harmonic noise
Analog Input Bandwidth− It should be greater than Nyquist Freq. for bandpass sampling
Considerations for ADC Circuit DesignConsiderations for ADC Circuit DesignInput center frequency is set to fNyquist /2 due to mitigate− 1/f Noise around DC − Image around fNyquist Isolation between analog input and digital circuit− Isolation between analog components and digital
components− Isolation between analog ground and digital ground
Input Clock for ADC should have− Very low noise − Be isolated with the clock for digital circuit− Be differential clock to alleviate noise
Performance of current and future ADCsPerformance of current and future ADCs
FeatureSemiconductor-Based Superconductor-Based
Performance Range
10 to 14 bits quoted (ENOB typically 2 to 4 less)
14 to 24 bits ENOB
Up to 200 MHz Up to > 2 GHz
60 to 90 dB 100 to 150 dB
N/A (normally post LNA) -120 to -180 dBm
Frequency
Resolution
Spur Free Dynamic Range
Sensitivity
Characterisitics of Digital-to-Analog ConverterCharacterisitics of Digital-to-Analog Converter
Sampling Speed− determines available output frequency
SFDR(Spur Free Dynamic Range)− determines output dynamic range with
considering Harmonic DistortionInverse Sinc Filter− is required for the flatness of inband frequency
characteristicImage Rejection Filter− Is required for unintentional harmonic image
Bandpass Sampling Technique (cont.)Bandpass Sampling Technique (cont.)
The technique of under-sampling a modulated signal to achieve frequency translation via
intentional aliasing.
The technique of under-sampling a modulated signal to achieve frequency translation via
intentional aliasing.
Bandpass SamplingBandpass Sampling
Sampling ConditionsSampling Conditions
20 I
IFBWF −<
22SI
IFFBWF <+
Bandpass Sampling Technique (cont.)Bandpass Sampling Technique (cont.)
IF frequency in information bandwidth which is occurred from folding can be determined from
sampling frequency Fs and center frequency Fa.
IF frequency in information bandwidth which is occurred from folding can be determined from
sampling frequency Fs and center frequency Fa.
Frequency Selection RuleFrequency Selection Rule
bby a ofdivision after remainder : b)(a,
aargument ofportion truncated: (a)frequency teintermedia
ADC tofrequency input where
),(),(
odd,even,
is2/
If
remfixFF
FFremFFFFremF
FFfix
IF
a
SaSIF
SaIF
s
a
==
−==
Bandpass Sampling Technique Bandpass Sampling Technique
fInformation
BandfInformation
Band
fInformationBand
Fs/2 3Fs/2Information
Band
Fs/2f
Signal after LNA Signal after LNA Signal after BPF Signal after BPF
Aliasing Effect due to FsAliasing Effect due to FsFolded IF frequencyFolded IF frequency
Bandpass Sampling for Multiband Signal Bandpass Sampling for Multiband Signal
Multiband signals resulted from folding effect should not be overlapped each other in information band.
Multiband signals resulted from folding effect should not be overlapped each other in information band.
Sampling ConditionSampling Condition
2|| 21
21
IIIFIF
BWBWFF
+≥−
Sample at Fs
Wanted signal #1 Wanted signal #2f
Fs/2 Fs/2 f
Bandpass Sampling for Multiband SignalBandpass Sampling for Multiband Signal
An Example : IS-95 and W-CDMAAn Example : IS-95 and W-CDMA
< Digital Board >
Sampling Freq. 40MHz
15MHz
5MHz175MHz
85MHz
FPGAADCsDAC
PCI INTERFACE
FPGAADCsDAC
PCI INTERFACE
PC
SIGNALGENERATOR
( IS-95 )
SIGNALGENERATOR( IMT-2000 )
S1
S2
S1 + S2
IMT-2000 Signal
IS-95 Signal
Fc=85MHz-10dBm
Fc=175MHz-10dBm
FPGAsDACADC
DACADC
Multimode Input (IS-95, W-CDMA, W-LAN)Multimode Input (IS-95, W-CDMA, W-LAN)Signals considered here− IS-95
Bandwidth : 1.25 MHz/1FAChip rate : 1.2288 Mcps
− W-CDMABandwidth : 5 MHz/1FAChip rate : 3.84 Mcps
− IEEE 802.11a W-LANEffective Bandwidth : 16.6MHzTransmission Bandwidth : 20 MHz
Total information bandwidth : 26.25 MHz
IF Freq. Plan for IS-95, W-CDMA, W-LANIF Freq. Plan for IS-95, W-CDMA, W-LANConditions
02lower
lowerBWF< −
2 2upper S
upper
BW FF + <
| |2
mid uppermid upper
BW BWF F
+− ≥| |
2mid lower
mid lowerBW BWF F +
− ≥
lowerF midF upperF0 / 2sF
lowerBW midBW upperBW
Selected IF Frequency PlansSelected IF Frequency PlansIF frequency band : 70~130 MHzSampling Frequency : 65 MHz
Digital Frequency (MHz)IF Frequency (MHz)
21491091267419431841269612263211810498235111071251192383881221272172109123128
W-LAN
W-CDMAIS-95W-
LANW-
CDMAIS-95
Digital IF Down ConversionDigital IF Down Conversion
A/D ⊗ LPF
Low Pass Filter Design (Decimation Filter);
CIC Filter + Half-Band Filter
sf sf
Tfje 02π
sf2/sf 2/3 sf0f
A/DIF
Digital Down ConversionBaseband
DigitalSignal
DecimationBy M
Mff ss /' =
NDecimation filter
Decimation Process N : Decimation ratio
Interpolation Process
InterpolationFilter
N
p : Interpolation ratio
Sampling rate
sf
Sampling rate
sf
Sampling rate
Nff s
s ='
sf
Nfs
2
'
2/sfNf s
2−
Sampling rate
ss fNf ⋅='
Nfs
2
'
−
Nfs
2
2/'sf '
sf
Decimation and Interpolation processDecimation and Interpolation process
Structure of CIC FilterStructure of CIC Filter
Decim
ate by R
4-stage Integrator Section
4-stage Comb Section
1−Z
Rate Expan
sion by R
Sample rate= Sample rate=sf Rfs /
Sample rate= sfSample rate= Rfs /
)(nx
)(nx
)(ny
)(ny
For Decimation
For Interpolation
1−Z 1−Z 1−Z
1−Z 1−Z 1−Z 1−Z
1−Z 1−Z 1−Z 1−Z
1−Z 1−Z 1−Z 1−Z
Decimation Filter using CIC & HB FilterDecimation Filter using CIC & HB Filter
16sf
sf
Rfs
CIC Filter R HB 2 HB 2 HB 2
CIC Filter R
sf16sf
16sf−
8
CIC FiltersfR
fs16R
fs16
−
8R
Rfs
Rfs2
R8
sfRfs
Rfs2
Rfs
16
11)(
1
0
1
kR
i
i
kR
z
zzzH
=
−−
=
∑−
=
−
−
−
Efficient FIR Filter Processing (cont.)Efficient FIR Filter Processing (cont.)
5:1 MUX
DATA_OUT(3x)
35bitACCUMULATORLatch
DATA_IN(15x)
sync
PP_CH#1Sync_IN
Sync_OUT
PP_CH#2Sync_IN
Sync_OUT
PP_CH#3Sync_IN
Sync_OUT
PP_CH#4Sync_IN
Sync_OUT
PP_CH#5Sync_IN
Sync_OUT
Polyphase Filter Bank Block
Efficient FIR Filter Processing Efficient FIR Filter Processing
SYNC_IN
DATA_IN(15x)
32bitACCUMULATOR
LOAD
SYNC_OUT
DATA_OUT(3x)
DATA_SYNCDEALY
(MultiplierLatency)
14x16Multiplier
24 x 16COEFROM
ADDR
DATATIMER
ADDR_A SYCN_OUT
ADDR_A ADDR_B
ADDR_COEF
24 x 14DPRAM
ADDR_A ADDR_B
DATA_A DATA_B
A_WR
PP_CH Block
SYNC_OUT
ADDR_A ADDR_B ADDR_COEF
SYNC_IN
4bit counterCE by SYNC
4bit counterReset by SYNC
Initial Value :0x7 4bit ADDER
4bit ADDER
CNTR_ACE
4bitREGISTER
CNTR_BRES
2 CLKDEALY
4bitREGISTER
4bitREGISTER
9
TIMER Block
Digital IF ChannelizerDigital IF Channelizer- Frequency Conversion- Analog Channel Selection
Analog
Analog
Analog
A/D Digital
Digital
Digital
CH 1
CH 2
CH N
Analog A/D Digital
- Frequency Conversion- Anti-alias Filtering
Software
Digital Channel Selection
Analog Channel Filter
Frequency
Conventional Multi-hardware Radio
Analog Channel Filter
Frequency
Digital Channel Filter
Software Defined Radio
A/D
A/D
Functionality of Digital IF Channelizer Functionality of Digital IF Channelizer
nK
kj
e
+
−4/12π
mje 2
π
)(mxk
A/D40Msps LPF K Re{ }
IF Signalx(t)
Sample Sequence
x(n)
FrequencySpectrum
FrequencyShift
#1 #2 #3 #4 #5 #6 #7 #8
1.25MHz
40/K 2.5 MHz
40/K 2.5 MHz
40/K 2.5 MHz
SSB Signal
FrequencyShift
1 2 3 4 5 6 7 8 8 7 6 5 4 3 2 1
#9 #10 #11 #12 #13 #14 #15 #16
FA
Subbands
FA2.5MHz
1.25MHz
20MHz
40MHz
Wanted FA Band : k=5, K=16 (Center Frequency is (k+1/4)*Fs/K )
#1 #2 #3 #4 #5 #6 #7 #8
Channelizer using Polyphase Filter BankChannelizer using Polyphase Filter Bank
The above models are equivalent.
PrototypeLowpass Filter )()()()()( 1
12
21
10
KK
KKKK zPzzPzzPzzPzH −+−−− ++++=
H(z)Sample
Sequencex(n)
SSB Signal
K Re{ }
nK
kj
e÷
+
− 4/12 π mje 2
π
)(0KzP
)(11 KzPz−
)(22 KzPz−
)(11 KK
K zPz −+−
Kn
Kkj
e÷
+
−4/12π
nK
kj
e÷
+
−4/12π
nK
kj
e÷
+
−4/12π
nK
kj
e÷
+
−4/12π
mje 2
π
DFTK
K
K
K
)(0 zP
)(1 zP
)(2 zP
)(1 zPK−
z-1
z-1
z-1
÷
−K
je 4
12π
÷
−K
je 4
22π
÷
−−KKj
e 412π
1
÷
−Kkj
eπ2
÷
−Kkj
e22π
÷
−−
KKkj
e)1(2π
1
Communicator
mj
mj
mj
mj
An Example : IS-95 and W-CDMAAn Example : IS-95 and W-CDMASampling Frequency : 80 MHzFA BW : 5MHzIS-95 : FA BW 1.25MHz
Multiband Channelizer for IS-95 & W-CDMAMultiband Channelizer for IS-95 & W-CDMACharacteristics :− Polyphase filter bank structure performed with low processing
clock− Each communicator is employed for each multi-FA standard.
nπfjelLFlF 121,1 )1()( −=
)(1,1 myM −
)(1,2 my
FAst10=n nπfjelLFlF 021,0 )0()( −=
nπfjM eMmMhmP 02
1,1 )1()( −−=−
nπfjemMhmP 021,2 )2()( −=
∑
nπfje 02−
FAnd2
FAth4
)(1,0 my
nπfjemMPmP 121,1 )1()( −=
)(1,1 my
)(1,1 myM −
)(1,2 my
FAst1
)(nx
0=n nπfjemMPmP 021,0 )0()( −=
nπfjM
MeMmMPmP 121,1 )1()( −−−=−
nπfjemMPmP 221,2 )2()( −=
∑
nπfje 02−
)(1 my
)(2 my)(10 my
FAnd2
FAth10
W-CDMA
IS-95)(1 ly
)(2 ly)(4 ly
W-CDMABaseband
Signal
IS-95Baseband
Signl
ConclusionsConclusionsFor future mobile communication systems, the development of multi-mode and multi-band SDR platform is necessary.For multi-mode and multi-band transceiver, the development of Digital IF technology is necessary.To realize multi-mode and multi-band SDR-based Digital IF module, reconfigurable RF devices and digital processors with high speed and low power consumption are required.More flexible and sophisticated digital signal processing algorithms must be employed onto SDR platform to improve the performance of future mobile communication systems.