Post on 19-Jan-2016
Review for Exam 2Using MUXs to implement logic
Using ROMs to implement logic
Timing Analysis
The internal structure of flip-flops
Flip-flop timings
Rising and falling edge triggered flip-flops
Counters and state machines
Generating next state equations from counter sequences.
Implementation using RS, D, T and JK flip-flops
Reading state sequence from timing diagrams
Determining next states from schematics
Moore vs. Mealy
Max frequency for a state machine
Verilog code
Implementing Logic Functions With Muxes
Implement:
Z = A’B + BC’
4-to-1MUX Z
A B
I0
I1
I2
I3
for AB=00, Z=0
0A B
C 00 01 11 10
0 0 1 1 0
1 0 1 0 0
Implementing Logic Functions With Muxes
Implement:
Z = A’B + BC’
4-to-1MUX Z
A B
I0
I1
I2
I3
0
for AB=01, Z=1
1
A B
C 00 01 11 10
0 0 1 1 0
1 0 1 0 0
Implementing Logic Functions With Muxes
Implement:
Z = A’B + BC’
4-to-1MUX Z
A B
I0
I1
I2
I3
0
1
for AB=11, Z=C’
C’
A B
C 00 01 11 10
0 0 1 1 0
1 0 1 0 0
Implementing Logic Functions With Muxes
Implement:
Z = A’B + BC’
4-to-1MUX Z
A B
I0
I1
I2
I3
0
1
C’
A B
C 00 01 11 10
0 0 1 1 0
1 0 1 0 0
0
Implementing Logic Functions With Muxes
An alternate method
4-to-1MUX Z
A B
I0
I1
I2
I3
0
1
C’
0
Z = A’B + BC’
A=0 B=0
A=0 B=1
A=1 B=0
A=1 B=1
Z = 1 0 + 0 C’ = 0
Z = 1 1 + 1 C’ = 1
Z = 0 0 + 0 C’ = 0
Z = 0 1 + 1 C’ = C’
Using a ROM For Logic
A B C F G H
0 0 00 0 10 1 00 1 11 0 01 0 11 1 01 1 1
Specify a truth table for a ROM which implements: F = AB + A’BC’
G = A’B’C + C’
H = AB’C’ + ABC’ + A’B’C
Using a ROM For Logic
A B C F G H
0 0 0 00 0 1 00 1 0 10 1 1 01 0 0 01 0 1 01 1 0 11 1 1 1
Specify a truth table for a ROM which implements: F = AB + A’BC’
G = A’B’C + C’
H = AB’C’ + ABC’ + A’B’C
Using a ROM For Logic
A B C F G H
0 0 0 0 10 0 1 0 10 1 0 1 10 1 1 0 01 0 0 0 11 0 1 0 01 1 0 1 11 1 1 1 0
Specify a truth table for a ROM which implements: F = AB + A’BC’
G = A’B’C + C’
H = AB’C’ + ABC’ + A’B’C
Using a ROM For Logic
Specify a truth table for a ROM which implements: F = AB + A’BC’
G = A’B’C + C’
H = AB’C’ + ABC’ + A’B’C
A B C F G H
0 0 0 0 1 00 0 1 0 1 10 1 0 1 1 00 1 1 0 0 01 0 0 0 1 11 0 1 0 0 01 1 0 1 1 11 1 1 1 0 0
Timing Analysis
X
A
B = 1
C = 1
D
E
F A
B
AB
E
C
D
CD
F
E+F
X
Timing Analysis
X
A
B = 1
C = 1
D
E
F A
B
AB
E
C
D
CD
F
E+F
X
Timing Analysis
X
A
B = 1
C = 1
D
E
F A
B
AB
E
C
D
CD
F
E+F
X
Timing Analysis
X
A
B = 1
C = 1
D
E
F A
B
AB
E
C
D
CD
F
E+F
X
Timing Analysis
X
A
B = 1
C = 1
D
E
F A
B
AB
E
C
D
CD
F
E+F
X
Timing Analysis
X
A
B = 1
C = 1
D
E
F A
B
AB
E
C
D
CD
F
E+F
X
Timing Analysis
X
A
B = 1
C = 1
D
E
F A
B
AB
E
C
D
CD
F
E+F
X
The internal structure of flip-flops
R
S
Q
Q’
GATE
GS
GRD
Q’
Q
GATE
D
CLK
Q
Q’
D-type Flip-Flop
The internal structure of flip-flops
T-type Flip-Flop
CLK
Q
Q’
T
The internal structure of flip-flops
JK-type Flip-Flop
CLK
Q
Q’
J
K
Flip-flop timingsClock-to-Q
D
CLK
Q
Q’
tCLK Q = tNOT + tAND + 2 x tNOR
CLK
D
Q
tCLK Q
time
Flip-flop timingsClock-to-Q
D
CLK
Q
Q’
tsetup = tNOT + tAND + 2 x tNOR
Flip-flop timingsSetup time
CLK
D
Q
tsetup
time
Flip-flop timingsSetup time
D
CLK
Q
Q’
thold = tNOT
Flip-flop timingsHold time
CLK
D
Q
thold = tNOT
time
Clock edge AND gate turns off, D can change
Flip-flop timingsHold time
Flip Flop Timing
CLK
D
Q
tsetup
thold
tCLK Q
time
D
CLK
Q
Q’
Falling Edge Triggered DFF
Rising and falling edge triggered flip-flops
Rising Edge Triggered DFF
D
CLK
Q
Q’
Rising and falling edge triggered flip-flops
Generating next state equations from counter sequences.
Desired count sequence = 00 01 00 10 11 00 …
If current state = 00, next state = ?????
Implemented count sequence = 000 001 100 110 011 000 …
Q2 Q1 Q0 N2 N1 N0
0 0 0 0 0 10 0 1 1 0 01 0 0 1 1 01 1 0 0 1 10 1 1 0 0 00 1 0 X X X1 0 1 X X X1 1 1 X X X
N2 = Q2 Q1’ + Q1’ Q0N1 = Q2N0 = Q2’ Q0’ + Q1 Q0’
Implementation using RS, D, T and JK flip-flops
N/A111
N/A011
1101
Set1001
0110
Reset0010
1100
No change000 0
CommentQ+QRS
N/A111
N/A011
1101
Set1001
0110
Reset0010
1100
No change000 0
CommentQ+QRS
0111
Toggle1011
1101
Set1001
0110
Reset0010
1100
No change000 0
CommentQ+QKJ
0111
Toggle1011
1101
Set1001
0110
Reset0010
1100
No change000 0
CommentQ+QKJ
0x11
1x01
x110
x00 0
KJQ+Q
0x11
1x01
x110
x00 0
KJQ+Q
011
101
110
00 0
TQ+Q
011
101
110
00 0
TQ+Q
011
101
110
00 0
Q+QT
011
101
110
00 0
Q+QT
Reading state sequence from timing diagrams
W
X
Y
Z
WXYZ = 0010, 0110, 0011, 0101, 1100, 1000, 1001, 1101, 1110, 0010
Determining next states from schematics
Q0
Q2
CLK
Q1
CLK
CLK
Q2
D Q
D Q
D Q
Q2
Q1’
Q1’
Q0
Q2’
Q0’
Q1
Q0’
Q2 Q1 Q0
0 0 0
0 0 1 1 0 0 1 1 0
Initial state
Moore vs. Mealy
Moore Mealy Outputs Function of Current
State Only Function of Current
State and Current I nputs Output Timing Outputs Available Af ter
Clock Transition (plus Gate Delays)
Outputs Available Anytime
(Af ter I nputs Stabilize) Delay Output Delayed One
Clock Cycle Output Available on Current Clock Cycle
Logic Requires more Requires less
Max frequency for a state machine
Steps: 1. Determine the delay through the Flip Flops
2. Determine the delay through the IFL (max)
3. Add in setup time
4. Determine the smallest clock period possible
5. Max frequency = 1------------------clock period
Structural Verilog Code
and (output, input1, input2, ……);
nand (output, input1, input2, ……);
or (output, input1, input2, ……);
nor (output, input1, input2, ……);
not (output, input1);
buf (output, input1);
xor (output, input1, input2, ……);
xnor (output, input1, input2, ……);
module mux21(q, sel, a, b);input sel, a, b;output q; wire selbar, a1, a2;
not(selbar, sel);and(a1, selbar, a);and(a2, sel, b);or(q, a1, a2);
endmodule
a
sela1
ba2
q
selbar
Structural Verilog Code example
Dataflow Verilog CodeOperator
TypeOperatorSymbol
OperationPerformed
# ofOperands Comments
Arithmetic *, /, +, - As expected 2
* and / take LOTS of hardware
% Modulo 2Logical ! Logic NOT 1 As in C
&& Logic AND 2 As in C|| Logic OR 2 As in C
Bitwise ~ Bitwise NOT 1 As in C& Bitwise AND 2 As in C| Bitwise OR 2 As in C^ Bitwise XOR 2 As in C~^ Bitwise XNOR 2
Relational <, >, <=, >= As expected 2 As in CEquality ==, != As expected 2 As in CReduction & Red. AND 1 Multi-bit input
~& Red. NAND 1 Multi-bit input| Red. OR 1 Multi-bit input~| Red. NOR 1 Multi-bit input^ Red. XOR 1 Multi-bit input~^ Red. XNOR 1 Multi-bit input
Shift << Left shift 2 Fill with 0's>> Right shift 2 Fill with 0's
Concat { } Concatenate Any numberReplicate { { } } Replicate Any numberCond ?: As expected 3 As in C
Dataflow Verilog Code example
module mux21(q, sel, a, b);input sel, a, b;output q;
assign q = (~sel & a) | (sel & b); endmodule
module mux21(q, sel, a, b);input sel, a, b;output q;
assign q = sel?b:a; endmodule
OR
Verilog Code Heirarchy
module mux41(q, sel, a, b, c, d);input[1:0] sel;input a, b, c, d;output q;wire tmp1, tmp2;
mux21 M0(tmp1, sel[0], a, b);mux21 M1(tmp2, sel[0], c, d);mux21 M2(q, sel[1], tmp1, tmp2);
endmodule
a
mux41
q
b c d
2sel
mux21mux21
mux21
sel[0]
sel[1]
a b c d
q
tmp1 tmp2