Lecture 11: Sequential Circuits

Introduction to

CMOS VLSI

Design

Lecture 11:

Sequential CircuitsDavid Harris, Harvey Mudd College

Kartik Mohanram and Steven Levitan

University of Pittsburgh

CMOS VLSI Design10: Sequential Circuits Slide 2

Outline

Floorplanning

Sequencing

Sequencing Element Design

Max and Min-Delay

Clock Skew

Time Borrowing

Two-Phase Clocking

Project Strategy

Proposal

– Specifies inputs, outputs, relation between them

Floorplan

– Begins with block diagram

– Annotate dimensions and location of each block

– Requires detailed paper design

Schematic

– Make paper design simulate correctly

Layout

– Physical design, DRC, NCC, ERC

Floorplan

How do you estimate block areas?

– Begin with block diagram

– Each block has

• Inputs

• Outputs

• Function (draw schematic)

• Type: array, datapath, random logic

Estimation depends on type of logic

MIPS Floorplan

datapath

2700 x 1050

(2.8 M2)

alucontrol

200 x 100

(20 k2)

zipper 2700 x 250

wiring channel: 30 tracks = 240

(4.6 M2)

bitslice 2700 x 100

control

1500 x 400

(0.6 M2)

10 I/O pads

10 I/O

Area Estimation

Arrays:

– Layout basic cell

– Calculate core area from # of cells

– Allow area for decoders, column circuitry

Datapaths

– Sketch slice plan

– Count area of cells from cell library

– Ensure wiring is possible

Random logic

– Compare complexity do a design you have done

MIPS Slice Plan

register file

ramslice

IR3...0

srcB srcA

memdatawritedata

pcimmediate

aluout

aluresult

srcBsrcAbitlines

44 24 93 93 93 93 93 44 24 52 48 48 48 48 16 86 93 93 93 9344 24 4424131 131 13139 39 39 39 160

Typical Layout Densities

Typical numbers of high-quality layout

Derate by 2 for class projects to allow routing and

some sloppy layout.

Allocate space for big wiring channels

Element Area

Random logic (2 metal layers) 1000-1500 2 / transistor

Datapath 250 – 750 2 / transistor

Or 6 WL + 360 2 / transistor

SRAM 1000 2 / bit

DRAM 100 2 / bit

ROM 100 2 / bit

Sequencing

Combinational logic

– output depends on current inputs

Sequential logic

– output depends on current and previous inputs

– Requires separating previous, current, future

– Called state or tokens

– Ex: FSM, pipeline

in out

clk clk clk

PipelineFinite State Machine

Sequencing Cont.

If tokens moved through pipeline at constant speed,

no sequencing elements would be necessary

Ex: fiber-optic cable

– Light pulses (tokens) are sent down cable

– Next pulse sent before first reaches end of cable

– No need for hardware to separate pulses

– But dispersion sets min time between pulses

This is called wave pipelining in circuits

In most circuits, dispersion is high

– Delay fast tokens so they don’t catch slow ones.

Sequencing Overhead

Use flip-flops to delay fast tokens so they move

through exactly one stage each cycle.

Inevitably adds some delay to the slow tokens

Makes circuit slower than just the logic delay

– Called sequencing overhead

Some people call this clocking overhead

– But it applies to asynchronous circuits too

– Inevitable side effect of maintaining sequence

Sequencing Elements

Latch: Level sensitive

– a.k.a. transparent latch, D latch

Flip-flop: edge triggered

– A.k.a. master-slave flip-flop, D flip-flop, D register

Timing Diagrams

– Transparent

– Opaque

– Edge-trigger

clk clk

Q (latch)

Q (flop)

Sequencing Elements

Latch: Level sensitive

– a.k.a. transparent latch, D latch

Flip-flop: edge triggered

– A.k.a. master-slave flip-flop, D flip-flop, D register

Timing Diagrams

– Transparent

– Opaque

– Edge-trigger

clk clk

Q (latch)

Q (flop)

Latch Design

Pass Transistor Latch

Latch Design

Pass Transistor Latch

+ Tiny

+ Low clock load

– Vt drop

– nonrestoring

– backdriving

– output noise sensitivity

– dynamic

– diffusion input

Used in 1970’s

Latch Design

Transmission gate

Latch Design

Transmission gate

+ No Vt drop

- Requires inverted clock D Q

Latch Design

Inverting buffer

+ Fixes either

Latch Design

Inverting buffer

+ Restoring

+ No backdriving

+ Fixes either

• Output noise sensitivity

• Or diffusion input

– Inverted output

Latch Design

Tristate feedback

Latch Design

Tristate feedback

+ Static

– Backdriving risk

Static latches are now essential

Latch Design

Buffered input

Latch Design

Buffered input

+ Fixes diffusion input

+ Noninverting

Latch Design

Buffered output

Latch Design

Buffered output

+ No backdriving

Widely used in standard cells

+ Very robust (most important)

- Rather large

- Rather slow (1.5 – 2 FO4 delays)

- High clock loading

Latch Design

Datapath latch

Latch Design

Datapath latch

+ Smaller, faster

- unbuffered input

Flip-Flop Design

Flip-flop is built as pair of back-to-back latches

Enable

Enable: ignore clock when en = 0

– Mux: increase latch D-Q delay

– Clock Gating: increase en setup time, skew

Symbol Multiplexer Design Clock Gating Design

Force output low when reset asserted

Synchronous vs. asynchronous

Synchro

nous R

Asynchro

nous R

reset reset

Set / Reset

Set forces output high when enabled

Flip-flop with asynchronous set and reset

setreset

Sequencing Methods

Flip-flops

2-Phase Latches

Pulsed Latches

clk clk

hase T

ranspare

Combinational Logic

Combinational

Combinational Logic

tnonoverlap

Half-Cycle 1 Half-Cycle 1

Timing Diagrams

Combinational

LogicA Y

clk clk

clkclk

tsetup t

tsetup

tpdLogic Prop. Delay

tcdLogic Cont. Delay

tpcqLatch/Flop Clk-Q Prop Delay

tccqLatch/Flop Clk-Q Cont. Delay

tpdqLatch D-Q Prop Delay

tpcqLatch D-Q Cont. Delay

tsetupLatch/Flop Setup Time

tholdLatch/Flop Hold Time

Contamination and

Propagation Delays

Max-Delay: Flip-Flops

clk clk

Combinational Logic

tsetup

sequencing overhead

pd ct T

Max-Delay: Flip-Flops

clk clk

Combinational Logic

tsetup

sequencing overhead

pd c pcqt T t t

Max Delay: 2-Phase Latches

Combinational

Logic 1

Combinational

Logic 2

Q2 Q3D1 D2 D3

sequencing overhead

pd pd pd ct t t T

Max Delay: 2-Phase Latches

Combinational

Logic 1

Combinational

Logic 2

Q2 Q3D1 D2 D3

sequencing overhead

2pd pd pd c pdqt t t T t

Max Delay: Pulsed Latches

Q1 Q2D1 D2

Combinational LogicL1

(a) tpw

> tsetup

(b) tpw

< tsetup

tsetup

sequencing overhead

max pd ct T

Max Delay: Pulsed Latches

Q1 Q2D1 D2

Combinational LogicL1

(a) tpw

> tsetup

(b) tpw

< tsetup

tsetup

sequencing overhead

max ,pd c pdq pcq pwt T t t t t

Min-Delay: Flip-Flops

cdt CL

Min-Delay: Flip-Flops

holdcd ccqt t t CL

Min-Delay: 2-Phase Latches

1, 2 cd cdt t CL

tnonoverlap

Hold time reduced by

nonoverlap

Paradox: hold applies

twice each cycle, vs.

only once for flops.

But a flop is made of

two latches!

Min-Delay: 2-Phase Latches

1, 2 hold nonoverlapcd cd ccqt t t t t CL

tnonoverlap

Hold time reduced by

nonoverlap

Paradox: hold applies

twice each cycle, vs.

only once for flops.

But a flop is made of

two latches!

Min-Delay: Pulsed Latches

cdt CL

Hold time increased

by pulse width

Min-Delay: Pulsed Latches

holdcd ccq pwt t t t CL

Hold time increased

by pulse width

Time Borrowing

In a flop-based system:

– Data launches on one rising edge

– Must setup before next rising edge

– If it arrives late, system fails

– If it arrives early, time is wasted

– Flops have hard edges

In a latch-based system

– Data can pass through latch while transparent

– Long cycle of logic can borrow time into next

– As long as each loop completes in one cycle

Time Borrowing Example

Combinational LogicCombinational

Borrowing time across

half-cycle boundary

Borrowing time across

pipeline stage boundary

hCombinational Logic

Combinational

Loops may borrow time internally but must complete within the cycle

How Much Borrowing?

Combinational Logic 1Q2D1 D2

Nominal Half-Cycle 1 Delay

tborrow

tnonoverlap

tsetup

borrow setup nonoverlap2cT

2-Phase Latches

borrow setuppwt t t

Pulsed Latches

Clock Skew

We have assumed zero clock skew

Clocks really have uncertainty in arrival time

– Decreases maximum propagation delay

– Increases minimum contamination delay

– Decreases time borrowing

Skew: Flip-Flops

clk clk

Combinational Logic

tsetup

setup skew

sequencing overhead

hold skew

pd c pcq

cd ccq

t T t t t

t t t t

Skew: Latches

Combinational

Logic 1

Combinational

Logic 2

Q2 Q3D1 D2 D3

sequencing overhead

1 2 hold nonoverlap skew

borrow setup nonoverlap skew

pd c pdq

cd cd ccq

t t t t t t

Tt t t t

2-Phase Latches

setup skew

sequencing overhead

hold skew

borrow setup skew

max ,pd c pdq pcq pw

cd pw ccq

t T t t t t t

t t t t t

t t t t

Pulsed Latches

Two-Phase Clocking

If setup times are violated, reduce clock speed

If hold times are violated, chip fails at any speed

In this class, working chips are most important

– No tools to analyze clock skew

An easy way to guarantee hold times is to use 2-

phase latches with big nonoverlap times

Call these clocks 1, 2 (ph1, ph2)

Safe Flip-Flop

In class, use flip-flop with nonoverlapping clocks

– Very slow – nonoverlap adds to setup time

– But no hold times

In industry, use a better timing analyzer

– Add buffers to slow signals if hold time is at risk

Summary

Flip-Flops:

– Very easy to use, supported by all tools

2-Phase Transparent Latches:

– Lots of skew tolerance and time borrowing

Pulsed Latches:

– Fast, some skew tol & borrow, hold time risk

Lecture 11: Sequential Circuits

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