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Outline Switch Logic

Dynamic Logic

Stack up

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Switch Logic Can implement Boolean formulas as networks of switches

Can build switches from MOS transistors— transmission

gates

Transmission gates do not amplify but have smaller

layouts

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Types of Switches

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Complementary N-MOS P-MOS

Behavior of n-type Switch n-type switch has source-drain voltage drop when

conducting:

conducts logic 0 perfectly

introduces threshold drop into logic 1

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n-type Switch Driving Static Logic Switch underdrives static gate, but gate restores logic

levels

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VDD

n-type Switch Driving Switch Logic Voltage drop causes next stage to be turned on weakly

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Behavior of Complementary Switch Complementary switch products full-supply voltages for

both logic 0 and logic 1:

n-type transistor conducts logic

p-type transistor conducts logic

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CMOS TG Electrical Model

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VA = VDD VB

How on is “on”? Assume VA = VDD then

TG Circuits: MUX

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TG Circuits: 4 to 1 MUX Multiplexers can easily

be done with TG

Never forget that TG are

bi-directional

Compact layout by

combining identical gates

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TG Circuits: XOR

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8 transistors

6 transistors

Switch Logic Advantage:

Can help save area and parasitics in some specialized

Disadvantages:

Is not universal

Many TG in series provoke large delays

Introduce hard-to-trace electrical problems

Charge Sharing

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Charge Sharing The most insidious electrical problem in switch networks

MOS transistors have parasistic capacitances at their

sources and drains thanks to the source/drain diffusion

Solution: design the switch network so that its output is

always driven by a power supply

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Charge Sharing

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Dynamic Logic Overview:

Domino

DCVSL

NORA

Zipper

Goal

You are familiar with dynamic logic gates and its different

families

You can handle the dynamic logic problems like charge

sharing and timing

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Tinkering with Logic Gates Things to like about CMOS gates:

Easy to translate logic to fets

Rail-to-rail switching

Good noise margins

No static power since fets are in cutoff

Sizing not critical to correct operation

Things not to like about CMOS gates:

N inputs 2N fets (i.e., one nfet and one pfet)

Large circuit area, especially for pfets

“Heavy” loading of inputs

Pfet’s are either large or slow relative to nfets

Series connections can get very slow Naser Mohammadzadeh 18

Tinkering with Logic Gates We can replace pfet pullup network with pseudo-NMOS

load (pfet with grounded gate) but

Dissipate static power when output is low

Have to make load fet small to ensure that VOL is low

enough to cut off nfets in next stage

Reduces static power consumption (good!)

Increases output rise time (bad!)

One alternative: Dynamic CMOS gates

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Static vs. Dynamic Circuits In static circuits at every point in time (except when switching)

the output is connected to either GND or VDD via a low

resistance path.

Dynamic circuits rely on the temporary storage of signal values

on the capacitance of high impedance nodes.

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Dynamic Gates

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Precharge Evaluation

Dynamic Gates

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Dynamic Gates Inputs must be stable before CLK goes high because once

output has been discharged it won’t go high again until

next cycle

For same reason, noise/glitches on inputs cannot exceed

nfet threshold, a much more stringent requirement than for

static CMOS gates

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Good News & Bad News The good news:

Dynamic gates are faster than static gates despite the extra

“evaluate” fet in the pull-down path because of the

reduction in selfloading and the elimination of the pullup

short-circuit current during the first part of the output

transition

The bad news:

Dynamic gates cannot be cascaded

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Cascading Problem

Solution: develop techniques that avoid races

CMOS Domino logic

CMOS NORA (no race) logic & CMOS Zipper logic Naser Mohammadzadeh 25

CMOS Domino Logic

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Precharge: high

Evaluate: falls (maybe)

Precharge: low

Evaluate: rises (maybe)

CMOS Domino Logic When CLK is low, dynamic node is precharged high

and buffer inverter output is low. Nfets in the next logic

block will be off.

When CLK goes high, dynamic node is conditionally

discharged and the buffer output will conditionally go

high. Since discharge can only happen once, buffer

output can only make one low-to-high transition

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CMOS Domino Logic When domino gates are cascaded, as each gate

“evaluates”, if its output rises, it will trigger the

evaluation of the next stage, and so on… like a line of

dominos falling. Like dominos, once the internal node

in a gate “falls”, it stays “fallen” until it is “picked up”

by the precharge phase of the next cycle. Thus many

gates may evaluate in one evaluation cycle.

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More Domino-Style Circuits Weak pfet “keeper” keeps dynamic node pulled high during

evaluate phase if it’s not being pulled down through nfets

gate is static in both clock phases.

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More Domino-Style Circuits “Latching” pfet acts like keeper above unless dynamic

node gets pulled down during evaluate phase. When buffer

output goes high it switches keeper off saving static

power. Good for leakage current problems...

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Note that you can put an even

number of static gates after the

inverter and before the next

domino gate.

Optimizing Domino Logic (I)

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Optimizing Domino Logic (I) Since domino gate outputs are low during the precharge

phase, gates which have only domino output nodes as

inputs don’t need the “evaluate” nfet since all the nfets in

the pulldown will be off anyway.

But remember: if evaluate nfet is removed, precharge will

“ripple” through cascaded gates just like evaluates do.

Maybe only remove for gates where nfet stack is tall (i.e.

resistive) enough that pullup will start to “win” anyway

before ripple reaches gates and turns off pulldowns.

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Optimizing Domino Logic (II)

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In domino logic circuits we want evaluatation phase to

happen as quickly as possible. We can size fets to optimize

evaluation phase speed.

Some designers also “grade” the sizes of the

nfets, smallest at the top (increase in R

offset by decrease in C)

CLK

Optimizing Domino Logic (II) If we make the nfet in the output inverter much smaller

than the pfet then

The load on the internal node decreases, and

The switching threshold of the inverter increases

Both effects make the gate evaluate sooner. If large >>

small, the gate delay can be cut almost in half! However,

the other edge is very slow, so ripple precharge is a

problem.

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A Few “Little” Difficulties “Charge sharing” between nodes in the pull-down network

and the dynamic node can unintentionally reduce the voltage

of the dynamic node enough to switch output buffer

The addition of the output inverter makes domino gates non-

inverting. One can often design around this limitation, but

some circuits cannot be implemented solely using domino

logic unless both polarities (true and complement) of the

inputs are available. If both polarities of inputs are available

then we can generate both polarities of internal signals with

two domino gates so subsequent stages will have both

polarities of their inputs available too Naser Mohammadzadeh 35

Charge Sharing (I) Suppose the dynamic node has been

discharged during the previous evaluate

cycle. Then during precharge, all the

intermediate nodes in the pull-down chain

will remain discharged while the dynamic

node is precharged. Calculate the voltage

on the dynamic node when CLK goes

high. When CLK goes high, the voltage

on the dynamic node goes to

36

31.1 3.3

3 6DD DD

CV v for V v

C C

which is low enough to switch the output

inverter.

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Charge Sharing Fortunately this situation is easily detected by CAD tools

and can be resolved by

Adding additional precharge devices to intermediate nodes

Increasing size of output buffer which will increase

capacitance of dynamic node (faster output buffer may

compensate for larger internal capacitance).

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Charge

Sharing

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Additional precharge

devices to eliminate

charge sharing problems

Domino Logic Design To convert to Domino-style design we need to create

schematic that uses non-inverting gates:

I. Look for CMOS gates followed by inverter

II. Use Demorgan’s Law to create non-inv gates

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Domino Logic Design

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Dual-rail Domino Logic Domino circuits that generate both polarities of output

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DCVS Logic DCVSL = differential cascade voltage switch logic

Static logic—consumes no dynamic power

Uses latch to compute output quickly

Requires true/complement inputs, produces

true/complement outputs

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DCVS Structure

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DCVS Operation Exactly one of true/complement pull-down networks will

complete a path to the power supply

Pull-down network will lower output voltage, turning on

other p-type, which also turns off p-type for node which is

going down

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DCVS Example

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CMOS NORA Logic (NP Domino)

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CMOS NORA Logic (NP Domino) If we turn a dynamic gate “upside down” and use pfets to

build the logic block, we get a logic gate that “precharges”

low and “discharges” high. By using these gates in an

alternating sequence with regular nfet dynamic gates we

can eliminate the race problem we had with nfet-only

dynamic gate sequences and hence we don’t need the

buffer inverter present in domino gates.

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CMOS NORA Logic (NP Domino) Removing the buffer is a mixed blessing

we may need it for drive reasons

we need it to keep compatibility with other domino gates

It makes NORA logic very susceptible to noise

since during the evaluate phase all information is stored

dynamically

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CMOS Zipper

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CMOS Zipper Similar architecture with CMOS NORA

The clock signals are different

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VDD + VTH,p

Domino Life Cycle

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Advantages of Dynamic Logic Smaller area than fully static gates

Smaller parasitic capacitances hence higher speed

Reliable operation if correctly designed. Concerns:

Charge sharing with dynamic nodes

Sub-threshold leakage currents in evaluation logic

Alpha particle immunity

Vdd/GND noise and resistance

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Pass Transistor Quiz

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VDD

A

A’ B’

B

Out

C’

C

C

C’ A

A’ B

B’

VDD

Out A B C

F A BVDD

VDD VDD

VDD-Vt

VDD

Vout=?

2out DD tV V V