Logic Gates and Introduction to Logic Families
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Transcript of Logic Gates and Introduction to Logic Families
KARMAVEER BHAURAO PATIL POLYTECHNIC,
SATARA
Rayat Shikshan Sanstha’s
Department Of Electronics And Telecommunication Engineering
Logic Gates & Introduction to Logic Families
05/03/2023 Amit Nevase 2
Principles of Digital Techniques
Amit NevaseLecturer,
Department of Electronics & Telecommunication Engineering, Karmaveer Bhaurao Patil Polytechnic, Satara
EJ3G Subject Code: 17320 Second Year Entc
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Objectives
The student will be able to:Understand basic digital circuits.Understand conversion of number systems.Implement combinational and sequential
circuits.Understand logic families, data converters
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Teaching & Examination Scheme
Two tests each of 25 marks to be conducted as per the schedule given by MSBTE.
Total of tests marks for all theory subjects are to be converted out of 50 and to be entered in mark sheet under the head Sessional Work (SW).
Teaching Scheme Examination Scheme
TH TU PR PAPERHRS TH PR OR TW TOTAL
03 -- 02 03 100 25# --- 25@ 150
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Module I – Number System
Introduction to digital signal, Advantages of Digital System over analog systems (8 Marks)Number Systems: Different types of number systems( Binary,
Octal, Hexadecimal ), conversion of number systems,Binary arithmetic: Addition, Subtraction, Multiplication, Division.Subtraction using 1’s complement and 2’s complement
Codes (4 Marks) Codes -BCD, Gray Code, Excess-3, ASCII codeBCD addition, BCD subtraction using 9’s and 10’ complement
(Numericals based on above topic).
05/03/2023 Amit Nevase 6
Module II – Logic Gates & Introduction to Logic Families
Logic Gates (8 Marks)Basic Gates and Derived GatesNAND and NOR as Universal GatesBoolean Algebra: Fundamentals of Boolean LawsDuality Theorem, De-Morgan’s TheoremNumericals based on above topic
Logic Families (8 Marks) Characteristics of Logic Families & Comparison between different
Logic FamiliesLogic Families such as TTL, CMOS, ECLTTL NAND gate – Totem Pole, Open CollectorCMOS Inverter
05/03/2023 Amit Nevase 7
Module III – Combinational Logic Circuits
Introduction (8 Marks)Standard representation of canonical forms (SOP & POS),
Maxterm and Minterm , Conversion between SOP and POS formsK-map reduction techniques upto 4 variables (SOP & POS form),
Design of Half Adder, Full Adder, Half Subtractor & Full Subtractor using k-Map
Code Converter using K-map: Gray to Binary Binary to Gray Code Converter (upto 4 bit)
IC 7447 as BCD to 7- Segment decoder driver IC 7483 as Adder & Subtractor, 1 Digit BCD AdderBlock Schematic of ALU IC 74181 IC 74381
05/03/2023 Amit Nevase 8
Module III – Combinational Logic Circuits
Necessity, Applications and Realization of following (8 Marks) Multiplexers (MUX): MUX TreeDemultiplexers (DEMUX): DEMUX Tree, DEMUX as DecoderStudy of IC 74151, IC 74155Priority Encoder 8:3, Decimal to BCD EncoderTristate Logic, Unidirectional & Bidirectional buffer ICs: IC 74244
and IC 74245
05/03/2023 Amit Nevase 9
Module IV – Sequential Logic Circuit
Sequential Circuits (12 Marks)Comparison between Combinational & Sequential circuitsOne bit memory cell: RS Latch- using NAND & NOR Triggering Methods: Edge & Level TriggeringFlip Flops: SR Flip Flop, Clocked SR FF with preset & clear,
Drawbacks of SR FFClocked JK FF with preset & clear, Race around condition in JK FF,
Master Slave JK FFD and T Flip FlopsExcitation Tables of Flip FlopsBlock schematic and function table of IC 7474, IC 7475, IC 74373
05/03/2023 Amit Nevase 10
Module IV – Sequential Logic Circuit Study of Counters (8 Marks)
Counter: Modulus of Counter, Types of Counters: Asynchronous & Synchronous Counters
Asynchronous Counter/Ripple Counter: 4 Bit Up/Down Counter Synchronous Counter: Excitation Tables of FFs, 3 Bit Synchronous
Counter, its truth table & waveformsBlock schematic and waveform of IC 7490 as MOD-N Counter
Shift Registers (4 Marks) Logic diagram, Truth Table and waveforms of 4 bit shift registers:
SISO, SIPO, PIPO, PISO 4 Bit Universial Shift RegistersApplications of Shift Registers (Logic Diagram & waveforms) of
Ring Counter and Twisted Ring Counter
05/03/2023 Amit Nevase 11
Module V – Data Converters
Introduction and Necessity of Code Converters (8 Marks)DAC Types & Comparison of weighted resistor type (Mathematical
Derivation) and R-2R Ladder Type DAC (Mathematical Derivation upto 3 variable)
ADC Types & Their Comparison (8 Marks) Single Slope ADC. Dual Slope ADC, SAR ADC IC PCF 8591: 8 Bit ADC-DAC
05/03/2023 Amit Nevase 12
Module VI – Memories
Principle of Operation & Classification of memory (10 Marks)Organization of memoriesRAM (Static & Dynamic), Volatile and Non-volatileROM (PROM, EPROM, EEPROM)Flash MemoryComparison between EEPROM & Flash
Study of Memory ICs Identification of IC number and their function of following ICs: IC
2716, IC 7481 and IC 6116
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Module-IILogic Gates & Introduction
to Logic Families
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Specific Objectives
Define Logic gates & logic families.Study of Boolean Algebra.Use of Boolean Laws for simplification.Develop logic for simple digital circuit.Define Logic Families.Different types and comparison between Logic
Families.
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Module II – Logic Gates & Introduction to Logic Families
Logic Gates (8 Marks)Basic Gates and Derived GatesNAND and NOR as Universal GatesBoolean Algebra: Fundamentals of Boolean LawsDuality Theorem, De-Morgan’s TheoremNumericals based on above topic
Logic Families (8 Marks) Characteristics of Logic Families & Comparison between different
Logic FamiliesLogic Families such as TTL, CMOS, ECLTTL NAND gate – Totem Pole, Open CollectorCMOS Inverter
05/03/2023 Amit Nevase 16
Basics…..
Logic gates are the fundamental building blocks
of digital systems.
The name logic gate is derived from the ability
of such devices to make decisions, in the sense
that it produces one output level when some
combinations of input levels are present
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Basics…..
Inputs & Outputs for Logic Circuits
Input & Output of logic gates can occur only in two levels.
HIGH LOW True False ON OFF 1 0
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Basics…..
Truth TableA table which lists all the possible combinations of
input variables and the corresponding outputs is called a “Truth Table”.
It shows how the logic circuits output responds to various combinations of logic levels at the inputs
Switches in parallel => ORSwitch 1 Switch 2 Output
OFF OFF OFF
OFF ON GLOW
ON OFF GLOW
ON ON GLOW
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Basics…..
Logic
A logic in which the voltage levels represent logic 1 and logic 0.
Level logic may be Positive or Negative.
A “Positive Logic” is the one which the higher of the two
voltage levels represents the logic 1 and the lower of the two
voltage level represents the logic 0.
A “Negative Logic” is the one which the lower of the two
voltage levels represents the logic 1 and the higher of the two
voltage level represents the logic 0.
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Basics…..
Logic
Positive Logic
Logic 0 (LOW)=0V
Logic 1 (HIGH)=+5V
Negative Logic
Logic 0 (LOW)=+5V
Logic 1 (HIGH)=0V
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Logic Gates
Logic Gates
Basic Gates Universal Gates Special Purpose Gates
AND GateOR GateNOT Gate
NAND Gate
NOR Gate
Ex-OR Gate
Ex-NOR Gate
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AND Gate
An AND gate has two or more inputs but only
one output.
The output assumes the logic 1 state, when
both inputs are at logic 1 state.
The output assumes the logic 0 state even if one
of its inputs is at logic 0 state.AB
Y=A.B
Logic Symbol
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Inputs Output
A B Y=A.BAB
Y=A.B0
00 0 0 0
AND Gate
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Inputs Output
A B Y=A.B
0 0 0AB
Y=A.B0
10
0 01
AND Gate
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Inputs Output
A B Y=A.B
0 0 0
0 1 0
AB
Y=A.B1
00
1 0 0
AND Gate
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Inputs Output
A B Y=A.B
0 0 0
0 1 0
1 0 0
AB
Y=A.B1
11
1 1 1
AND Gate
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Realization of AND Gate using Diode
D1
D2
+5V
R
OutputA
B
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Realization of AND Gate using Diode
D1
D2
+5V
R
Output = 0A = 0
B = 0
Case I: When A = 0 and B = 0
Inputs OutputA B Y=A.B0 0 0
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Realization of AND Gate using Diode
D1
D2
+5V
R
Output = 0A = 0
B = 1
Case II: When A = 0 and B = 1
Inputs OutputA B Y=A.B0 0 00 1 0+5V
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Realization of AND Gate using Diode
D1
D2
+5V
R
Output = 0A = 1
B = 0
Case III: When A = 1 and B = 0
Inputs OutputA B Y=A.B0 0 00 1 01 0 0
+5V
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Realization of AND Gate using Diode
D1
D2
+5V
R
Output = 1A = 1
B = 1
Case IV: When A = 1 and B = 1
Inputs OutputA B Y=A.B0 0 00 1 01 0 01 1 1
+5V
+5V
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Realization of AND Gate using Transistor
+5V
R
Output A
B
R
R
R
R
Q1
Q2 Q3
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Realization of AND Gate using Transistor
+5V
R
Output = 0 A
B R
R
R
R
Q1
Q2 Q3
Case I: When A = 0 and B = 0
Inputs OutputA B Y=A.B0 0 0
OFF
OFF ON+
-VBE>0.7
VBE<0.7
VBE<0.7
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Realization of AND Gate using Transistor
+5V
R
Output = 0 A
B R
R
R
R
Q1
Q2 Q3
Case II: When A = 0 and B = 1
Inputs OutputA B Y=A.B0 0 00 1 0
OFF
ON ON+
-
+5V +
-VBE>0.7 VBE>0.7
VBE<0.7
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Realization of AND Gate using Transistor
+5V
R
Output = 0 A
B R
R
R
R
Q1
Q2 Q3
Case III: When A = 1 and B = 0
Inputs OutputA B Y=A.B0 0 00 1 01 0 0
ON
OFF ON+
-
+5V+
-VBE>0.7
VBE>0.7VBE<0.7
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Realization of AND Gate using Transistor
+5V
R
Output = 1 A
B R
R
R
R
Q1
Q2 Q3
Case IV: When A = 1 and B = 1
Inputs OutputA B Y=A.B0 0 00 1 01 0 01 1 1
ON
ON OFF+
-
+5V+
-VBE>0.7
VBE>0.7 VBE<0.7
+5V
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3 - Input AND Gate
AB
Y1=A.BY=Y1.C =A.B.CC
ABC
Y=A.B.C
Input OutputY=A.B.C
A B C Y
0 0 0 0
0 0 1 0
0 1 0 0
0 1 1 0
1 0 0 0
1 0 1 0
1 1 0 0
1 1 1 1
3 – Input AND Gate using 2 – Input AND Gate
Symbol : 3 – Input AND Gate
Truth Table : 3 – Input AND Gate
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AND Gate IC – IC 7408 (Quad 2 I/P AND Gate)
This device contains four independent gates each of which performs the logic AND function.
Pin Configuration of IC 7408 Function Table of IC 7408
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Verification of AND Gate IC 7408
+5V
R 330Ω
Double check the pin numbers when working with ICs.
1 7
814
Verification of AND Gate IC 7408
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VCC
A
B
Verification of AND Gate IC 7408
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GND
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OR Gate
An OR gate has two or more inputs but only one
output.
The output assumes the logic 1 state, when
even if one of its inputs is in logic 1 state.
The output assumes the logic 0 state only when
both the inputs are in logic 0 state.A
BY=A+B
Logic Symbol
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Inputs Output
A B Y=A+BAB
Y=A+B0
00 0 0 0
OR Gate
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Inputs Output
A B Y=A+B
0 0 0AB
Y=A+B0
11
0 11
OR Gate
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Inputs Output
A B Y=A+B
0 0 0
0 1 1
AB
Y=A+B1
01
1 0 1
OR Gate
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Inputs Output
A B Y=A+B
0 0 0
0 1 1
1 0 1
AB
Y=A+B1
11
1 1 1
OR Gate
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Realization of OR Gate Using Diodes
D1
D2
R
OutputA
B
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Realization of OR Gate Using Diodes
D1
D2
R
Output =0A=0
B=0
Case I: When A = 0 and B = 0
Inputs OutputA B Y=A+B0 0 0
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Realization of OR Gate Using Diodes
D1
D2
R
Output = 1A=0
B=1
Case II: When A = 0 and B = 1
Inputs OutputA B Y=A+B0 0 00 1 1
+5V
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Realization of OR Gate Using Diodes
D1
D2
R
Output = 1A=1
B=0
Case III: When A = 1 and B = 0
Inputs OutputA B Y=A+B0 0 00 1 11 0 1
+5V
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Realization of OR Gate Using Diodes
D1
D2
R
Output = 1A=1
B=1
Case IV: When A = 1 and B = 1
Inputs OutputA B Y=A+B0 0 00 1 11 0 11 1 1
+5V
+5V
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Realization of OR Gate Using Transistors
+5V
R
Output
A
B
R
R
R
Q1 Q2 Q3
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Realization of OR Gate Using Transistors
+5V
R
Output = 0
A=0
B=0
R
R
R
Q1 Q2 Q3 Inputs OutputA B Y=A.B0 0 0
OFF
ON+
-VBE>0.7
VBE<0.7 OFFVBE<0.7
Case I: When A = 0 and B = 0
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Realization of OR Gate Using Transistors
+5V
R
Output = 1
A=0
B=1
R
R
R
Q1 Q2 Q3 Inputs OutputA B Y=A.B0 0 00 1 1
OFF
ON+
-VBE>0.7VBE<0.7 OFFVBE<0.7
Case II: When A = 0 and B = 1
+5V
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Realization of OR Gate Using Transistors
+5V
R
Output = 1
A=1
B=0
R
R
R
Q1 Q2 Q3 Inputs OutputA B Y=A.B0 0 00 1 11 0 1
OFFON+
-VBE>0.7 VBE<0.7 OFFVBE<0.7
Case III: When A = 1 and B = 0
+5V
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Realization of OR Gate Using Transistors
+5V
R
Output = 1
A=1
B=1
R
R
R
Q1 Q2 Q3 Inputs OutputA B Y=A.B0 0 00 1 11 0 11 1 1
ON+
-VBE>0.7 OFFVBE<0.7
Case IV: When A = 1 and B = 1
+5V ONVBE>0.7
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Three Input OR Gate
A
B
Y1=A+B Y=Y1+C =A+B
C
ABC
Input OutputY=A+B+C
A B C Y
0 0 0 0
0 0 1 1
0 1 0 1
0 1 1 1
1 0 0 1
1 0 1 1
1 1 0 1
1 1 1 1
3 – Input OR Gate using 2 – Input OR Gate
Symbol : 3 – Input OR Gate
Truth Table : 3 – Input OR Gate
Y=A+B+C
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OR Gate IC – IC 7432 (Quad 2 I/P OR Gate)
This device contains four independent gates each of which performs the logic OR function
Pin Configuration of IC 7432 Function Table of IC 7432
05/03/2023 Amit Nevase 59
NOT Gate (Inverter)
A NOT gate, also called inverter, has only one input
and of course only one output.
It is a device whose output is always the
complement of its input.
That is, the output of a NOT gate assumes the logic 1
state when its input is in logic 0 state and vice versa.
A Y A
Logic Symbol
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NOT Gate
A
0 1Y A
Input Output
A Y A
10
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NOT Gate
A1 0
Y A
Input Output
A
0 1
Y A
1 0
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Realization of NOT Gate using Transistor
+5V
Output
A R
R
Q1
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Realization of NOT Gate using Transistor
+5V
Output= 1
A=0 R
R
Q1
Input Output
A
0 1
Y A
OFFVBE<0.7
Case I: When A = 0
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Realization of NOT Gate using Transistor
+5V
Output= 0
A=1 R
R
Q1
Input Output
A
0 1
1 0
Y A
ONVBE>0.7
Case II: When A = 1
+5V
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NOT Gate IC – IC 7404 (Hex Inverters)
This device contains six independent inverters
Pin Configuration of IC 7404Function Table of IC 7404
05/03/2023 Amit Nevase 66
Module II – Logic Gates & Introduction to Logic Families
Logic Gates (8 Marks)Basic Gates and Derived GatesNAND and NOR as Universal GatesBoolean Algebra: Fundamentals of Boolean LawsDuality Theorem, De-Morgan’s TheoremNumericals based on above topic
Logic Families (8 Marks) Characteristics of Logic Families & Comparison between different
Logic FamiliesLogic Families such as TTL, CMOS, ECLTTL NAND gate – Totem Pole, Open CollectorCMOS Inverter
05/03/2023 Amit Nevase 67
Universal Gates (NAND and NOR Gate)
NAND and NOR gates are Universal Gates.
Both NAND and NOR gates can perform all the
three basic logic functions (AND, OR and NOT).
Therefore, AOI logic can be converted to NAND
logic or NOR logic
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NAND Gate
NAND means NOT AND i.e. AND output is inverted.
So NAND gate is a combination of an AND gate and a
NOT gate.
A
B.A BAB .A B
A
B
NAND GateAND Gate NOT Gate
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NAND Gate
The output is logic 0 level, only when all the
inputs are logic 1 level.
For any other combination of inputs, the output
is a logic 1 level.
AB
.Y A B
Logic Symbol
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NAND Gate
Inputs Output
A BAB
0
01 0 0 1.Y A B
.Y A B
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NAND Gate
Inputs Output
A B
0 0 1AB
0
11
0 11
.Y A B.Y A B
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NAND Gate
Inputs Output
A B
0 0 1
0 1 1
AB
1
01
1 0 1
.Y A B.Y A B
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NAND Gate
Inputs Output
A B
0 0 1
0 1 1
1 0 1
AB
1
10
1 1 0
.Y A B.Y A B
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Realization of NAND Gate using Transistor
+5V
R
Output A
B
D1
R
Q1
D2
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3 - Input NAND Gate
AB
. .Y A BCC
INPUT OUTPUT
A B C Y
0 0 0 1
0 0 1 1
0 1 0 1
0 1 1 1
1 0 0 1
1 0 1 1
1 1 0 1
1 1 1 0
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NAND Gate IC – IC 7400 (Quad 2 I/P NAND Gate)
This device contains four independent gates each of which performs the logic NAND function.
Pin Configuration of IC 7400 Function Table of IC 7400
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NOR Gate
NOR means NOT OR i.e. OR output is inverted.
So NOR gate is a combination of an OR gate and
a NOT gate.
NOR Gate
AB
Y A B
OR Gate
AB
A B
NOT Gate
A B
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NOR Gate
The output is logic 1 level, only when all the
inputs are logic 0 level.
For any other combination of inputs, the output
is a logic 0 level.
Logic Symbol
AB
Y A B
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NOR Gate
Inputs Output
A BAB
0
01 0 0 1Y A B
Y A B
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NOR Gate
Inputs Output
A B
0 0 1AB
0
10
0 01
Y A B
Y A B
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NOR Gate
Inputs Output
A B
0 0 1
0 1 0
AB
1
00
1 0 0
Y A B
Y A B
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NOR Gate
Inputs Output
A B
0 0 1
0 1 0
1 0 0
AB
1
10
1 1 0
Y A B
Y A B
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Realization of NOR Gate using Transistor
+5V
R
Output
A
B
R
R
Q1 Q2
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3 – Input NOR Gate
AB
Y A B C
C
INPUT OUTPUT
A B C Y
0 0 0 1
0 0 1 0
0 1 0 0
0 1 1 0
1 0 0 0
1 0 1 0
1 1 0 0
1 1 1 0
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NOR Gate IC – IC 7402 (Quad 2 I/P NOR Gate)
This device contains four independent gates each of which performs the logic NOR function.
Pin Configuration of IC 7402 Function Table of IC 7402
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Universal Gate
NOT Gate using NAND Gate
A .Y A A
A Y A
......... (A.A=A)Y A
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Universal Gate
AND Gate using NAND Gate
A 1 .Y A B
B . Y A B
. ( =A ) Y A B A
AB
Y=A.B
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Universal Gate
OR Gate using NAND Gate
A
B
1Y A
2Y B
. Y A B
( Demorgan's Theorem) Y A B Y A B
A
BY=A+B
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Universal Gate
NOR Gate using NAND Gate
A
B
1Y A
2Y B
3 .Y A B
Y A B
3Y A B
AB
Y A B
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Universal Gate
NOT Gate using NOR Gate
A Y A A
A Y A
......... (A+A=A)Y A
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Universal Gate
OR Gate using NOR Gate
A 1Y A B
B Y A B
( =A ) Y A B A
A
BY=A+B
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Universal Gate
AND Gate using NOR Gate
A
B
1Y A
2Y B
+ Y A B
. ( Demorgan's Theorem) Y A B . Y AB
AB
Y=A.B
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Universal Gate
NAND Gate using NOR Gate
A
B
1Y A
2Y B
3 +Y A B
.Y A B
3 .Y A B
AB
.Y A B
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Why NAND Logic or NOR Logic?
IC Type Gates Gate / IC # ICs
74LS04 1 6 1
74LS08 2 4 1
74LS32 1 4 1
Total Number of ICs → 3
IC Type Gates Gate / IC # ICs
74LS02 7 4 2
Total Number of ICs → 2
AOI Logic NOR Logic
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Special Purpose Gate – Ex-OR Gate
An Ex-OR gate is two input, one output logic circuit.
The output assumes the logic 1 state, when one and
only one of its two inputs assumes a logic 1 state.
Under the conditions when both the inputs assume
the logic 0 state or logic 1 state, the output assumes
logic 0.
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Ex-OR Gate
If input variables are represented by A and B
and the output variable by Y the representation
for the output of this gate is as
AB
Y A B
Y AB AB
Logic Symbol Logic Expression
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Ex-OR Gate
Inputs Output
A BAB
0
00 0 0 0
Y A B Y A B
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Ex-OR Gate
Inputs Output
A B
0 0 0AB
0
11
0 11
Y A B Y A B
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Ex-OR Gate
Inputs Output
A B
0 0 0
0 1 1
AB
1
01
1 0 1
Y A B Y A B
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Ex-OR Gate
Inputs Output
A B
0 0 0
0 1 1
1 0 1
AB
1
10
1 1 0
Y A B Y A B
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3 – Input Ex-OR Gate
AB Y A B C
AB
C
A B
Y A B C
INPUT OUTPUT
A B C
0 0 0 0
0 0 1 1
0 1 0 1
0 1 1 0
1 0 0 1
1 0 1 0
1 1 0 0
1 1 1 1
Y A B C
C
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Ex-OR Gate IC – IC 7486 (Quad 2 I/P Ex-OR Gate)
This device contains four independent gates each of which performs the logic XOR function.
Pin Configuration of IC 7486 Function Table of IC 7486
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Special Purpose Gate – Ex-NOR Gate
An Ex-NOR gate is two input, one output logic
circuit.
The output assumes a logic 0 state, when one of
the input assumes a logic 0 state and other a logic 1
state.
The output assumes a logic 1 state only when both
the inputs assume a logic 0 state or when both the
inputs assume a logic state.
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Ex-NOR Gate
If input variables are represented by A and B and
the output variable by Y the representation for
the output of this gate is as
AB
Y A B
Y AB AB
Logic Symbol Logic Expression
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Ex-NOR Gate
Inputs Output
A BAB
0
01 0 0 1
Y A B Y A B
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Ex-NOR Gate
Inputs Output
A B
0 0 1AB
0
10
0 01
Y A B Y A B
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Ex-NOR Gate
Inputs Output
A B
0 0 1
0 1 0
AB
1
00
1 0 0
Y A B Y A B
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Ex-NOR Gate
Inputs Output
A B
0 0 1
0 1 0
1 0 0
AB
1
11
1 1 1
Y A B Y A B
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3 – Input Ex-NOR Gate
AB
C
A B
Y A B C
INPUT OUTPUT
A B C
0 0 0 1
0 0 1 0
0 1 0 0
0 1 1 1
1 0 0 0
1 0 1 1
1 1 0 1
1 1 1 0
Y A B C
CY A B C
AB
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Ex-NOR Gate IC – IC 74266
This device contains four independent gates each of which performs the logic XNOR function.
Pin Configuration of IC 74266
05/03/2023 Amit Nevase 111
Module II – Logic Gates & Introduction to Logic Families
Logic Gates (8 Marks)Basic Gates and Derived GatesNAND and NOR as Universal GatesBoolean Algebra: Fundamentals of Boolean LawsDuality Theorem, De-Morgan’s TheoremNumericals based on above topic
Logic Families (8 Marks) Characteristics of Logic Families & Comparison between different
Logic FamiliesLogic Families such as TTL, CMOS, ECLTTL NAND gate – Totem Pole, Open CollectorCMOS Inverter
05/03/2023 Amit Nevase 112
Boolean Algebra
Boolean Algebra is used to analyze and simplify
the digital (Logic) circuit.
Since it uses only the binary numbers i.e. 0 and
1 it is also called as “Binary Algebra” or “Logical
Algebra”.
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The rules of Boolean Algebra are different from
those of the conventional algebra.
It is invented by George Boole in the year 1854.
Boolean Algebra
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Boolean Algebra
Axioms
Axioms or postulates of Boolean algebra are set of
logical expressions that we accept without proof and
upon which we can build a set of useful theorems.
Actually, axioms are nothing more than the
definitions of the three basic logic operations that
we have already discussed AND, OR and INVERT.
05/03/2023 Amit Nevase 115
Axioms AND Operation
Axiom 1: 0 . 0 = 0Axiom 2: 0 . 1 = 0Axiom 3: 1 . 0 = 0Axiom 4: 1 . 1 = 1
Boolean Algebra
05/03/2023 Amit Nevase 116
Axioms OR Operation
Axiom 5: 0 + 0 = 0Axiom 6: 0 + 1 = 1Axiom 7: 1 + 0 = 1Axiom 8: 1 + 1 = 1
Boolean Algebra
05/03/2023 Amit Nevase 117
Axioms NOT Operation
Axiom 9: Axiom 10:
1 0
0 1
Boolean Algebra
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Inversion Law (or Complementation Law)The term complement means to invert i.e. to
change 0’s to 1’s and 1’s to 0’s.Law 1: Law 2:Law 3: If A=0, then Law 4: If A=1, then
Law 5: (Double Inversion Law)
0 1
1 0
1A
0A
A A
Boolean Algebra
05/03/2023 Amit Nevase 119
AND Laws Law 1: A . 0 = 0 Null LawLaw 2: A . 1 = A Identity LawLaw 3: A . A = ALaw 4: = 0.A A
Boolean Algebra
05/03/2023 Amit Nevase 120
OR Laws Law 1: A + 0 = A Null LawLaw 2: A + 1 = 1 Identity LawLaw 3: A + A = ALaw 4: = 1A A
Boolean Algebra
05/03/2023 Amit Nevase 121
Commutative Laws
Law 1: A+B = B+A
This Law states that, A OR B is the same as B OR A i.e.
the order in which the variables are ORed is
immaterial.
This means that it makes no difference which input of
an OR gate is connected to A and which to B.
Boolean Algebra
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Proof: A+B B+A
Inputs Output
A B Y=A+B
0 0 0
0 1 1
1 0 1
1 1 1
AB
Inputs Output
B A Y=B+A
0 0 0
0 1 1
1 0 1
1 1 1
A
B
Boolean Algebra
05/03/2023 Amit Nevase 123
Commutative Laws
This law can be extended to any number of variables. For example,
A+B+C = B+C+A = C+A+B = B+A+C
Boolean Algebra
05/03/2023 Amit Nevase 124
Commutative Laws
Law 2: A.B = B.A
This Law states that, A AND B is the same as B AND
A i.e. the order in which the variables are ANDed is
immaterial.
This means that it makes no difference which input
of an AND gate is connected to A and which to B.
Boolean Algebra
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Proof: A.B B.A
Inputs Output
A B Y=A.B
0 0 0
0 1 0
1 0 0
1 1 1
AB
Inputs Output
B A Y=B.A
0 0 0
0 1 0
1 0 0
1 1 1
AB
Boolean Algebra
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Commutative Laws
This law can be extended to any number of variables. For example,
A.B.C = B.C.A = C.A.B = B.A.C
Boolean Algebra
05/03/2023 Amit Nevase 127
Associative Laws
Law 1: (A+B)+C = A+(B+C)
A OR B ORed with C is the same as A ORed with B
OR C.
This law states that the way the variables are
grouped and ORed is immaterial.
Boolean Algebra
05/03/2023 Amit Nevase 128
Proof: (A+B)+C A+(B+C)
AB A
B
A B C A+B (A+B)+C
0 0 0 0 0
0 0 1 0 1
0 1 0 1 1
0 1 1 1 1
1 0 0 1 1
1 0 1 1 1
1 1 0 1 1
1 1 1 1 1
A B C B+C A+(B+C)
0 0 0 0 0
0 0 1 1 1
0 1 0 1 1
0 1 1 1 1
1 0 0 0 1
1 0 1 1 1
1 1 0 1 1
1 1 1 1 1
C C
Boolean Algebra
05/03/2023 Amit Nevase 129
Associative Laws
This law can be extended to any number of variables. For example,
A+(B+C+D) = (A+B+C)+D = (A+B)+(C+D)
Boolean Algebra
05/03/2023 Amit Nevase 130
Associative Laws
Law 2: (A.B).C = A.(B.C)
A AND B ANDed with C is the same as A ANDed with
B AND C.
This law states that the way the variables are
grouped and ANDed is immaterial.
Boolean Algebra
05/03/2023 Amit Nevase 131
Proof: (A.B).C A.(B.C)
AB A
B
A B C A.B (A.B).C
0 0 0 0 0
0 0 1 0 0
0 1 0 0 0
0 1 1 0 0
1 0 0 0 0
1 0 1 0 0
1 1 0 1 0
1 1 1 1 1
A B C B.C A.(B.C)
0 0 0 0 0
0 0 1 0 0
0 1 0 0 0
0 1 1 1 0
1 0 0 0 0
1 0 1 0 0
1 1 0 0 0
1 1 1 1 1
C C
Boolean Algebra
05/03/2023 Amit Nevase 132
Associative Laws
This law can be extended to any number of variables. For example,
A.(B.C.D) = (A.B.C).D = (A.B).(C.D)
Boolean Algebra
05/03/2023 Amit Nevase 133
Distributive Laws
Law 1: A(B+C) = AB+AC
This law states that ORing of several variables and
ANDing the result with a single variable is equivalent
to ANDing that single variable with each of the
several variables and then ORing the products.
Boolean Algebra
05/03/2023 Amit Nevase 134
Proof: A.(B+C) AB+AC
ABB
A B C B+C A(B+C)
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 1 0
1 0 0 0 0
1 0 1 1 1
1 1 0 1 1
1 1 1 1 1
A B C AB AC AB+AC
0 0 0 0 0 0
0 0 1 0 0 0
0 1 0 0 0 0
0 1 1 0 0 0
1 0 0 0 0 0
1 0 1 0 1 1
1 1 0 1 0 1
1 1 1 1 1 1
C
C
A
A
Boolean Algebra
05/03/2023 Amit Nevase 135
Distributive Laws
This law can be extended to any number of variables. For example,
ABC(D+E) = ABCD + ABCE
AB(CD+EF) = ABCD +ABEF
Boolean Algebra
05/03/2023 Amit Nevase 136
Distributive Laws Law 2: A+BC = (A+B).(A+C)
This law states that ANDing of several variables and
ORing the result with a single variable is equivalent
to ORing that single variable with each of the several
variables and then ANDing the products.
Boolean Algebra
05/03/2023 Amit Nevase 137
Proof: A+(B.C) (A+B).(A+C)
ABB
A B C BC A+BC
0 0 0 0 0
0 0 1 0 0
0 1 0 0 0
0 1 1 1 1
1 0 0 0 1
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1
A B C A+B A+C (A+B)(A+C)
0 0 0 0 0 0
0 0 1 0 1 0
0 1 0 1 0 0
0 1 1 1 1 1
1 0 0 1 1 1
1 0 1 1 1 1
1 1 0 1 1 1
1 1 1 1 1 1
C
C
A
A
Boolean Algebra
05/03/2023 Amit Nevase 138
Redundant Literal Rule Law 1:
This law states that ORing of variable with the
AND of the complement of that variable with
another variable, is equal to the ORing of the two
variables
A AB A B
Boolean Algebra
05/03/2023 Amit Nevase 139
Proof:
B
A B
0 0 0 0
0 1 1 1
1 0 0 1
1 1 0 1
A
A AB
A B
A B A+B
0 0 0
0 1 1
1 0 1
1 1 1
A AB
A AB
A BA
BAB
AB
Boolean Algebra
05/03/2023 Amit Nevase 140
Redundant Literal Rule Law 2:
This law states that ANDing of variable with the OR
of the complement of that variable with another
variable, is equal to the ANDing of the two variables
( ) .A A B A B
Boolean Algebra
05/03/2023 Amit Nevase 141
Proof:
B
A B
0 0 1 0
0 1 1 0
1 0 0 0
1 1 1 1
A
( )A A B
.A B
A B A.B
0 0 0
0 1 0
1 0 0
1 1 1
.A BA
BA B
A B
A( )A A B
( )A A B
Boolean Algebra
05/03/2023 Amit Nevase 142
Idempotence Laws Law 1:
Idempotence means the same value
If A=0, then A.A = 0.0 = 0 = A
If A=1, then A.A = 1.1 = 1 = A
This law states that ANDing of a variable with itself is
equal to that variable only.
.A A AAA
A
Boolean Algebra
05/03/2023 Amit Nevase 143
Idempotence Laws Law 2:
Idempotence means the same value
If A=0, then A+A = 0+0 = 0 = A
If A=1, then A+A = 1+1 = 1 = A
This law states that ORing of a variable with itself is equal to
that variable only.
A A A
AA
A
Boolean Algebra
05/03/2023 Amit Nevase 144
Absorption Laws Law 1:
This law states that ORing of a variable with AND of that
variable and another variable is equal to that variable
itself.
Therefore,
A + A. Any Term = A
.A A B A
Boolean Algebra
05/03/2023 Amit Nevase 145
Proof:
A B
0 0 0 0
0 1 0 0
1 0 0 1
1 1 1 1
.A A B A
.A A B
A AB A AB
AB
.A B
A
Boolean Algebra
05/03/2023 Amit Nevase 146
Absorption Laws Law 2:
This law states that ANDing of a variable with OR of
that variable and another variable is equal to that
variable itself.
Therefore,
A . (A + Any Term) = A
( )A A B A
Boolean Algebra
05/03/2023 Amit Nevase 147
Proof:
A B
0 0 0 0
0 1 1 0
1 0 1 1
1 1 1 1
( )A A B A
( )A A B
( )A A B A AB
A B
A
A B
Boolean Algebra
05/03/2023 Amit Nevase 148
Module II – Logic Gates & Introduction to Logic Families
Logic Gates (8 Marks)Basic Gates and Derived GatesNAND and NOR as Universal GatesBoolean Algebra: Fundamentals of Boolean LawsDuality Theorem, De-Morgan’s TheoremNumericals based on above topic
Logic Families (8 Marks) Characteristics of Logic Families & Comparison between different
Logic FamiliesLogic Families such as TTL, CMOS, ECLTTL NAND gate – Totem Pole, Open CollectorCMOS Inverter
05/03/2023 Amit Nevase 149
De-Morgan’s Theorem First Theorem:
This theorem states that the complement of a sum of variables
is equal to the product of their individual complements.
What it means is that the complement of two or more
variables ORed together, is the same as the AND of the
complements of each of the individual variables
.A B A B
Boolean Algebra
05/03/2023 Amit Nevase 150
Proof: Logic Diagram L.H.S.
R.H.S.
A
B
A B
A
A BA
BA B
B
A
B
.A B
A
B.A B
NOR Gate
Bubbled AND Gate
Boolean Algebra
05/03/2023 Amit Nevase 151
Proof: Logic Table
A B
0 0 0 1
0 1 1 0
1 0 1 0
1 1 1 0
A B
0 0 1 1 1
0 1 1 0 0
1 0 0 1 0
1 1 0 0 0
A B A B A
B
.A B
A B .A B
Boolean Algebra
05/03/2023 Amit Nevase 152
De-Morgan’s Theorem
This law can be extended to any number of variables. For example,
......... . . . ........A B C D A B C D
......... (AB).(CD).(EFG)........AB CD EFG
Boolean Algebra
05/03/2023 Amit Nevase 153
De-Morgan’s Theorem Second Theorem:
This theorem states that the complement of a product of variables is equal to the sum of their individual complements.
What it means is that the complement of two or more variables ANDed together, is the same as the OR of the complements of each of the individual variables
.A B A B
Boolean Algebra
05/03/2023 Amit Nevase 154
Proof: Logic Diagram L.H.S.
R.H.S.
A
B
.A B
A
.ABA
B.A B
B
A
B
A B
A
BA B
NAND Gate
Bubbled OR Gate
Boolean Algebra
05/03/2023 Amit Nevase 155
Proof:
A B
0 0 0 1
0 1 0 1
1 0 0 1
1 1 1 0
A B
0 0 1 1 1
0 1 1 0 1
1 0 0 1 1
1 1 0 0 0
.A B .A B A
B
A B
.A B A B
Boolean Algebra
05/03/2023 Amit Nevase 156
De-Morgan’s Theorem
This law can be extended to any number of variables. For example,
. . . ......... ............A BC D A B C D
( )( )( )......... AB CD EFG ........AB CD EFG
Boolean Algebra
05/03/2023 Amit Nevase 157
Module II – Logic Gates & Introduction to Logic Families
Logic Gates (8 Marks)Basic Gates and Derived GatesNAND and NOR as Universal GatesBoolean Algebra: Fundamentals of Boolean LawsDuality Theorem, De-Morgan’s TheoremNumericals based on above topic
Logic Families (8 Marks) Characteristics of Logic Families & Comparison between different
Logic FamiliesLogic Families such as TTL, CMOS, ECLTTL NAND gate – Totem Pole, Open CollectorCMOS Inverter
05/03/2023 Amit Nevase 158
Duality
Duality represents relation between
expressions in positive logic system and
expression in negative logic system.
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The distinction between positive and negative
logic system is important.
An OR gate in positive logic system becomes an
AND gate in negative logic system and vice
versa.
Positive & negative logics thus give rise to a
basic duality in all Boolean identities.
Duality
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When changing from one logic system to
another 0 becomes 1 and 1 becomes 0.
Furthermore, an AND gate becomes an OR gate
and an OR gate becomes AND gate.
Duality
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Given Boolean identity, we can produce a dual
identity by changing all ‘+’ signs to ‘.’ signs, all ‘.’
signs to ‘+’ signs and complementing all 0’s and
1’s.
The variables are not complemented in this
process.
Duality
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Examples of Dual Identities
Sr. No. Given Expression Dual
1
2
3
4
5
6
0 1
1 0
0.1 0 1 0 1
0.0 0 1 1 1
1.1 1 0 0 0
A.0 0 1 1A A.1 A 0A A
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Sr. No. Given Expression Dual
7
8
9
10
11
12
13
. .A B B A A B B A
.( . ) ( . ).A BC AB C ( ) ( )A B C A B C
.( ) . .A B C A B AC ( )( )A BC A B A C
.(A )A B A A AB A
.(A. ) .A B AB AA B A B
.A B A B
.A B A B
(A )(A C) ( )(A C)B A B
A AC ACB AB
Examples of Dual Identities
05/03/2023 Amit Nevase 164
Module II – Logic Gates & Introduction to Logic Families
Logic Gates (8 Marks)Basic Gates and Derived GatesNAND and NOR as Universal GatesBoolean Algebra: Fundamentals of Boolean LawsDuality Theorem, De-Morgan’s TheoremNumericals based on above topic
Logic Families (8 Marks) Characteristics of Logic Families & Comparison between different
Logic FamiliesLogic Families such as TTL, CMOS, ECLTTL NAND gate – Totem Pole, Open CollectorCMOS Inverter
05/03/2023 Amit Nevase 165
Example 1
Reduce the following Boolean Expression using Boolean Laws:
. . . .AB A B A B A B
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Example 1
Reduce the following Boolean Expression using Boolean Laws:
. . . .AB A B A B A B
. . . .A B A B AB A B
. . . .A B A B A B A B
.( ) ( ) ( 1)A B B A B B B B ( 1)A A A A
1
. . . . 1AB A B A B A B
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Example 2
Reduce the following Boolean Expression using Boolean Laws:
ABC ABC ABC
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Example 2
Reduce the following Boolean Expression using Boolean Laws:
ABC ABC ABC
ABC ABC ABC
( )ABC BC A A ( A+A=1)ABC BC
( ) C AB B ( )( ) ( Distributive Law)C B A B B ( ) ( 1)C B A B B AC BC
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Example 3
Realize Y=AB+AC using one OR gate and one AND gate
05/03/2023 Amit Nevase 170
Example 3
Realize Y=AB+AC using one OR gate and one AND gate
Y AB AC
A.C is one product term Hence requires 1 AND gate
A.B is one product term Hence requires 1 AND gate
A.C & A.B is one sum term Hence requires 1 OR gate
Hence to implement Y=AB+AC equation we require 2 AND gates and 1 OR gate
But we have to use only 1 AND gate and 1 OR gate
Hence simplification is necessary
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Example 3 Continue……..
Y AB AC ( )Y A B C
BC
A
B C
( )Y A B C
Y AB AC
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Example 4
Prove that:
A AB A B
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Example 4
Prove that:
A AB A B
L.H.S A AB (1)A AB
(1 )A B AB
A AB AB
( )A B A A ( 1)A B A A
L.H.S R.H.S
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Example 5
Prove that:( )( )A B A B A
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Example 5
Prove that:( )( )A B A B A
L.H.S ( )( )A B A B
AA AB AB BB
0 ( AA=A, BB=0)A AB AB ( )A A B B
( 1)A A B B ( )A A A A
L.H.S R.H.S
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Example 6
With the help of Boolean Laws, Prove that:( )( ). 0A B AB A B AB
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Example 6
With the help of Boolean Laws, Prove that:( )( ). 0A B AB A B AB
L.H.S R.H.S
L.H.S.=( )( ).A B AB A B AB
=( )( )A B AB AAB ABB
=( ).(0) ( A.A=0, B.B=0)A B AB 0
Amit Nevase 178
Example 7
05/03/2023
With the help of Boolean Laws, Prove that:
AB AB AB A B
Amit Nevase 179
Example 7
05/03/2023
With the help of Boolean Laws, Prove that:
AB AB AB A B
L.H.S R.H.S
L.H.S. AB AB AB
AB AB AB
( )A B B AB
( 0)A AB B B ( )( ) ( ( )( ))A A A B A AB A A A B 1.( ) ( 1)A B A A A B
Amit Nevase 180
Example 8
05/03/2023
Simplify; F XY XYZ XYZ X ZY
Amit Nevase 181
Example 8
05/03/2023
Simplify; F XY XYZ XYZ X ZY
F XY XYZ XYZ X ZY
( XYZ+XYZ=XYZ)XY XYZ X ZY (1 )XY Z Z
( 1 1)XY Z Z XY
Amit Nevase 182
Example 9
05/03/2023
Prove that; AB ABC AB A
Amit Nevase 183
Example 9
05/03/2023
Prove that; AB ABC AB A
. . .L H S AB ABC AB
(1 )AB C AB
( 1 1)AB AB C ( ) A B B
( 1)A B B L.H.S R.H.S
05/03/2023 Amit Nevase 184
Module II – Logic Gates & Introduction to Logic Families
Logic Gates (8 Marks)Basic Gates and Derived GatesNAND and NOR as Universal GatesBoolean Algebra: Fundamentals of Boolean LawsDuality Theorem, De-Morgan’s TheoremNumericals based on above topic
Logic Families (8 Marks) Characteristics of Logic Families & Comparison between different
Logic FamiliesLogic Families such as TTL, CMOS, ECLTTL NAND gate – Totem Pole, Open CollectorCMOS Inverter
05/03/2023 Amit Nevase 185
Logic Families
IC Chip Manufacturing Process
05/03/2023 Amit Nevase 186
Logic Families
Small Scale Integration (SSI)
Medium Scale Integration (MSI)
Large Scale Integration (LSI)
Very Large Scale Integration (VLSI)
Ultra Large Scale Integration (ULSI)
Giant Scale Integration (GSI)
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Logic Families
Gate/transistor ratio is roughly 1/10
– SSI < 12 gates/chip
– MSI < 100 gates/chip
– LSI …1K gates/chip
– VLSI …10K gates/chip
– ULSI …100K gates/chip
– GSI …1Meg gates/chip
05/03/2023 Amit Nevase 188
Moore’s Law
A prediction made by Moore (a co-founder of Intel)
in 1965: “… a number of transistors to double every
2 years.”
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Transistor as Switch
both FETs and bipolar transistors make good switches
neither form produce ideal switches and their
characteristics are slightly different
both forms of device take a finite time to switch and
this produces a slight delay in the operation of the
gate
this is termed the propagation delay of the circuit
05/03/2023 Amit Nevase 190
FET as a Logical Switch
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FET as a Logical Switch
Rise and fall times because the waveforms are not perfectly square we
need a way of measuring switching times
we measure the rise time, tr and fall time, tf as
shown below
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Bipolar Transistor as Logical Switch
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when the input voltage to a bipolar transistor is high the
transistor turns ON and the output voltage is driven down to its
saturation voltage which is about 0.1 V
however, saturation of the transistor results in the storage of
excess charge in the base region
this increases the time taken to turn OFF the device – an effect
known as storage time
this makes the device faster to turn ON than OFF
some switching circuits increase speed by preventing the
transistors from entering saturation
Bipolar Transistor as Logical Switch
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Timing considerations all gates have a certain propagation delay time,
tPD this is the average of the two switching times
)t(tt PLHPHLPD 21
Bipolar Transistor as Logical Switch
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We have seen that different devices use
different voltages ranges for their logic levels
They also differ in other characteristics
In order to assure correct operation when gates
are interconnected they are normally produced
in families
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Logic Families
The electronic components used in the construction of the basic
circuit are usually used as the name of the technology. The
following are the most popular:
– RTL resistor-transistor logic
– DTL diode-transistor logic
– TTL transistor-transistor logic (widespread, standard)
– ECL emitter-coupled logic (high speed)
– MOS, PMOS, NMOS metal-oxide semiconductor (high component
density)
– CMOS complementary metal-oxide semiconductor (low power
consumption)
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Logic Families - I
The entire range of digital ICs is fabricated using either bipolar devices or MOS devices or a combination of the two.
Bipolar families:Diode logic (DL). (obsolete)Resistor transistor logic (RTL). (obsolete)Diode transistor logic (DTL). (obsolete)Transistor Transistor logic (TTL).Emitter Coupled Logic (ECL), also known as Current Mode
Logic(CML). Integrated Injection logic (I2L). (obsolete)
05/03/2023 Amit Nevase 198
Logic Families - II
MOS families:
PMOS family (using P-channel MOSFETs)
The NMOS family (using N-channel MOSFETs)
The CMOS family (using both N- and P-channel
devices).
The Bi-MOS logic family uses both bipolar and MOS
devices.
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Before going to study of Different logic families,
one look towards different terms &
characteristics of logic families.
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Module II – Logic Gates & Introduction to Logic Families
Logic Gates (8 Marks)Basic Gates and Derived GatesNAND and NOR as Universal GatesBoolean Algebra: Fundamentals of Boolean LawsDuality Theorem, De-Morgan’s TheoremNumericals based on above topic
Logic Families (8 Marks) Characteristics of Logic Families & Comparison between
different Logic FamiliesLogic Families such as TTL, CMOS, ECLTTL NAND gate – Totem Pole, Open CollectorCMOS Inverter
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Characteristics of Logic Families
Threshold Voltage
Threshold voltage is defined as that voltage at
the input of a gate which causes a change in the
state of the output from one logic level to the
other
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Propagation Delay
A pulse through a gate takes a certain amount of
time to propagate from input to output. This interval
of time is known as the “Propagation Delay” of the
gate. It is the average transition delay time ,
expressed as
Characteristics of Logic Families
2PDLH PDHL
pdt tt
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Propagation Delay
Characteristics of Logic Families
TPD,HL – input-to-output propagation delay from HI to LO outputTPD,LH – input-to-output propagation delay from LO to HI output
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Power Dissipation
Every logic gate draws some current from the
supply for its operation. The current drawn in HIGH
state is different from that drawn in LOW state. The
power dissipation, of a logic gate is the power
required by the gate to operate with 50% duty cycle at
a specified frequency and is expressed in milliwatts.
Characteristics of Logic Families
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Power Dissipation The power dissipation of a gate is given by,
Where, is the gate supply voltage is the average current drawn from the supply by the entire IC. is the number of gates in IC
Characteristics of Logic Families
(avg)CC CCDV XIP
n
CCV (avg)CCI
n
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Current Output Definitions
Sourcing means that the current flows out of
the terminal.
Sinking means that the current flows into the
terminal.
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Circuit Behavior for R Load
An output must sink current from a load when the output is in the LOW state.
An output must source current to a load when the output is in the HIGH state.
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Current Designations
Sourcing currents are designated as negative.
Sinking currents are designated as positive.
Sign is disregarded in fan out calculations.
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Characteristics of Logic Families
Fan In
The fan in of a logic gate is defined as the
number of inputs that the gate is designed to
handle.
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Fan Out
The fan out (also called the loading factor) of a
logic gate is defined as the maximum number of
standard loads that the output of the gate can
drive without impairing its normal operation.
Characteristics of Logic Families
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Concept of Fan In & Fan Out
Current Sourcing in HIGH state Current Sinking in LOW state
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The driving gate sinks current when it is in LOW
state and sources current when it is in HIGH
state.
HIGH state fan out =(max)OHI
IHI
LOW state fan out =(max)OLI
ILI
Concept of Fan In & Fan Out
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Characteristics of Logic Families
Voltage Parameters
HIGH Level Input Voltage:
It is the minimum voltage level required at the input of a
gate for that input to be treated as a logic 1. Any voltage
below this level will not be accepted as a logic 1 by the logic
circuit.
It is designated as, (MIN)IHV
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Voltage Parameters
HIGH Level Output Voltage:
It is the minimum voltage level required at the
output of a gate for that output to be treated as a logic
1. Any voltage below this level will not be accepted as a
logic 1 output by the logic circuit.
It is designated as, (MIN)OHV
Characteristics of Logic Families
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Voltage Parameters
LOW Level Input Voltage:
It is the maximum voltage level that can be treated
as logic 0 at the input of the gate. Any voltage above this
level will not be treated as a logic 0 input by the logic
gate.
It is designated as, (MAX)ILV
Characteristics of Logic Families
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Voltage Parameters
LOW Level Output Voltage:
It is the maximum voltage level that can be treated as
logic 0 at the output of the gate. Any voltage above this
level will not be treated as a logic 0 output by the logic
gate.
It is designated as, (MAX)OLV
Characteristics of Logic Families
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Current Parameters
HIGH Level Input Current:
The current that flows into an input when a
specified HIGH level voltage is applied to that input.
It is designated as, IHI
Characteristics of Logic Families
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Current Parameters
LOW Level Input Current:
The current that flows into an input when a
specified LOW level voltage is applied to that input.
It is designated as, ILI
Characteristics of Logic Families
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Current Parameters
HIGH Level Output Current:
The current that flows an output in a logic 1 state
under specified load conditions.
It is designated as, OHI
Characteristics of Logic Families
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Current Parameters
LOW Level Output Current:
The current that flows an output in a logic 0 state
under specified load conditions.
It is designated as, OLI
Characteristics of Logic Families
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Concept of Voltage & Current Parameters
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Noise Margin
When the digital circuits operate in noisy
environment the gates may malfunction if the noise
is beyond certain limits. The noise immunity of a
logic circuit refers to the circuits ability to tolerate
noise voltages at its inputs. A quantitative measure
of noise immunity is called “Noise Margin”
Characteristics of Logic Families
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Noise Margin
HI state noise margin:VNH = VOH(min) – VIH(min)
LO state noise margin:VNL = VIL(max) – VOL(max)
Noise margin:VN = min(VNH,VNL)
Characteristics of Logic Families
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Operating Temperatures
The range specified:
- for commercial applications is to
- for industrial applications is to
- for military applications is to
00 C 070 C
00 C 085 C
055 C 0125 C
Characteristics of Logic Families
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Speed Power Product
A common means for measuring and comparing
the overall performance of an IC family is the speed
power product, which is obtained by multiplying the
gate propagation delay by the gate power
dissipation. A low value of speed power product is
desirableSpeed-power product: TPD Pavg
Characteristics of Logic Families
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Module II – Logic Gates & Introduction to Logic Families
Logic Gates (8 Marks)Basic Gates and Derived GatesNAND and NOR as Universal GatesBoolean Algebra: Fundamentals of Boolean LawsDuality Theorem, De-Morgan’s TheoremNumericals based on above topic
Logic Families (8 Marks) Characteristics of Logic Families & Comparison between
different Logic FamiliesLogic Families such as TTL, CMOS, ECLTTL NAND gate – Totem Pole, Open CollectorCMOS Inverter
05/03/2023 Amit Nevase 227
Comparison
Parameter CMOS TTL ECL
Basic gate NAND/NOR NAND OR/NOR
Fan-out >50 10 25
Power per gate (mW) 1 @ 1 MHz 1 - 22 4 - 55
Noise immunity Excellent Very good Good
tPD (ns) 1 - 200 1.5 – 33 1 - 4
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Module II – Logic Gates & Introduction to Logic Families
Logic Gates (8 Marks)Basic Gates and Derived GatesNAND and NOR as Universal GatesBoolean Algebra: Fundamentals of Boolean LawsDuality Theorem, De-Morgan’s TheoremNumericals based on above topic
Logic Families (8 Marks) Characteristics of Logic Families & Comparison between different
Logic FamiliesLogic Families such as TTL, CMOS, ECLTTL NAND gate – Totem Pole, Open CollectorCMOS Inverter
05/03/2023 Amit Nevase 229
DL Logic
Diode Logic (DL)
Simplest; does not scale
NOT not possible (need an active element)
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Diode AND Gate- Example of DL Logic
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RTL Logic
Resistor-Transistor Logic (RTL) replace diode switch with a transistor switch
can be cascaded
large power draw
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NOR Gate- Example of RTL Logic
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DTL Logic
Diode-Transistor Logic (DTL) essentially diode logic with transistor amplification
reduced power consumption
faster than RTL
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NAND Gate- Example of DTL Logic
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TTL Logic Family
Transistor-transistor logic (TTL)
based on bipolar transistors
one of the most widely used families for small- and medium-
scale devices – rarely used for VLSI
typically operated from 5V supply
typical noise immunity about 1 – 1.6 V
many forms, some optimised for speed, power, etc.
high speed versions comparable to CMOS (~ 1.5 ns)
low-power versions down to about 1 mW/gate
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TTL Logic Levels & Noise Margins
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2 Input TTL NAND Gate
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Multiemitter Transistor
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Totem Pole Output
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Advantages of Totem Pole Configuration
Changes state faster than open-collector
outputs.
No external components are required.
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Open Collector
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TTL Subfamilies
Legacy: don’t use in new designs
Widely used today
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TTL Subfamilies
TTL Series Prefix Example Standard TTL 74 7486 High-speed TTL 74H 74H86 Low-power TTL 74L 74L86 Schottky TTL 74S 74S86 Low-power Schottky TTL 74LS 74LS86 Advanced Schottky TTL 74AS 74AS86 Advanced Low-power Schottky TTL 74ALS 74ALS86
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Module II – Logic Gates & Introduction to Logic Families
Logic Gates (8 Marks)Basic Gates and Derived GatesNAND and NOR as Universal GatesBoolean Algebra: Fundamentals of Boolean LawsDuality Theorem, De-Morgan’s TheoremNumericals based on above topic
Logic Families (8 Marks) Characteristics of Logic Families & Comparison between different
Logic FamiliesLogic Families such as TTL, CMOS, ECLTTL NAND gate – Totem Pole, Open CollectorCMOS Inverter
05/03/2023 Amit Nevase 245
ECL Logic Family
Emitter-coupled logic (ECL)
based on bipolar transistors, but removes problems of
storage time by preventing the transistors from saturating
very fast operation - propagation delays of 1ns or less
high power consumption, perhaps 60 mW/gate
low noise immunity of about 0.2-0.25 V
used in some high speed specialist applications, but now
largely replaced by high speed CMOS
05/03/2023 Amit Nevase 246
ECL Logic Family
Emitter-Coupled Logic (ECL)
PROS: Fastest logic family available (~1ns)
CONS: low noise margin and high power dissipation
Operated in emitter coupled geometry (recall differential
amplifier or emitter-follower), transistors are biased and
operate near their Q-point (never near saturation!)
Logic levels. “0”: –1.7V. “1”: –0.8V
Such strange logic levels require extra effort when
interfacing to TTL/CMOS logic families.
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2 – Input ECL OR/NOR Gate
-5.2V
OR Output
A B
Q1BQ2
Q3
Q1A
Q4
NOR Output
-1.3V
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Module II – Logic Gates & Introduction to Logic Families
Logic Gates (8 Marks)Basic Gates and Derived GatesNAND and NOR as Universal GatesBoolean Algebra: Fundamentals of Boolean LawsDuality Theorem, De-Morgan’s TheoremNumericals based on above topic
Logic Families (8 Marks) Characteristics of Logic Families & Comparison between different
Logic FamiliesLogic Families such as TTL, CMOS, ECLTTL NAND gate – Totem Pole, Open CollectorCMOS Inverter
05/03/2023 Amit Nevase 249
CMOS Logic Family
Complementary metal oxide semiconductor (CMOS)
most widely used family for large-scale devices
combines high speed with low power consumption
usually operates from a single supply of 5 – 15 V
excellent noise immunity of about 30% of supply voltage
can be connected to a large number of gates (about 50)
many forms – some with tPD down to 1 ns
power consumption depends on speed (perhaps 1 mW)
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Logic Level & Noise Margin for CMOS Devices
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Comparison between TTL & CMOS Logic Levels
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CMOS Inverter
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CMOS Inverter
Formation of CMOS Inverter
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CMOS NAND Gate
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CMOS AND Gate
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CMOS NOR Gate
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CMOS Subfamilies
obsolete
Reduction of dynamic losses through successively decreasing supply voltages: 12V 5V 3.3V 2.5V 1.8V
CD4000 LVC/ALVC/AVC Power reduction is one of the keys to
progressive growth of integration
General trend:
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CMOS Subfamilies
CMOS Series Prefix Example Original CMOS 40 4009 Pin compatible with TTL 74C 74H04 High-speed and pin compatible with TTL 74HC 74HC04 High-speed and electrically compatible with TTL 74HCT 74HCT04 Very High-speed and pin compatible with TTL 74VHC 74VHC04 Very High-speed and electrically compatible with TTL 74VHCT 74VHCT04 Advanced High-speed and pin compatible with TTL 74AHC 74AHC04 Advanced High-speed and electrically compatible with TTL 74AHCT 74AHCT04 Fast and electrically compatible with TTL 74FCT 74 FCT 04 Fast and electrically compatible with TTL with TTL VOH 74FCT-T 74 FCT04T
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References
Digital Principles by Malvino
Leach
Modern Digital Electronics by
R.P. Jain
Digital Electronics, Principles and
Integrated Circuits by Anil K.
Maini
Digital Techniques by A. Anand
Kumar
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Online Tutorials
http://
nptel.ac.in/video.php?s
ubjectId=117106086
http://
www.electronics-tutoria
ls.ws/logic/logic_1.html
http://
www.electronics-tutoria
ls.ws/boolean/bool_1.ht
ml
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Thank You
Amit Nevase