Digital Logic Project

EENG 2710

ProjectName: Ore Afolayan

Note : “~” means compliment

“&” means AND

“|” means OR

Part 1)

Truth Table for combinational square

0 0 0 0 0 0 0 0 0 0 0 0 0 0 00 0 0 0 1 0 0 0 0 0 0 0 0 0 10 0 0 1 0 0 0 0 0 0 0 0 1 0 00 0 0 1 1 0 0 0 0 0 0 1 0 0 10 0 1 0 0 0 0 0 0 0 1 0 0 0 00 0 1 0 1 0 0 0 0 0 1 1 0 0 1

0 0 1 1 0 0 0 0 0 1 0 0 1 0 00 0 1 1 1 0 0 0 0 1 1 0 0 0 10 1 0 0 0 0 0 0 1 0 0 0 0 0 00 1 0 0 1 0 0 0 1 0 1 0 0 0 00 1 0 1 0 0 0 0 1 1 0 0 1 0 00 1 0 1 1 0 0 0 1 1 1 1 0 0 10 1 1 0 0 0 0 1 0 0 1 0 0 0 00 1 1 0 1 0 0 1 0 1 0 1 0 0 10 1 1 1 0 0 0 1 1 0 0 0 1 0 00 1 1 1 1 0 0 1 1 1 0 0 0 0 11 0 0 0 0 0 1 0 0 0 0 0 0 0 01 0 0 0 1 0 1 0 0 1 0 0 0 0 11 0 0 1 0 0 1 0 1 0 0 0 1 0 01 0 0 1 1 0 1 0 1 1 0 1 0 0 11 0 1 0 0 0 1 1 0 0 1 0 0 0 01 0 1 0 1 0 1 1 0 1 1 1 0 0 11 0 1 1 0 0 1 1 1 1 0 0 1 0 01 0 1 1 1 1 0 0 0 0 1 0 0 0 11 1 0 0 0 1 0 0 1 0 0 0 0 0 01 1 0 0 1 1 0 0 1 1 1 0 0 0 11 1 0 1 0 1 0 1 0 1 0 0 1 0 01 1 0 1 1 1 0 1 1 0 1 1 0 0 11 1 1 0 0 1 1 0 0 0 1 0 0 0 01 1 1 0 1 1 1 0 1 0 0 1 0 0 11 1 1 1 0 1 1 1 0 0 0 0 1 0 01 1 1 1 1 1 1 1 1 0 0 0 0 0 1

Output Equations

O0 = A0 ( based on observation from truth table)

O1 = 0 (from truth table)

O2 = A1 & ~A0

O3 =( A2 & ~A1 & A0) | (~A2 & A1 & A0)

O4 =(A3 & ~A2 & A0) | (A2 & ~A1 & ~A0) | ( ~A3 & A2 & A0)

O7 =( A4 & ~A3 & A2 & ~A1) | (~A4 & A3 & A2) | (A4 & A3 & A1) | (A4 & A2 & A1 & ~A0)

O8 =( A4 & A3 & A2) | (A4 & ~A3 & ~A2) | (A4 & A2 & ~A1) | (A4 & A2 & ~A0)

O9 =( A4 & A3) | (A4 & A2 & A1 & A0)

Karnaugh maps showing the equation generation process

Circuit Diagram of the outputs

Part 2)

By looking at the equations from the truth table for each output, the following outputs can be optimized using decoders and multiplexers

Part 3)

OutputsO0 O1 O2 O3 O4 O5 O6 O7 O8 O9 Sub total

Gates 0 0 1 4 4 9 7 5 5 3 38Inputs 0 0 2 15 12 41 28 18 16 6 138Total Inverters 5

Total Cost 181

Digital Logic Project

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