Digital Systems

Topic 10: Counters in VHDL

28/18/2010

Objectives• To understand and be able to implement:

– Sequential Circuits and Counters in VHDL• Flip-flops in VHDL• Counters in VHDL

– With asynchronous and synchronous reset inputs– With enable inputs

– Implement the descriptions in Xilinx– Simulate the descriptions in Modelsim

of 42

38/18/2010

Registers• There 3 methods to explicitly insert registers

(flip-flops) into your design:– Instantiate a flip-flop in your design

• Using schematic capture tools• Instantiating a register component in your VHDL

design description– Use a process that is sensitive to a signal

• Registers may also be inserted implicitly into a design clock– Either intentionally or unintentionally

of 42

48/18/2010

Registers: Level-Triggered D LatchLIBRARY ieee ; USE ieee.std_logic_1164.all ;

ENTITY latch IS PORT (D, Clk: IN STD_LOGIC ;

Q: OUT STD_LOGIC) ; END latch ;

ARCHITECTURE Behavior OF latch IS BEGIN

PROCESS ( D, Clk ) BEGIN

IF Clk = '1' THEN Q <= D ;

END IF ; END PROCESS ;

END Behavior ;

A VHDL Design Description for a gated D latch. Note that both D and Clk are listed in the sensitivity list, meaning that a change of state in either of these signals will activate the process.

of 42

58/18/2010

Registers: Level-Triggered D LatchLIBRARY ieee ; USE ieee.std_logic_1164.all ;

ENTITY latch IS PORT (D, Clk: IN STD_LOGIC ;

Q: OUT STD_LOGIC) ; END latch ;

ARCHITECTURE Behavior OF latch IS BEGIN

PROCESS ( D, Clk ) BEGIN

IF Clk = '1' THEN Q <= D ;

END IF ; END PROCESS ;

END Behavior ;

A VHDL Design Description for a gated D latch. Note that both D and Clk are listed in the sensitivity list, meaning that a change of state in either of these signals will activate the process.

This is also a sample of implicitly inserting a register into the design (this was done intentionally).

Within the process it is stated that:If Clk=‘1’ then

Q<=D;This explicitly states what is to be done if the clock signal goes high: Q is to be assigned the value of D.

of 42

68/18/2010

Registers: Level-Triggered D LatchLIBRARY ieee ; USE ieee.std_logic_1164.all ;

ENTITY latch IS PORT (D, Clk: IN STD_LOGIC ;

Q: OUT STD_LOGIC) ; END latch ;

ARCHITECTURE Behavior OF latch IS BEGIN

PROCESS ( D, Clk ) BEGIN

IF Clk = '1' THEN Q <= D ;

END IF ; END PROCESS ;

END Behavior ;

A VHDL Design Description for a gated D latch. Note that both D and Clk are listed in the sensitivity list, meaning that a change of state in either of these signals will activate the process.

This is also a sample of implicitly inserting a register into the design (this was done intentionally).

Within the process it is stated that:If Clk=‘1’ then

Q<=D;This explicitly states what is to be done if the clock signal goes high: Q is to be assigned the value of D.

Nothing is stated about what is to be done with Q if the clock signal is low. This (as far as VHDL is concerned) implies that Q should not change: that it should remain the same, that Q should remember and retain its previous state.

of 42

78/18/2010

Registers: Level-Triggered D LatchLIBRARY ieee ; USE ieee.std_logic_1164.all ;

ENTITY latch IS PORT (D, Clk: IN STD_LOGIC ;

Q: OUT STD_LOGIC) ; END latch ;

ARCHITECTURE Behavior OF latch IS BEGIN

PROCESS ( D, Clk ) BEGIN

IF Clk = '1' THEN Q <= D ;

END IF ; END PROCESS ;

END Behavior ;

A VHDL Design Description for a gated D latch. Note that both D and Clk are listed in the sensitivity list, meaning that a change of state in either of these signals will activate the process.

This is also a sample of implicitly inserting a register into the design (this was done intentionally).

Within the process it is stated that:If Clk=‘1’ then

Q<=D;This explicitly states what is to be done if the clock signal goes high: Q is to be assigned the value of D.

Nothing is stated about what is to be done with Q if the clock signal is low. This (as far as VHDL is concerned) implies that Q should not change: that it should remain the same, that Q should remember and retain its previous state.

Note also that the code above describes a level-triggered D latch.

of 42

88/18/2010

Registers: Edge-Triggered D Latch

A VHDL Design Description for an edge-triggered D flip-flop. Note that now, only Clk is in the sensitivity list, meaning that a change of state of the Clk will activate the process.

LIBRARY ieee ; USE ieee.std_logic_1164.all ;

ENTITY Dff IS PORT (D, Clk: IN STD_LOGIC ;

Q: OUT STD_LOGIC) ; END Dff ;

ARCHITECTURE Behavior OF Dff IS BEGIN

PROCESS (Clk ) BEGIN

IF Clk’EVENT AND Clk = '1' THEN Q <= D ;

END IF ; END PROCESS ;

END Behavior ;

of 42

98/18/2010

Registers: Edge-Triggered D Latch

A VHDL Design Description for an edge-triggered D flip-flop. Note that now, only Clk is in the sensitivity list, meaning that a change of state of the Clk will activate the process.

The If statement has also changed: it now has:If Clk’EVENT AND Clk = ‘1’ then

“ ‘EVENT” is an attribute of the signal “Clk”. In this case the ‘EVENT attribute refers to any change in the state of the Clk signal.

LIBRARY ieee ; USE ieee.std_logic_1164.all ;

ENTITY Dff IS PORT (D, Clk: IN STD_LOGIC ;

Q: OUT STD_LOGIC) ; END Dff ;

ARCHITECTURE Behavior OF Dff IS BEGIN

PROCESS (Clk ) BEGIN

IF Clk’EVENT AND Clk = '1' THEN Q <= D ;

END IF ; END PROCESS ;

END Behavior ;

of 42

108/18/2010

Registers: Edge-Triggered D Latch

A VHDL Design Description for an edge-triggered D flip-flop. Note that now, only Clk is in the sensitivity list, meaning that a change of state of the Clk will activate the process.

The If statement has also changed: it now has:If Clk’EVENT AND Clk = ‘1’ then

“ ‘EVENT” is an attribute of the signal “Clk”. In this case the ‘EVENT attribute refers to any change in the state of the Clk signal.

Combining the ‘EVENT condition with the Clk=‘1’ condition means that: “the state of the Clk signal has just changed (the event) and is now 1.” So, this statement describes a positive edge-triggered Clk signal, so that Q will change (if D has changed) on the positive edge of the Clk.

LIBRARY ieee ; USE ieee.std_logic_1164.all ;

ENTITY Dff IS PORT (D, Clk: IN STD_LOGIC ;

Q: OUT STD_LOGIC) ; END Dff ;

ARCHITECTURE Behavior OF Dff IS BEGIN

PROCESS (Clk ) BEGIN

IF Clk’EVENT AND Clk = '1' THEN Q <= D ;

END IF ; END PROCESS ;

END Behavior ;

of 42

118/18/2010

Registers: Edge-Triggered D Latch

A VHDL Design Description for an edge-triggered D flip-flop. Note that now, only Clk is in the sensitivity list, meaning that a change of state of the Clk will activate the process.

The If statement has also changed: it now has:If Clk’EVENT AND Clk = ‘1’ then

“ ‘EVENT” is an attribute of the signal “Clk”. In this case the ‘EVENT attribute refers to any change in the state of the Clk signal.

Combining the ‘EVENT condition with the Clk=‘1’ condition means that: “the state of the Clk signal has just changed (the event) and is now 1.” So, this statement describes a positive edge-triggered Clk signal, so that Q will change (if D has changed) on the positive edge of the Clk.

LIBRARY ieee ; USE ieee.std_logic_1164.all ;

ENTITY Dff IS PORT (D, Clk: IN STD_LOGIC ;

Q: OUT STD_LOGIC) ; END Dff ;

ARCHITECTURE Behavior OF Dff IS BEGIN

PROCESS (Clk ) BEGIN

IF Clk’EVENT AND Clk = '1' THEN Q <= D ;

END IF ; END PROCESS ;

END Behavior ;

Hands-On: Change the description above to describe a negative edge-triggered D flip-flop.

of 42

128/18/2010

Registers: Edge-Triggered D Latch

The only change that must take place is to change the “Clk’EVENT AND Clk = ‘1’ to when these two occurrences equal 0.

LIBRARY ieee ; USE ieee.std_logic_1164.all ;

ENTITY Dff IS PORT (D, Clk: IN STD_LOGIC ;

Q: OUT STD_LOGIC) ; END Dff ;

ARCHITECTURE Behavior OF Dff IS BEGIN

PROCESS (Clk ) BEGIN

IF Clk’EVENT AND Clk = ‘0' THEN Q <= D ;

END IF ; END PROCESS ;

END Behavior ;

of 42

138/18/2010

Registers: Edge-Triggered D Latch

The only change that must take place is to change the “Clk’EVENT AND Clk = ‘1’ to when these two occurrences equal 0.

LIBRARY ieee ; USE ieee.std_logic_1164.all ;

ENTITY Dff IS PORT (D, Clk: IN STD_LOGIC ;

Q: OUT STD_LOGIC) ; END Dff ;

ARCHITECTURE Behavior OF Dff IS BEGIN

PROCESS (Clk ) BEGIN

IF Clk’EVENT AND Clk = ‘0' THEN Q <= D ;

END IF ; END PROCESS ;

END Behavior ;

Xilinx synthesized the code above to the circuit below.

of 42

148/18/2010

Registers: Wait Until

The WAIT UNTIL clause can also be used to describe an edge-triggered flip-flop. When a WAIT UNTIL clause is used, the sensitivity list is removed from the process statement because this statement implies that the clock signal is the only signal that will trigger the process.

LIBRARY ieee ; USE ieee.std_logic_1164.all ;

ENTITY Dff IS PORT (D, Clk: IN STD_LOGIC ;

Q: OUT STD_LOGIC) ; END Dff ;

ARCHITECTURE Behavior OF Dff IS BEGIN

PROCESSBEGIN

WAIT UNTIL Clk’EVENT AND Clk = ‘0' THEN Q <= D ;

END IF ; END PROCESS ;

END Behavior ;

of 42

158/18/2010

Registers: Wait Until

The WAIT UNTIL clause can also be used to describe an edge-triggered flip-flop. When a WAIT UNTIL clause is used, the sensitivity list is removed from the process statement because this statement implies that the clock signal is the only signal that will trigger the process.

In some (but not all) CAD synthesis tools the WAIT UNTIL is redundant with “ ‘EVENT”. It is included here as good practice and because it is not known which CAD tool you will use after graduation.

LIBRARY ieee ; USE ieee.std_logic_1164.all ;

ENTITY Dff IS PORT (D, Clk: IN STD_LOGIC ;

Q: OUT STD_LOGIC) ; END Dff ;

ARCHITECTURE Behavior OF Dff IS BEGIN

PROCESSBEGIN

WAIT UNTIL Clk’EVENT AND Clk = ‘0' THEN Q <= D ;

END IF ; END PROCESS ;

END Behavior ;

of 42

168/18/2010

Registers: Wait Until

The WAIT UNTIL clause can also be used to describe an edge-triggered flip-flop. When a WAIT UNTIL clause is used, the sensitivity list is removed from the process statement because this statement implies that the clock signal is the only signal that will trigger the process.

In some (but not all) CAD synthesis tools the WAIT UNTIL is redundant with “ ‘EVENT”. It is included here as good practice and because it is not known which CAD tool you will use after graduation.

LIBRARY ieee ; USE ieee.std_logic_1164.all ;

ENTITY Dff IS PORT (D, Clk: IN STD_LOGIC ;

Q: OUT STD_LOGIC) ; END Dff ;

ARCHITECTURE Behavior OF Dff IS BEGIN

PROCESSBEGIN

WAIT UNTIL Clk’EVENT AND Clk = ‘0' THEN Q <= D ;

END IF ; END PROCESS ;

END Behavior ;

So: Why use the WAIT UNTIL instead of the IF?

When the Clk’EVENT AND Clk = ‘x’ statement is used in an IF statement, any signals that are assigned values within the IF statement are implemented as outputs of a flip-flop.

When the Clk’EVENT AND Clk = ‘x’ statement is used in a WAIT UNTIL statement, any signals that are assigned values within the entire process statement are implemented as outputs of a flip-flop.

of 42

178/18/2010

Registers: D FF with RESET

LIBRARY ieee ; USE ieee.std_logic_1164.all ;

ENTITY flipflop IS PORT (D, Resetn, Clock: IN STD_LOGIC ;

Q: OUT STD_LOGIC) ; END flipflop ;

ARCHITECTURE Behavior OF flipflop IS BEGIN

PROCESS ( Resetn, Clock ) BEGIN

IF Resetn = '0' THEN Q <= '0' ;

ELSIF Clock'EVENT AND Clock = '1' THEN Q <= D ;

END IF ; END PROCESS ;

END Behavior ;

Many flip-flops (and counters) have a reset input. Some are synchronous, some are asynchronous. Below is the code for two very similar, D flip-flops. Which has a synchronous reset? Which has an asynchronous reset?

LIBRARY ieee ; USE ieee.std_logic_1164.all ;

ENTITY flipflop IS PORT (D, Resetn, Clock: IN STD_LOGIC ;

Q: OUT STD_LOGIC) ; END flipflop ;

ARCHITECTURE Behavior OF flipflop IS BEGIN

PROCESS BEGIN

WAIT UNTIL Clock'EVENT AND Clock = '1' ;IF Resetn = '0' THEN

Q <= '0' ; ELSE

Q <= D ; END IF ;

END PROCESS ;END Behavior ;

of 42

188/18/2010

Registers: D FF with RESET

LIBRARY ieee ; USE ieee.std_logic_1164.all ;

ENTITY flipflop IS PORT (D, Resetn, Clock: IN STD_LOGIC ;

Q: OUT STD_LOGIC) ; END flipflop ;

ARCHITECTURE Behavior OF flipflop IS BEGIN

PROCESS ( Resetn, Clock ) BEGIN

IF Resetn = '0' THEN Q <= '0' ;

ELSIF Clock'EVENT AND Clock = '1' THEN Q <= D ;

END IF ; END PROCESS ;

END Behavior ;

Many flip-flops (and counters) have a reset input. Some are synchronous, some are asynchronous. Below is the code for two very similar, D flip-flops. Which has a synchronous reset? Which has an asynchronous reset?

LIBRARY ieee ; USE ieee.std_logic_1164.all ;

ENTITY flipflop IS PORT (D, Resetn, Clock: IN STD_LOGIC ;

Q: OUT STD_LOGIC) ; END flipflop ;

ARCHITECTURE Behavior OF flipflop IS BEGIN

PROCESS BEGIN

WAIT UNTIL Clock'EVENT AND Clock = '1' ;IF Resetn = '0' THEN

Q <= '0' ; ELSE

Q <= D ; END IF ;

END PROCESS ;END Behavior ;

Asynchronous, the Reset signal is outside the clock event

Synchronous, the Reset signal is within the clock event

of 42

198/18/2010

Registers: D FF with RESETXilinx synthesized the implementation shown below for the synchronous D flip-flop

of 42

208/18/2010

Counters: A 4-bit Up CounterThe code for a 4-bit counter with an asynchronous reset input and an enable input (E).

LIBRARY ieee ; USE ieee.std_logic_1164.all ; USE ieee.std_logic_unsigned.all ;

ENTITY Counter IS PORT (Clock, Reset, E: IN STD_LOGIC ;

Q: OUT STD_LOGIC_VECTOR (3 DOWNTO 0) ) ; END Counter ;

ARCHITECTURE Behavior OF Counter IS SIGNAL Count: STD_LOGIC_VECTOR (3 DOWNTO 0);

BEGINPROCESS (Clock, Reset)

BEGINIF Reset = ‘0’ THEN

Count <= ‘0000’;ELSIF (Clock’EVENT AND Clock = ‘1’) THEN

IF E=‘1’ THEN Count <= Count +1;

ELSECOUNT <= Count;

ENDIF;ENDIF;

END PROCESS ; Q <= Count;

END Behavior ;

of 42

218/18/2010

Counters: A 4-bit Up CounterThe code for a 4-bit counter with an asynchronous reset input and an enable input (E).

LIBRARY ieee ; USE ieee.std_logic_1164.all ; USE ieee.std_logic_unsigned.all ;

ENTITY Counter IS PORT (Clock, Reset, E: IN STD_LOGIC ;

Q: OUT STD_LOGIC_VECTOR (3 DOWNTO 0) ) ; END Counter ;

ARCHITECTURE Behavior OF Counter IS SIGNAL Count: STD_LOGIC_VECTOR (3 DOWNTO 0);

BEGINPROCESS (Clock, Reset)

BEGINIF Reset = ‘0’ THEN

Count <= ‘0000’;ELSIF (Clock’EVENT AND Clock = ‘1’) THEN

IF E=‘1’ THEN Count <= Count +1;

ELSECOUNT <= Count;

ENDIF;ENDIF;

END PROCESS ; Q <= Count;

END Behavior ;

Count is an internal 4-bit signal that is equal to Q

Reset is asynchronous because it is outside the Clock’EVENT AND Clock=‘1’ clause.

E enables the counter: i.e.; the counter will only count if E=1Count is specified explicitly (for clarity) if the counter is not enabled.

Q is assigned the value of Count

of 42

228/18/2010

Counters: A 4-bit Up CounterThe code for the 4-bit counter shown in the previous slide should produce one of two circuits, depending on whether the synthesizer chose T flip flops or ……..

T Q

Q Clock

T Q

Q

Enable

Clear

T Q

Q

T Q

Q

of 42

238/18/2010

Counters: A 4-bit Up Counter

Clock

Enable D QQ

D QQ

D QQ

D QQ

Q0

Q1

Q2

Q3

Outputcarry

The code for the 4-bit counter shown in the previous slide should produce one of two circuits, depending on whether the synthesizer chose T flip flops or D flip flops

of 42

248/18/2010

Counters: A 4-bit Up Counter

Clock

Enable D Q

Q

D Q

Q

D Q

Q

D Q

Q

Q0

Q1

Q2

Q3

Outputcarry

The code for the 4-bit counter shown in the previous slide should produce one of two circuits, depending on whether the synthesizer chose T flip flops or D flip flops

I decided to try it myself in Xilinx …….

of 42

258/18/2010

Counters: A 4-bit Up CounterAlthough the code to the left is standard VHDL, the Xilinx ISE produced several errors upon attempting to synthesize.

LIBRARY ieee ; USE ieee.std_logic_1164.all ; USE ieee.std_logic_unsigned.all ;

ENTITY Counter IS PORT (Clock, Reset, E: IN STD_LOGIC ;

Q: OUT STD_LOGIC_VECTOR (3 DOWNTO 0) ) ; END Counter ;

ARCHITECTURE Behavior OF Counter IS SIGNAL Count: STD_LOGIC_VECTOR (3 DOWNTO 0);

BEGINPROCESS (Clock, Reset)

BEGINIF Reset = ‘0’ THEN

Count <= ‘0000’;ELSIF (Clock’EVENT AND Clock = ‘1’) THEN

IF E=‘1’ THEN Count <= Count +1;

ELSECOUNT <= Count;

ENDIF;ENDIF;

END PROCESS ; Q <= Count;

END Behavior ;

of 42

268/18/2010

Counters: A 4-bit Up CounterAlthough the code to the left is standard VHDL, the Xilinx ISE produced several errors upon attempting to synthesize (because of copy-paste). The file below synthesized (the only difference is highlighted):

LIBRARY ieee ; USE ieee.std_logic_1164.all ; USE ieee.std_logic_unsigned.all ;

ENTITY Counter IS PORT (Clock, Reset, E: IN STD_LOGIC ;

Q: OUT STD_LOGIC_VECTOR (3 DOWNTO 0) ) ; END Counter ;

ARCHITECTURE Behavior OF Counter IS SIGNAL Count: STD_LOGIC_VECTOR (3 DOWNTO 0);

BEGINPROCESS (Clock, Reset)

BEGINIF Reset = ‘0’ THEN

Count <= ‘0000’;ELSEIF (Clock’EVENT AND Clock = ‘1’) THEN

IF E=‘1’ THEN Count <= Count +1;

ELSECOUNT <= Count;

ENDIF;ENDIF;

END PROCESS ; Q <= Count;

END Behavior ;

LIBRARY ieee ; USE ieee.std_logic_1164.all ; USE ieee.std_logic_unsigned.all ;

ENTITY Counter IS PORT (Clock, Reset, E: IN STD_LOGIC ;

Q: OUT STD_LOGIC_VECTOR (3 DOWNTO 0) ) ; END Counter ;

ARCHITECTURE Behavior OF Counter IS SIGNAL Count: STD_LOGIC_VECTOR (3 DOWNTO 0);

BEGINPROCESS (Clock, Reset)

BEGINIF Reset = ‘0’ THEN

Count <= “0000”;ELSIF (Clock’EVENT AND Clock = ‘1’) THEN

IF E=‘1’ THEN Count <= Count +1;

ELSECOUNT <= Count;

ENDIF;ENDIF;

END PROCESS ; Q <= Count;

END Behavior ;

Xilinx wanted double quotes around the 0s assigned to Count instead of single quotes.

of 42

278/18/2010

Counters: A 4-bit Up CounterThe synthesized circuit is shown below.

Double clicking on this symbol produced…..

of 42

288/18/2010

Counters: A 4-bit Up CounterThe logic circuit

of 42

298/18/2010

Counters: A 4-bit Up CounterThe logic circuit

These are positive edge-triggered D flip-flops with an enable (CE), a clock (C), a reset (clr), and a D input.

The outputs are also fed back to the input logic (as should be done with a counter)

of 42

308/18/2010

Counters: A 4-bit Up CounterThe logic circuit

The input logic was different for each D flip-flop.

of 42

318/18/2010

Counters: A 4-bit Up CounterThe logic circuit

The input logic was different for each D flip-flop.

of 42

328/18/2010

Counters: A 4-bit Up CounterThe logic circuit

The input logic was different for each D flip-flop.

Each also has an associated KMap and Truth Table.

of 42

338/18/2010

SimulationThe waveform below was added to the project file to see if it operated as it should

of 42

348/18/2010

Simulation

E enables the counter when high. Reset should reset the counter when low.

The waveform below was added to the project file to see if it operated as it should

of 42

358/18/2010

Simulation

The count should change for each pulse of the clock (on the positive edge).

The waveform below was added to the project file to see if it operated as it should

of 42

368/18/2010

Modelsim Results

The counter starts at “0000” because the reset signal was low to start

of 42

378/18/2010

Modelsim Results

The counter didn’t change to a “0001” until the count was enabled

of 42

388/18/2010

Modelsim Results

The counter didn’t change to a “0001” until the count was enabled, and continued until disabled

of 42

398/18/2010

Modelsim Results

Instead of seeing these numbers, some like to see the individual counter waveforms. To see them click on the [+]

of 42

408/18/2010

Modelsim Results

Instead of seeing these numbers, some like to see the individual counter waveforms. To see them click on the [+] and they can be seen.

of 42

418/18/2010

The Counter• The counter is the fundamental building

block for state machines (our next topic)• Flip-flops are the fundamental building block

for:• Static Memory• Counters• Registers

of 42

428/18/2010

Summary• In this topic will discussed the building

blocks for state machines– We discussed and were able to implement:

• Sequential Circuits and Counters in VHDL– Flip-flops in VHDL– Counters in VHDL

» With asynchronous and synchronous reset inputs» With enable inputs

• Implement the descriptions in Xilinx• Simulate the descriptions in Modelsim

of 42