CET 486 – 586 Hardware Description Language:Hardware Description Language:...
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CET 486 – 586 Hardware Description Language:Hardware Description Language:
VHDLVHDL
Introduction to hardware description languages using VHDL. Techniques for modeling and simulating small digital systems
using a VHDL simulator
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Textbooks
“A VHDL Primer” by J. Bhasker, Prentice Hall, Third Edition Required textEdition. Required text“The Designer’s Guide to VHDL” by Peter Ashenden,Morgan Kaufman Reference textMorgan Kaufman. Reference text“VHDL for Designers” by Sjoholm and Lindh. PrenticeHall Reference textHall. Reference text“VHDL for Logic Synthesis. An introductory guide for
hi i D i R i t ” b A d R htachieving Design Requirements” by Andrew Rushton. McGraw Hill. Reference text
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General Information
P i itPrerequisites
Purposes
Labs
Exercises
Quiz
Tests
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Grading
Quizzes 10%
Mid Term Exam 20%
Labs 25%
Project 25%
Final Exam 20%Final Exam 20%
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Academic Integrity Policy
• AIP: http://www asu edu/studentlife/judicial/integrity htmlhttp://www.asu.edu/studentlife/judicial/integrity.html
C d f C d t• Code of Conduct: http://www.asu.edu/aad/manuals/sta/sta104-01.html
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Contact Information
C i ti Si tCristian [email protected]: www. . .
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VHDL – IntroductionVHDL Introduction
Chapter I
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VHDL - Features
• V Hi h S d IC H d D i ti L• Very High Speed IC Hardware Description Language• The design is technologically independent• Allow to design generic components• Standard component already coded in VHDLp y• Timing verification• The designer concern is the functionality• The designer concern is the functionality • Portability: VHDL is an IEEE standard
VHDL S ti l L C t L• VHDL = Sequential Language + Concurrent Language + Net-List + Timing Constraints + Waveform Generation
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VHDL – Features (cont’)
• Flexible design methodology: top down bottom up• Flexible design methodology: top-down, bottom-up • It is not proprietary• There is no limit for the design to be described in VHDL• Allow description of delay time (minimum and
maximum), hold time, setup time• Very short development timey p• Allow different levels of abstraction (Assembler, C, C++)
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VHDL Flow Design
Specifications Synthesis & p
VHDL C d
yOptimization
VHDL CodePlace & Route
CompilationTiming
VerificationSimulation & Verification
Verification
Back-end ToolsFront-end Tools
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VHDL – General ViewVHDL General View
Introduction to VHDL
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Entity
• A hardware abstraction of a Digital System is an entity• A hardware abstraction of a Digital System is an entity
• Five VHDL design units describe an entity– Entity declaration– Architecture body– Configuration declaration– Package declaration– Package body
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Entity declaration
• Describe the external view of an entity The input and• Describe the external view of an entity. The input and output signal names:--===================================================------ entity declaration syntax----===================================================--
tit i ientity <entity_name> is[generic
(list_of_generics_their_types_and_value);][port[port
(list_of_interface_port_names_mode_and_types);][entity_item_declaration][begin[begin
entity_statements]end [entity] [entity_name];
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Architecture body
• Contains the internal description of the entity--====================================================------ architecture body syntax----====================================================--
architecture <architecture_name> of <entity_name> is[architecture_declarations]
beginconcurrent_statements;
[process_statementblock_statement
t d ll t t tconcurrent_procedure_call_statementconcurrent_assertion_statementconcurrent_signal_assignment_statementcomponent instantiation statementcomponent_instantiation_statementgenerate_statement]
end [architecture] [architecture_name];
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Example: Half-adder
A SumX1 Sum
Carry
X1
B CarryA1
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Half-adder: entity declaration
--================================------- Circuit: Half Adder-- Objective: example -- Ref: fig 2.3 "VHDL Primer"
A SumX1
Ref: fig 2.3 VHDL Primer----===============================-- B CarryA1
entity half_adder isport(
A: in bit;B: in bit;SUM: out bit;CARRY: out bit);
end half_adder;
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Half_adder: architecture body as a set of interconnected componentsinterconnected components
STRUCTURAL----====== structural style of modeling =====----architecture HA_STRUCTURE of HALF_ADDER is
component XOR2port (X, Y: in bit
Z: out bit);end component;component AND2
port (L, M: in bit;
ASumX1
p ( , ;N: out bit);
end component;begin
X1 XOR2 t (A B SUM)
B CarryA1
X1: XOR2 port map (A, B, SUM);A1: AND2 port map (A, B, CARRY);
end HA_STRUCTURE;
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Half_adder: architecture body as a set of concurrent assignment statementsconcurrent assignment statements
DATAFLOW----====== data flow style of modeling ======----architecture HA_DATA_FLOW of HALF_ADDER isbegin
SUM <= A xor B;CARRY <= A and B;
end HA_CONCURRENT;
ASumX1
B CarryA1
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Half_adder: architecture body as a set of sequential assignment statementssequential assignment statements
BEHAVOIRAL----========= behavioral style of modeling ========----architecture HA BEHAVIORAL 2 of HALF ADDER is_ _ _beginprocess (A, B)begin
if (A='0' and B='0')thenSUM <= '0';CARRY <= '0';
elsif (A='1' and B='0'| A='0' and B='1')thenSUM <= '1';CARRY <= '0';
l '1' d '1' Aelse -- A'1' and B='1'SUM <= '0';CARRY <= '1';
end if
A SumX1
end if;end process;end HA_BEHAVIORAL_2; B
CarryA1
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Half_adder: architecture body as a mixed style
--========= mixed style of modeling =========----architecture HA_BEHAVIORAL_2 of HALF_ADDER is
signal SUM1: bit;component AND2
port(L, M: in bit;N: out bit);
end component;beginbegin
X1: XOR2 port map (A, B, SUM1); -- structural process (A, B) -- behaviorbegin
if (A '0' d B '0')thif (A='0' and B='0')thenCARRY <= '0';
elsif (A='1' and B='0'| A='0' and B='1')thenCARRY <= '0';
else -- A'1' and B='1'CARRY <= '1';
end if;end process;end process;SUM <= SUM1; -- data flow
end HA_BEHAVIORAL_2;
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Simulation
Waveform Text
Stimulus ResultsDevice Under
Test (DUT)
Test Bench WaveformTest Bench (VHDL Code)
Waveform
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Simulation
Waveform StimulusWaveform Stimulus
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Simulation
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Simulation
Test BenchTest Bench
a <= '1' '0' after 10 nsa <= 1 , 0 after 10 ns, '1' after 39 ns, '0' after 110 ns, '1' ft 145 '0' ft 155'1' after 145 ns, '0' after 155 ns;
b <= '0', '1' after 30 ns, '0' ft 49 '1' ft 90'0' after 49 ns, '1' after 90 ns, '0' after 115 ns, '1' after 135 ns;
assert (a=‘1’ and b=‘1’ and sum=‘0’)report “error when a=b=‘1’ sum /= ‘0’”
severity note;
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Simulation
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