Digital Integrated Circuits 2nd Sequential Circuits Digital Integrated Circuits A Design Perspective...

Sequential Circuits

Digital Integrated Digital Integrated CircuitsCircuitsA Design PerspectiveA Design Perspective

Designing SequentialDesigning SequentialLogic CircuitsLogic Circuits

Jan M. RabaeyAnantha ChandrakasanBorivoje Nikolic

November 2002

Sequential Circuits

Sequential LogicSequential Logic

2 storage mechanisms• positive feedback• charge-based

COMBINATIONALLOGIC

Registers

Outputs

Next state

Current State

Inputs

Sequential Circuits

Naming ConventionsNaming Conventions

In our text: a latch is level sensitive a register is edge-triggered

There are many different naming conventions For instance, many books call edge-

triggered elements flip-flops This leads to confusion however

Sequential Circuits

Latch versus RegisterLatch versus Register Latch

stores data when clock is low

Registerstores data when clock rises

Clk Clk

Sequential Circuits

LatchesLatches

Positive Latch

Outstable

Outfollows In

Negative Latch

Outstable

Outfollows In

Sequential Circuits

Latch-Based DesignLatch-Based Design

• N latch is transparentwhen = 1

• P latch is transparent when = 0

NLatch Logic

PLatch

Sequential Circuits

Timing DefinitionsTiming Definitions

tc 2 q

tholdtsu

tQ DATA

STABLE

DATASTABLE

Register

Sequential Circuits

Characterizing TimingCharacterizing Timing

tC 2 Q

tD 2 Q

Register Latch

Sequential Circuits

Maximum Clock FrequencyMaximum Clock Frequency

FF’s

tp,comb

Also:tcdreg + tcdlogic > thold

tcd: contamination delay = minimum delaytclk-Q + tp,comb + tsetup =

Sequential Circuits

Positive Feedback: Bi-StabilityPositive Feedback: Bi-StabilityVi1 Vo2

Vo2 =Vi1

Vo1 =Vi2

Vi1=Vo2

Vo1 Vi2

Vi2=Vo1

Sequential Circuits

Meta-StabilityMeta-Stability

Gain should be larger than 1 in the transition region

Vi1 5Vo2

Sequential Circuits

Writing into a Static LatchWriting into a Static Latch

Converting into a MUXForcing the state(can implement as NMOS-only)

Use the clock as a decoupling signal, that distinguishes between the transparent and opaque states

Sequential Circuits

Mux-Based LatchesMux-Based LatchesNegative latch(transparent when CLK= 0)Positive latch

(transparent when CLK= 1)

InClkQClkQ InClkQClkQ

Sequential Circuits

Mux-Based LatchMux-Based Latch

Sequential Circuits

Mux-Based LatchMux-Based Latch

CLKCLK

NMOS only Non-overlapping clocks

Sequential Circuits

Master-Slave (Edge-Triggered) Master-Slave (Edge-Triggered) RegisterRegister

Master

Two opposite latches trigger on edgeAlso called master-slave latch pair

Sequential Circuits

Master-Slave RegisterMaster-Slave Register

I3 T4I5

Multiplexer-based latch pair

Sequential Circuits

Reduced Clock Load Reduced Clock Load Master-Slave RegisterMaster-Slave Register

D QT1 I1

Sequential Circuits

Avoiding Clock OverlapAvoiding Clock OverlapCLK

(a) Schematic diagram

(b) Overlapping clock pairs

Sequential Circuits

Overpowering the Feedback Loop ─Overpowering the Feedback Loop ─Cross-Coupled PairsCross-Coupled Pairs

Forbidden State

010 1011 0R Q

NOR-based set-reset

Sequential Circuits

Storage MechanismsStorage Mechanisms

Dynamic (charge-based)

Static

Sequential Circuits

Other Latches/Registers: COther Latches/Registers: C22MOSMOS

Master Stage

CLK M8

“Keepers” can be added to make circuit pseudo-static

Sequential Circuits

Insensitive to Clock-OverlapInsensitive to Clock-Overlap

(a) (0-0) overlap

(b) (1-1) overlap

Sequential Circuits

PipeliningPipeliningRE

REGlog

Reference Pipelined

Sequential Circuits

Other Latches/Registers: TSPCOther Latches/Registers: TSPC

Negative latch(transparent when CLK= 0)

Positive latch(transparent when CLK= 1)

Sequential Circuits

TSPC RegisterTSPC Register

Sequential Circuits

Including Logic in TSPCIncluding Logic in TSPC

CLKIn CLK

VDDVDD

In1 In2

AND latchExample: logic inside the latch

Sequential Circuits

Pulse-Triggered LatchesPulse-Triggered LatchesAn Alternative ApproachAn Alternative Approach

Master-Slave Latches

Pulse-Triggered Latch

L1 L2 L

Ways to design an edge-triggered sequential cell:

Sequential Circuits

Pulsed LatchesPulsed Latches

(a) register (b) glitch generation

Sequential Circuits

Latch-Based PipelineLatch-Based Pipeline

In Out

Compute F compute G

Sequential Circuits

Non-Bistable Sequential Circuits─Non-Bistable Sequential Circuits─Schmitt TriggerSchmitt Trigger

In Out

Vout VOH

VM– VM+

•VTC with hysteresis•Restores signal slopes

Sequential Circuits

Noise Suppression using Schmitt Noise Suppression using Schmitt TriggerTrigger

t0 + tp t

Sequential Circuits

Schmitt Trigger Simulated VTCSchmitt Trigger Simulated VTC

Vin (V)

Voltage-transfer characteristics with hysteresis. The effect of varying the ratio of thePMOS device M4 . The width isk* 0.5 m.m

0.00.0 0.5 1.0 1.5 2.0 2.5

k = 2k = 3

Vin (V)

0.00.0 0.5 1.0 1.5 2.0 2.5

Sequential Circuits

CMOS Schmitt Trigger (2)CMOS Schmitt Trigger (2)

Sequential Circuits

MonostableMonostable

Sequential Circuits

Astable Multivibrators (Oscillators)Astable Multivibrators (Oscillators)

0 1 2 N-1

Ring Oscillator

simulated response of 5-stage oscillator

2.5V1 V3 V5

20.50.5

time (ns)

1.0 1.5

Sequential Circuits

Relaxation OscillatorRelaxation Oscillator

T = 2 (log3) RC

Sequential Circuits

Voltage Controller Oscillator (VCO)Voltage Controller Oscillator (VCO)

Vcontr Current starved inverter

Iref Iref

Schmitt Triggerrestores signal slopes

0.5 1.5 2.5Vcontr (V)

propagation delay as a functionof control voltage

Digital Integrated Circuits 2nd Sequential Circuits Digital Integrated Circuits A Design Perspective...

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