Post on 13-Jan-2016
April 21, 2023 1
A Stable System Clock Generator Using Reference Clock
SamplingAatmesh ShrivastavaRobust Low Power VLSI GroupUniversity of Virginia
Alicia KlinefelterRobust Low Power VLSI Group
University of Virginia
April 21, 2023 2
Outline
• Motivation Crystal oscillator design and power consumption
• Novel Circuit Architecture Three phases of operation viz calibration, conversion and retention phase
• Circuit Design: Calibration Phase F to V converter Op-Amp VCO PTAT
• Conversion and Retention Phase ADC Capacitive DAC R-2R DAC
• Summary• References
April 21, 2023 3
Motivation : Crystal Oscillator CRYSTAL
• Almost all microprocessors, micro-controllers, PICs, and CPUs operate using a crystal oscillator.
Crystal oscillator provides the reference clock.
• Why?? Highest accuracy and frequency stability compared
to any known oscillator.
• Usually Fed to PLL to generate system clock, Sometimes can be used as is.
• Frequency range from 10Khz-50Mhz
CRYSTAL SYMBOL
Board Hook-up Equivalent circuit Circuit Diagram of Xtal oscillator
April 21, 2023 4
Motivation : Crystal Oscillator Power
• Crystal with Char. frequency of 32Khz to 50Mhz designed to obtain power. Most optimal point for oscillation. Crystal parameter obtained through vendor data-sheets.
• Power dissipated ranges from 2.6uW @ 32Khz to 70mW @ 50Mhz. At 200Khz power ranges from 5uW to 30uW.
• Crystal Oscillator consumes significant amount of power, critically impacts the power consumption of a system designed for lower power.
April 21, 2023 5
Motivation : Proposed Circuit techniqueWe propose a fully integrated reference/system clock circuit in CMOS.
The circuit achieves a high frequency stability of +/-250ppm. We reduce the power consumption to a very low level < 2u Watts @ 200Khz Unlike a crystal oscillator the power consumption of proposed circuit does not scale up with the
frequency because of the architecture.
Proposed Circuit
F to V Converter
Op. Amp.
VCO
F to V Converter
_
+
PTAT
control out
Clock coming from crystal or
RF source
ADCReg
Block
DACCounter
done
1
0
clock
done
Analog Mux
E
AF to V Converter
Op. Amp.
VCO
F to V Converter
_
+
PTAT
control out
Clock coming from crystal or
RF source
ADCRegister
Block
DACCounter
done
1
0clock
done
Analog Mux
• Retention Phase.(done=1) After done goes high, DAC is calibrated with desired o/p voltage for VCO. Clock can be turned off. The voltage at DAC can be maintained through bank of registers. All other blocks except DAC, PTAT and VCO can be disabled and are disabled. PTAT controls the temperature drift of VCO.
• Calibration Phase. (done=0)
A stable voltage is obtained at A, corresponding to reference frequency through crystal oscillator
The amplifier controls the VCO. The VCO oscillation frequency is converted back to voltage using F to V converter.
Feedback structure makes sure that A=E. (Need very high gain amplifier to insure this)
Calibration is completed once voltage at E becomes equal to A.
• Conversion Phase. (done=0) Once E settles to value of A, Analog to Digital
converter (ADC) and Digital to Analog Converter is enabled.
These two blocks generates C which is equal to B with <1mV quantization error.
Done signal goes high after conversion is done which causes MUX to select the DAC output.
April 21, 2023 6
Circuit Operate in 3 Phases.
April 21, 2023 7
Circuit Design: Frequency to Voltage converter[1]
Is
VDD
Clk
11
2
C1 C2
MP1 MN1
MN2
T1 T2
Time
1
2
ClK
T2
Clk1
2
T1
T2
T1
• Figure shows Frequency to Voltage converter (FVC) schematic which is based on switching capacitors and current source.
• 1 and 2 are pulse signals. 1 is generated after rising edge of Clock, while 2 is generated after falling edge of 1
Circuit Diagram FVC
April 21, 2023 8
Functioning
Time
1
2
ClK
T2
T1
C1 C2
Is
• When Clock is Low MP1 is on transmission gate T1 is off and MN2 is off.
• C1 gets charged through Is. C1=C2
• When goes high MP1 is off and MN2 is OFF. T1 is on and C1 and C2 Share charge as shown
• When goes high T1 is off MP1 is off and MN2 is ON which discharges C1 to ground.
C2
• This process is repeated and eventually charges C2 to the maximum Voltage of C1.
• A voltage thus inversely proportional to frequency is obtained at C2.
April 21, 2023 9
Output waveforms
A OUT
Out build-Up
Steady state internal net waveforms
April 21, 2023 10
Circuit Design: Folded Cascode Operational Amplifier
VDD VDD
VDDINPINN
MP1 MP2
MN1 MN2
M1
VM
VDD
VM
VM=VDD/2
OUT
A
B
CCp
• Gain of the amplifier gets multiplied through each stage.
• Very High gain. • Quiescent current = 200nA• Since Op-amp is used in feedback structure,
stability of the system is achieved Cp. Compensating Cap
+
_OUT
April 21, 2023 11
Proposed Circuit
Stability of the system
Feedback path
Because of the feedback, stability sims were done.
April 21, 2023 12
Insuring Stability of the system
+
_VCO F to V
OUTA
REF
• As voltage at A changes, frequency of VCO changes and because frequency changes voltage at OUT will changes. In other words voltage at A changes voltage at OUT.• This means there is a phase difference b/w A and OUT or there is a pole b/w A and OUT.
• OUT being feedback net so this pole impacts the stability.
• We obtain the delay from A to OUT. Using the delay number we approximate the pole by RC and perform open loop AC analysis.
=+
_ OUTA
REF
Pole to replace VCO and F to V for stability analysis
open-loop ac analysis reduction for the system.
Feedback portion of the system
April 21, 2023 13
Stability Analysis
Phase Margin=DC Gain= 100 dB
80
April 21, 2023 14
Voltage Controlled Oscillator
+
_INV BUF
OUT5 OUT1
VP
VNOPAMP
Current Mirror
VP
VN
IN
=
Delay Element in VCO
Functioning• Current sources MP and MN determine the delay and hence frequency of VCO.• As Output of OPAMP increases, VN increases and VP decreases.• Current sources MP and MN drive increases, which increases frequency.• Five such delay elements are used.
MP
MN
Voltage Controlled Oscillator
Voltage Controlled Oscillator
VCO output at VN=700mVVCO output at VN=883mV f=200Khz
Effect of Temperature variation on VCO• After the calibration phase, VCO input would remain at constant voltage.• Temperature will cause current source to vary.• This will change the frequency.
Frequency changes from 220Khz to 200 Khz from 0 to 100oC
Sweeping temperature for IN.
• With increasing temperature IDRIVE of NMOS drops
April 21, 2023 17
Removing effect of Temperature: PTAT[2]• Idrive reduces with temp. Use PTAT to control temperature drift.• Add current of MOS and PTAT to get zero temperature coefficient. (ZTC)
Sta
rt-u
p
IB
RB
IB
1
1 1
M>1
MP2MP1
MN1MN2
• As Temperature increases, the Threshold voltage of transistor decreases.
• Current in the circuit is given by
VGS
• With temperature VT of MN1 drops hence VGS, consequently VB increases increasing IB.
VB
PTAT Output
Sweeping temperature for IPTAT.
April 21, 2023 18
Getting ZTC currents for VCO
Variation of Current sources in VCO.
April 21, 2023 19
• Current in VCO’s current source vary by 3nA over ~400nA over a temperature variation of 0 to 100oC
VCO output at 0, 50 and 100 Degrees
April 21, 2023 20
• With change is temperature frequency of oscillation changes from 200 Khz to 201 Khz.
Frequency stability = +/-250ppm
F to V Converter
Op. Amp. VCO
F to V Converter
_
+
PTAT
control
out
Clock coming from crystal or
RF source
Putting it together: Calibration Phase
FV1
FV2
VCO_in
VCO_in
FV1
FV2
FV2=FV1
F to V Converter
Op. Amp. VCO
F to V Converter
_
+
PTAT
control
out
Clock coming from crystal or
RF source
Putting it together: Calibration Phase
CLKIN
VCO_OUT
ADC Architectures
Sigma Delta Successive Approximation
Accuracy High Accuracy Determined by DAC and Comparator
Power Higher Lower
Conversion Time Fast (due to oversampling)
N*(cycle time)No pipeline delay
Typical Bit Range > 10 bits < 15 bits
Complexity High Low
April 21, 2023 23
Successive Approximation (SAR) ADC
• Begins by making assumptions about bit values starting with the MSB and forcing 1000…00 (Vref/2)onto the DAC.
• If this voltage is above the analog input, the assumed bit goes to 0, else it remains 1.
• Then assumptions are made about all bits till the LSB and checked so the system “zeros in” on the result.
April 21, 2023 24
SAR ADC Block Diagram [4]
• Comparator: Compares assumption coming from DAC and input analog voltage.
• DAC: Takes current assumption bits and turns them into analog voltage for comparison in next stage.
• SAR Logic: Takes output of comparator (0 or 1) to determine the next bit value and set the next bit assumption.
April 21, 2023 25
Comparator
• Three op amps used (two P, one N)
April 21, 2023 26
The Charge Scaling 10-bit DAC [3]
• Capacitor DAC acts as both DAC and sample-hold circuit.• Design consideration: base cap size, C.• Needs to be reset before use (discharge caps).
0 0.002 0.004 0.006 0.008 0.01 0.012-0.1
0
0.1
0.2
0.3
0.4
0.5
0.6
time (ms)
volta
ge (
V)
Charge Scaling DAC Output
April 21, 2023 27
• DAC makes series of guesses. – If (guess voltage) > (analog input) over-approximation. This bit is 0.– Else the guess is below the expected value. This bit is 1.
0 0.2 0.4 0.6 0.8 1 1.2
x 10-3
0
0.2
0.4
0.6
0.8
1
time (ms)
voltage (
V)
ADC Converging with Comp. Output
Analog Ref.
Comp. OutDAC Out
April 21, 2023 28
The R-2R 10-bit DAC [3]
• Simple voltage divider network.• Does not require initialization signal and does not need to be periodically refreshed.• Tradeoff: branch current vs. resistor size
0 0.002 0.004 0.006 0.008 0.01 0.012
0
0.05
0.1
0.15
0.2
0.25
0.3
0.35
0.4
0.45
0.5
time (ms)
volta
ge (
V)
R-2R Ladder DAC
April 21, 2023 29
The ADC/DAC Network• Active Power
consumption: 550nA• Technology: IBM 130nm• Supply Voltage: 1 V• Sampling Rate: 20 kHz• Future optimizations:
– Low-power optimization for ADC
April 21, 2023 30
April 21, 2023 31
Summary• Novel low power, high stability clock circuit is proposed.
• The circuit achieves a frequency stability of +/-250ppm.
• Power in calibration-phase = 5uW, retention-phase = 2uW.
• Similar to crystal in stability (+/-100ppm) better than crystal in terms of power consumption.
Power consumption does not scale up with frequency unlike crystal oscillator
April 21, 2023 32
Questions?
April 21, 2023 33Aatmeshas4xz@virginia.edu
References[1] A Djemouai et al. “New Frequency Locked Loop based CMOS frequency to voltage converter: Design and Implementation” IEEE Transactions on Circuits and systme II: Analog and Digital Signal Processing. vol. 48 No-5, May 2001.[2] D. Liu et al. “A simple voltage reference circuit using transistor with ZTC point and PTAT current source” IEEE J Solid-State Circuits vol. 29 pp 663- 670, June 1994.[3] Allen E. and Holberg D. “CMOS Analog Circuit Design” Oxford University Press, New York, 2002.[4] Simone Gambini and Jan Rabaey. “Low-Power Succesive Approximation Converter with 0.5 V Supply in 90 nm CMOS” IEE Transactions of Solid-State Circuits. Vol. 42, no. 11, Nov. 2007.
April 21, 2023 Aaatmesh 34
BACK UP
Crystal Oscillator: Design
April 21, 2023 35Aatmeshas4xz@virginia.edu
RBIAS
• During start-up phase RBIAS( extremely high value) keeps the Inverter at VM.
• Oscillation builds up with noise.• The crystal passes only the resonant frequency
voltage, which gets amplifier.• The amplified value gets passed through crystal
which again gets amplified.• This goes on till Oscillation saturates.
CLCL
April 21, 2023 Aaatmesh 36
+
_VCO F to V
OUTA
REF
Feedback portion of the system
=+
_ OUTA
REF
Pole to replace VCO and F to V for stability analysis
Configuration for open-loop ac analysis of the system.
A to OUT delay = 100uSSo if R=10K C=100pFWe choose R=50K and C=100pF for our ac analysis
April 21, 2023 37
Addressing variability: Global variation• Global variation will cause the shift in the current in PTAT which can cause the
temperature compensation to drift either in CTAT or PTAT direction.
Sta
rt-u
p
IB
RB
1
1 1
M>1
MP2MP1
MN1MN2 • Vary RB through bit control to affect a good ztc point.
April 21, 2023 38
Addressing variability: Local Mismatch• Local mismatch can cause an offset which can cause frequency of VCO to be
different from Clock.
F to V Converter
Op. Amp.
VCO
F to V Converter
_
+
PTAT
control out
Clock coming from crystal or
RF source
ADCReg
Block
DACCounter
done
1
0
clock
done
Analog Mux
FV1
FV2
• If we bit control the current source of FV2, we can set f(Clock)=f(VCO).
April 21, 2023 39
Solution for high frequency clocks• In order to get higher frequency output divide the VCO output by K just like a
PLL.• This would have very little impact on over all power consumption of the
system.
F to V Converter
Op. Amp.
VCO
F to V Converter
_
+
PTAT
control out
Clock coming from crystal or
RF source
ADCReg
Block
DACCounter
done
1
0
clock
done
Analog Mux
Divide/K