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Transcript of 1 A stable and low power on-chip system clock circuit for sensor nodes and low Power Timers Aatmesh...
![Page 1: 1 A stable and low power on-chip system clock circuit for sensor nodes and low Power Timers Aatmesh Shrivastava Robust Low Power VLSI Group University.](https://reader035.fdocuments.us/reader035/viewer/2022062308/56649eb65503460f94bbee87/html5/thumbnails/1.jpg)
1
A stable and low power on-chip system clock circuit for sensor nodes and low Power Timers
Aatmesh ShrivastavaRobust Low Power VLSI GroupUniversity of Virginia
![Page 2: 1 A stable and low power on-chip system clock circuit for sensor nodes and low Power Timers Aatmesh Shrivastava Robust Low Power VLSI Group University.](https://reader035.fdocuments.us/reader035/viewer/2022062308/56649eb65503460f94bbee87/html5/thumbnails/2.jpg)
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Outline• Motivation
Power for clock source Temperature stability for clock source
• Goal• Oscillator Architecture
Current source PTAT and CTAT Calibration Architecture Results/Discussion 2nd order compensation. Results/Discussion
• Low power DCO Leakage current
• Results• Question• References• Back-up
![Page 3: 1 A stable and low power on-chip system clock circuit for sensor nodes and low Power Timers Aatmesh Shrivastava Robust Low Power VLSI Group University.](https://reader035.fdocuments.us/reader035/viewer/2022062308/56649eb65503460f94bbee87/html5/thumbnails/3.jpg)
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Motivation• Stable On-chip oscillator for system clock/Time reference
• Why?Lower PowerReduces feature size, makes the platform implantableLower Cost
• Other OptionCrystal oscillatorHigher cost, increased feature size, more power etc.Better temperature stability etc.
![Page 4: 1 A stable and low power on-chip system clock circuit for sensor nodes and low Power Timers Aatmesh Shrivastava Robust Low Power VLSI Group University.](https://reader035.fdocuments.us/reader035/viewer/2022062308/56649eb65503460f94bbee87/html5/thumbnails/4.jpg)
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10-1
100
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103
104
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107
108
109
10-11
10-10
10-9
10-8
10-7
10-6
10-5
10-4
10-3
10-2
10-1
Frequency in Hertz
Po
wer
in W
atts
Crystal OscillatorOnChip Oscillator
[3]
[5] [8]
[6,7]
[9]
[1][2]
[4]
[10]
[12]
[11]
[13]
[14]
Power for clock source
• Literature shows that on-chip oscillator consumes lower power in general than crystal oscillator
![Page 5: 1 A stable and low power on-chip system clock circuit for sensor nodes and low Power Timers Aatmesh Shrivastava Robust Low Power VLSI Group University.](https://reader035.fdocuments.us/reader035/viewer/2022062308/56649eb65503460f94bbee87/html5/thumbnails/5.jpg)
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10-1
100
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10-2
10-1
100
101
102
103
104
105
106
Frequency in Hertz
Te
mp
era
ture
sta
bil
ity
in
pp
m/o
C
Crystal OscillatorOn Chip Oscillator
[1]
[2][3]
[4] [6,7] [9] [11]
[10] [5] [12]
[8]
[13][14]
Uncompensated
Temp. Stability for clock source
• Stability expressed in ppm/oC 1ppm/oC means ~1S variation of clock period in a day for a change of 10oC in
temperature
• Crystal more stable than on-chip oscillators.
![Page 6: 1 A stable and low power on-chip system clock circuit for sensor nodes and low Power Timers Aatmesh Shrivastava Robust Low Power VLSI Group University.](https://reader035.fdocuments.us/reader035/viewer/2022062308/56649eb65503460f94bbee87/html5/thumbnails/6.jpg)
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Goal• Ideal solution
On-chip oscillator with stability close to crystal oscillator.
• Goal :- Move towards ideal solutionProposes a stable clock with stability 8ppm/oC.Consumes <2uW and runs at 200Khz.
• Also presentA 70nW clock at 200Khz using leakage current
(uncompensated).An open loop calibration circuit for the clock, Circuit for
voltage, Process and mismatch effects for the clock.
![Page 7: 1 A stable and low power on-chip system clock circuit for sensor nodes and low Power Timers Aatmesh Shrivastava Robust Low Power VLSI Group University.](https://reader035.fdocuments.us/reader035/viewer/2022062308/56649eb65503460f94bbee87/html5/thumbnails/7.jpg)
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Oscillator Architecture• Options.
On-chip LC [16] -> Higher power/ higher area On-chip Relaxation oscillator [8] -> Uses Opamp, higher power, area.
• Current starved ring oscillator. Best for low power. [1-3] & [17-18] and is selected.
• [1-3] uses gate leakage as current source and used at extremely low frequency.
• Constant Io and CL will result in a stable oscillation.
Io
Io
Io
IoCL CL
![Page 8: 1 A stable and low power on-chip system clock circuit for sensor nodes and low Power Timers Aatmesh Shrivastava Robust Low Power VLSI Group University.](https://reader035.fdocuments.us/reader035/viewer/2022062308/56649eb65503460f94bbee87/html5/thumbnails/8.jpg)
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• PTAT + CTAT=C. Will result in constant
current Less than 1% variation Standard way of
obtaining constant current
• CTAT. MOS in strong inversion Current decreases with
temp
Constant current source
Sta
rt-up
IB
RB
IB
1
1 1
M>1
MP2MP1
MN1MN2
• PTAT. Current increases
with temp
Process variation
Process variation
![Page 9: 1 A stable and low power on-chip system clock circuit for sensor nodes and low Power Timers Aatmesh Shrivastava Robust Low Power VLSI Group University.](https://reader035.fdocuments.us/reader035/viewer/2022062308/56649eb65503460f94bbee87/html5/thumbnails/9.jpg)
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Current source• Because of process variation the absolute value of
the current will change. 8 bits are used which can give different weight of the constant current. Digital control bits
VDD
Current
Source1/256
P0
1/128 1/2 1
P1 P7 P8
To DCO
VDD VDD VDD VDD
• Using Binary weights a desired current is obtained
![Page 10: 1 A stable and low power on-chip system clock circuit for sensor nodes and low Power Timers Aatmesh Shrivastava Robust Low Power VLSI Group University.](https://reader035.fdocuments.us/reader035/viewer/2022062308/56649eb65503460f94bbee87/html5/thumbnails/10.jpg)
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Obtaining accurate frequency• Mismatch b/w current source will result in
frequency error
8 bit binarycontrol
8 bit binarycontrol
Delay Line10 bit coarse control
Delay Line5 bit fine control
Current source controlled (5) Delay elements
• Additional digital delay line is used for accuracy. Maximum delay comes from current source structure Digital inverter based delay line corrects for offset.
A DCO
![Page 11: 1 A stable and low power on-chip system clock circuit for sensor nodes and low Power Timers Aatmesh Shrivastava Robust Low Power VLSI Group University.](https://reader035.fdocuments.us/reader035/viewer/2022062308/56649eb65503460f94bbee87/html5/thumbnails/11.jpg)
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Calibration technique/Architecture
DCO
Frequency Comparator
SARLOGIC
ConstantCurrent Source
P<0:7>8 bit Process Control Bits
c<0:9>
F<0:4>
EnableDone
Refin=Ref Clk*2
10 bit coarse Control
5 bit fine ControlDCO_OUT
• Every cycle DCO is compared with reference by frequency comparator.
• Similar to [25]
• Its output sets the 15 bit of SAR• Alternate cycles are used for calibration to enable the settling of current source
• Once calibrated reference can be turned off
![Page 12: 1 A stable and low power on-chip system clock circuit for sensor nodes and low Power Timers Aatmesh Shrivastava Robust Low Power VLSI Group University.](https://reader035.fdocuments.us/reader035/viewer/2022062308/56649eb65503460f94bbee87/html5/thumbnails/12.jpg)
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ResultDCO
Frequency Comparator
SARLOGIC
ConstantCurrentSource
P<0:7>8 bit Process Control Bits
c<0:9>
F<0:4>
EnableDone
Ref Clk*2
10 bit coarse Control
5 bit fine ControlDCO_OUT
• Output frequency has an error of 300pS• Very close to reference frequency
![Page 13: 1 A stable and low power on-chip system clock circuit for sensor nodes and low Power Timers Aatmesh Shrivastava Robust Low Power VLSI Group University.](https://reader035.fdocuments.us/reader035/viewer/2022062308/56649eb65503460f94bbee87/html5/thumbnails/13.jpg)
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Advantages of This architecture• Simpler architecture than an ADPLL.
• Much lower settling time. Takes 46 cycles to settle compared to 64000 cycles in [22]
• Consequently lower power during calibration
• After calibration gives output clock in phase with reference.
• Disadvantage -> After calibration does not track the phase
Can use counter control technique to keep it in lock[23]
• Stability of the oscillator controls the drift.
![Page 14: 1 A stable and low power on-chip system clock circuit for sensor nodes and low Power Timers Aatmesh Shrivastava Robust Low Power VLSI Group University.](https://reader035.fdocuments.us/reader035/viewer/2022062308/56649eb65503460f94bbee87/html5/thumbnails/14.jpg)
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Result
0 10 20 30 40 50 60 70 80 90 1004.95
4.96
4.97
4.98
4.99
5
5.01x 10
-6
Temperature in oC
Tim
er p
erio
d in
Sec
on
ds
Time period
• Can achieve 40ppm/oC Comparable to reported best work [3] & [8] { 32ppm/oC and 23ppm/oC}
• Can be improved further
![Page 15: 1 A stable and low power on-chip system clock circuit for sensor nodes and low Power Timers Aatmesh Shrivastava Robust Low Power VLSI Group University.](https://reader035.fdocuments.us/reader035/viewer/2022062308/56649eb65503460f94bbee87/html5/thumbnails/15.jpg)
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2nd Order compensation
• At higher temperature current increases Leakage has similar trend
• Use leakage current to apply 2nd order compensation
![Page 16: 1 A stable and low power on-chip system clock circuit for sensor nodes and low Power Timers Aatmesh Shrivastava Robust Low Power VLSI Group University.](https://reader035.fdocuments.us/reader035/viewer/2022062308/56649eb65503460f94bbee87/html5/thumbnails/16.jpg)
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2nd order compensation
• The additional circuit incorporates little delay which increases with temperature.
Constant current
Current source controlled
Constant current
LVt
LPVt
Charges the cap
![Page 17: 1 A stable and low power on-chip system clock circuit for sensor nodes and low Power Timers Aatmesh Shrivastava Robust Low Power VLSI Group University.](https://reader035.fdocuments.us/reader035/viewer/2022062308/56649eb65503460f94bbee87/html5/thumbnails/17.jpg)
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Result
0 10 20 30 40 50 60 70 80 90 1004.98
4.985
4.99
4.995
5
5.005
5.01x 10
-6
Temperature in oC
Per
iod
in s
eco
nd
s
• Over 0-100 oC we do not get significant improvement
• 20-90 oC stability is much improved
![Page 18: 1 A stable and low power on-chip system clock circuit for sensor nodes and low Power Timers Aatmesh Shrivastava Robust Low Power VLSI Group University.](https://reader035.fdocuments.us/reader035/viewer/2022062308/56649eb65503460f94bbee87/html5/thumbnails/18.jpg)
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Result
20 30 40 50 60 70 80 904.9975
4.998
4.9985
4.999
4.9995
5
5.0005
5.001
5.0015
5.002x 10
-6
Temperature in oC
Per
iod
in s
eco
nd
s
• Over 20-90oC stability is 8ppm/oC Period of 5uS varies by 3nS over 70oC temperature range
• Better than best reported works [3] & [8] { 32ppm/oC and 23ppm/oC}
![Page 19: 1 A stable and low power on-chip system clock circuit for sensor nodes and low Power Timers Aatmesh Shrivastava Robust Low Power VLSI Group University.](https://reader035.fdocuments.us/reader035/viewer/2022062308/56649eb65503460f94bbee87/html5/thumbnails/19.jpg)
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Low power DCO -> uncomp.• To design an DCO working at 200Khz or lower,
leakage current should be used [1-3]. Other approach like hysteretic delay cell [24] etc. will result in more
power because of higher caps required for delay
P0 P1 P7
1/256 1/128 1
Keeper to obtain full rail
• Delay is constructed using binary weights of leakage current
Uses LVT transistor for leakage current
![Page 20: 1 A stable and low power on-chip system clock circuit for sensor nodes and low Power Timers Aatmesh Shrivastava Robust Low Power VLSI Group University.](https://reader035.fdocuments.us/reader035/viewer/2022062308/56649eb65503460f94bbee87/html5/thumbnails/20.jpg)
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ResultDCO
Frequency Comparator
SARLOGIC
ConstantCurrentSource
P<0:7>8 bit Process Control Bits
c<0:9>
F<0:4>
EnableDone
Ref Clk*2
10 bit coarse Control
5 bit fine ControlDCO_OUT• Same calibration technique is
used
• Output frequency has an error of +/-2nS• This architecture does not have good stability w.r.t temperature
![Page 21: 1 A stable and low power on-chip system clock circuit for sensor nodes and low Power Timers Aatmesh Shrivastava Robust Low Power VLSI Group University.](https://reader035.fdocuments.us/reader035/viewer/2022062308/56649eb65503460f94bbee87/html5/thumbnails/21.jpg)
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10-1
100
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10-11
10-10
10-9
10-8
10-7
10-6
10-5
10-4
10-3
10-2
10-1
Frequency in Hertz
Po
wer
in W
atts
Crystal OscillatorOnChip Oscillator
[3]
[5] [8]
[6,7]
[9]
[1][2]
[4]
[10]
[12]
[11]
[13]
[14] This workTemp Compensated
This worklow power clk
Result
• Compensated DCO consumes 2uW, uncompensated DCO consumes 70nW.
Results are in line with the trend, lower than crystal
![Page 22: 1 A stable and low power on-chip system clock circuit for sensor nodes and low Power Timers Aatmesh Shrivastava Robust Low Power VLSI Group University.](https://reader035.fdocuments.us/reader035/viewer/2022062308/56649eb65503460f94bbee87/html5/thumbnails/22.jpg)
22
10-1
100
101
102
103
104
105
106
107
108
109
10-2
10-1
100
101
102
103
104
105
106
Frequency in Hertz
Te
mp
era
ture
sta
bil
ity
in
pp
m/o
C
Crystal OscillatorOn Chip Oscillator
[1]
[2][3]
[4] [6,7] [9] [11]
[10] [5] [12]
[8]
[13][14]
Uncompensated
This work Compensated Oscillator
This work
Result
• Stability of compensated oscillator is 8ppm/oC Better than reported works ~4S variation of clock period in a day for a change of 5oC in
temperature
![Page 23: 1 A stable and low power on-chip system clock circuit for sensor nodes and low Power Timers Aatmesh Shrivastava Robust Low Power VLSI Group University.](https://reader035.fdocuments.us/reader035/viewer/2022062308/56649eb65503460f94bbee87/html5/thumbnails/23.jpg)
23
Summary• A very high stability 8ppm/oC oscillator is presented
which can work as system clock.
• In-phase output using very simple calibration circuit.
• Consumes less than 2uW of power.
• Also presented a leakage current based ultra low power DCO
• Low power DCO consumes 70nW.
• A sensor node can decide what type of clock it needs, based on power or stability criterion
![Page 24: 1 A stable and low power on-chip system clock circuit for sensor nodes and low Power Timers Aatmesh Shrivastava Robust Low Power VLSI Group University.](https://reader035.fdocuments.us/reader035/viewer/2022062308/56649eb65503460f94bbee87/html5/thumbnails/24.jpg)
24
Questions
![Page 25: 1 A stable and low power on-chip system clock circuit for sensor nodes and low Power Timers Aatmesh Shrivastava Robust Low Power VLSI Group University.](https://reader035.fdocuments.us/reader035/viewer/2022062308/56649eb65503460f94bbee87/html5/thumbnails/25.jpg)
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References[1] Y.-S. Lin, D. Sylvester, and D. Blaauw, “A Sub-pW Timer Using Gate Leakage for Ultra Low-Power Sub-Hz Monitoring Systems,” IEEE Custom Integrated Circuits Conf., pp.397-400, Sept., 2007.[2] Yu-Shiang Lin; Sylvester, D.M.; Blaauw, D.T. “A 150pW program-and-hold timer for ultra-low-power sensor platforms” Solid-State Circuits Conference - Digest of Technical Papers, 2009. ISSCC 2009. IEEE International[3] Yoonmyung Lee, Bharan Giridhar, Zhiyoong Foo, Dennis Sylvester, David Blaauw, “A 660pW Multi-stage Temperature Compensated Timer for Ultra-low Power Wireless Sensor Node Synchronization,”IEEE International Solid-State Circuit Conference (ISSCC), February 2011[4]X. Zou, X. Xu, L. Yao, and Y. Lian, “A 1-V 450-nW fully integrated programmable biomedical sensor interface chip,” IEEE Journal of Solid-State Circuits, vol.44, no.4, Apr. 2009, pp.1067-1077.[5] K. Choe, O. D. Bernal, D. Nuttman, and M. Je, “A precision relaxation oscillator with a self-clocked offset-cancellation scheme for implantable biomedical SoCs,” in IEEE ISSCC Dig. Tech. Papers, Feb. 2009, pp. 402–403.[6] Shu-Yu Hsu; Jui-Yuan Yu; Chen-Yi Lee; , "A Sub-10-μW Digitally Controlled Oscillator Based on Hysteresis Delay Cell Topologies for WBAN Applications," Circuits and Systems II: Express Briefs, IEEE Transactions on , vol.57, no.12, pp.951-955, Dec. 2010[7] Man-Chia Chen; Jui-Yuan Yu; Chen-Yi Lee; , "A sub-100μW area-efficient digitally-controlled oscillator based on hysteresis delay cell topologies," Solid-State Circuits Conference, 2009. A-SSCC 2009. IEEE Asian, vol., no., pp.89-92, 16-18 Nov. 2009.[8] An On-Chip CMOS Relaxation Oscillator With Voltage Averaging Feedback Tokunaga, Y.; Sakiyama, S.; Matsumoto, A.; Dosho, S.; Solid-State Circuits, IEEE Journal of Volume: 45 , Issue: 6 Publication Year: 2010 , Page(s): 1150 – 1158[9] C.-Y. Yu, J.-Y. Yu, and C.-Y. Lee, “An eCrystal oscillator with selfcalibration capability,” in Proc. IEEE Int. Symp. Circuits and Systems (ISCAS), 2009, pp. 237–240.[10] Y.-S. Shyu and J.-C. Wu, “A process and temperature compensated ring oscillator,” in Proc. 1st IEEE Asia Pacific Conf., 1999, pp. 283–286.[11] J. Routama, K. Koli, and K. Halonen, “A novel ring-oscillator with a very small process and temperature variation,” in Proc. IEEE Int. Symp. Circuits and Systems (ISCAS’98), 1998, vol. 1, pp. 181–184.[12] K. Sundaresan, K. C. Brouse, K. U-Yen, F. Ayazi, and P. E. Allen, “A 7-MHz process, temperature and supply compensated clock oscillator in 0.25 ìm CMOS,” in Proc. 2003 Int. Symp. Circuits and Systems (ISCAS’03), 2003, vol. 1, pp. I-693–I-696.[12] R. Vijayaraghavan, S. K. Islam, M. R. Haider, and L. Zuo, “Wideband injection-locked frequency divider based on a process and temperature compensated ring oscillator,” IET Circuits, Devices & Syst., vol. 3, pp. 259–267, 2009.[13] G. De Vita, F. Marraccini, and G. Iannaccone, “Low-voltage low-power CMOS oscillator with low temperature and process sensitivity,” in Proc. IEEE Int. Symp. Circuits and Systems (ISCAS 2007), 2007, pp. 2152–2155.[14] K. R. Lakshmikumar, V. Mukundagiri, and S. L. J. Gierkink, “A process and temperature compensated two-stage ring oscillator,” in Proc. IEEE Custom Integrated Circuits Conf. (CICC’07), 2007, pp. 691–694.[15]Vittoz, E.A., Degrauwe, M.G.R. and Bitz, S. High-performance crystal oscillator circuits: theory and application. IEEE journal of Solid-State Circuits, 23, 5 (Jun 1988), 774-783.[16]Van Helleputte, N. , Gielen, G. An Ultra-low-Power Quadrature PLL in 130nm CMOS for Impulse Radio Receivers. Biomedical Circuits and Systems Conference, 2007. BIOCAS 2007. IEEE, 23, 5 (Nov 2007), 63-66.[17]Gundel, A. , Carr, W.N. , Ultra Low Power CMOS PLL Clock Synthesizer for Wireless Sensor Nodes Circuits and Systems, 2007. ISCAS 2007. IEEE International Symposium on (May 2007), 3059-3062.[18]S Drago, et al, Nai-Heng Tseng. A 200μA Duty-Cycled PLL for Wireless Sensor Nodes in 65 nm CMOS. JSSCC July 2010.[19]A Djemouai et al. “New Frequency Locked Loop based CMOS frequency to voltage converter: Design and Implementation” IEEE Transactions on Circuits and systme II: Analog and Digital Signal Processing. vol. 48 No-5, May 2001.[20]Kansal, A. , Srivastava, M.B. , An environmental energy harvesting framework for sensor network. Low Power Electronics and Design, 2003. ISLPED '03. Proceedings of the 2003 International Symposium on, 23, 5 (Aug-2003), 481-486[21]D. Liu et al. “A simple voltage reference circuit using transistor with ZTC point and PTAT current source” IEEE J Solid-State Circuits vol. 29 pp 663- 670, June 1994.[22] Chang, Hsiang-Hui ; Fu, Chia-Huang ; Chiu, Monty ; “A 320fs-RMS-jitter and 300kHz-BW all-digital fractional-N PLL with self-corrected TDC and fast temperature tacking loop for WiMax/WLAN 11n” VLSI Circuits, 2009 Symposium on[23] T. Matano, Y. Takai, T. Takahashi, Y. Sakito, I. Fujii, Y. Takaishi, H. Fujisawa, S. Kubouchi, S. Narui, K. Arai, M. morino, M. Nakamura, S. Miyatake, T. Sekiguchi, and K. Koyama, “A 1-Gb/s/pin 512-Mb DDRII SDRAM using a digital DLL and a slew-rate-controlled output buffer,” IEEE J. Solid-State Circuits, vol. 38, no. 5, pp. 762-768, May 2003.
![Page 26: 1 A stable and low power on-chip system clock circuit for sensor nodes and low Power Timers Aatmesh Shrivastava Robust Low Power VLSI Group University.](https://reader035.fdocuments.us/reader035/viewer/2022062308/56649eb65503460f94bbee87/html5/thumbnails/26.jpg)
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PTAT current source
Sta
rt-u
p
IB
RB
IB
1
1 1
M>1
MP2MP1
MN1MN2
• PTAT. Top transistors are in strong
inversionBottom transistor are in
weak inversion
![Page 27: 1 A stable and low power on-chip system clock circuit for sensor nodes and low Power Timers Aatmesh Shrivastava Robust Low Power VLSI Group University.](https://reader035.fdocuments.us/reader035/viewer/2022062308/56649eb65503460f94bbee87/html5/thumbnails/27.jpg)
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Process variation current source
Sta
rt-u
p
IB
RB
IB
1
1 1
M>1
MP2MP1
MN1MN2
Process variation causes the current source to move from ideal
5 bit control on resistor
Adding bit control on resistor yields ideal behavior
Mismatch can also be handled in the similar way
![Page 28: 1 A stable and low power on-chip system clock circuit for sensor nodes and low Power Timers Aatmesh Shrivastava Robust Low Power VLSI Group University.](https://reader035.fdocuments.us/reader035/viewer/2022062308/56649eb65503460f94bbee87/html5/thumbnails/28.jpg)
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Jitter on the clock
Less than 2nS of jitter seen on clock over 100 cycles
![Page 29: 1 A stable and low power on-chip system clock circuit for sensor nodes and low Power Timers Aatmesh Shrivastava Robust Low Power VLSI Group University.](https://reader035.fdocuments.us/reader035/viewer/2022062308/56649eb65503460f94bbee87/html5/thumbnails/29.jpg)
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2nd order compensation
• The additional circuit incorporates little delay which increases with temperature.
Constant current
Current source controlled
Constant current
LVt
LPVt
6 bit binary weighted control for process
![Page 30: 1 A stable and low power on-chip system clock circuit for sensor nodes and low Power Timers Aatmesh Shrivastava Robust Low Power VLSI Group University.](https://reader035.fdocuments.us/reader035/viewer/2022062308/56649eb65503460f94bbee87/html5/thumbnails/30.jpg)
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Stability strong
0.000005100000
0.000005110000
0.000005120000
0.000005130000
0.000005140000
0.000005150000
0.000005160000
0.000005170000
0.000005180000
0.000005190000
0.000005200000
0.000005210000
0 20 40 60 80 100 120
![Page 31: 1 A stable and low power on-chip system clock circuit for sensor nodes and low Power Timers Aatmesh Shrivastava Robust Low Power VLSI Group University.](https://reader035.fdocuments.us/reader035/viewer/2022062308/56649eb65503460f94bbee87/html5/thumbnails/31.jpg)
31
Stability weak
0.000004975000
0.000004980000
0.000004985000
0.000004990000
0.000004995000
0.000005000000
0.000005005000
0.000005010000
0.000005015000
0 20 40 60 80 100 120
![Page 32: 1 A stable and low power on-chip system clock circuit for sensor nodes and low Power Timers Aatmesh Shrivastava Robust Low Power VLSI Group University.](https://reader035.fdocuments.us/reader035/viewer/2022062308/56649eb65503460f94bbee87/html5/thumbnails/32.jpg)
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PPM calculation
• 3nS out of 5uS
• 3/5000*1000000= 600ppm
• This varies over 70oC
• Output= 600/70~8ppm/oC
![Page 33: 1 A stable and low power on-chip system clock circuit for sensor nodes and low Power Timers Aatmesh Shrivastava Robust Low Power VLSI Group University.](https://reader035.fdocuments.us/reader035/viewer/2022062308/56649eb65503460f94bbee87/html5/thumbnails/33.jpg)
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CTAT
PTAT
Sta
rt-u
p
M>1
RB
1
1 1 IN
![Page 34: 1 A stable and low power on-chip system clock circuit for sensor nodes and low Power Timers Aatmesh Shrivastava Robust Low Power VLSI Group University.](https://reader035.fdocuments.us/reader035/viewer/2022062308/56649eb65503460f94bbee87/html5/thumbnails/34.jpg)
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2nd order compensation
Current source controlled
Io
LVt
LPVt
Charges the cap Io
CL
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Calibration technique/Architecture
DCO
Frequency Comparator
SARLOGIC
ConstantCurrent Source
P<0:7>8 bit Process Control Bits
c<0:9>
F<0:4>
EnableDone
Ref2=Ref Clk*2
10 bit coarse Control
5 bit fine ControlDCO_OUT
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8 bit binarycontrol
8 bit binarycontrol
Delay Line10 bit coarse control
Delay Line5 bit fine control
Current source controlled (5) Delay elements
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Initial calibration phase
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Advantages of This architecture
A very high stability 8ppm/oC oscillator is presented which can work as system clock. In-phase output using very simple calibration circuit. Consumes less than 2uW of power. Also presented a leakage current based ultra low power DCO.
Low power DCO consumes 70nW. A sensor node can decide what type of clock it needs, based on power or stability criterion
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Result
a)Initial Calibration a)Final Settled
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PTAT
Sta
rt-u
p
M>1
RB
1
1 1 ICOMP
5:32 bit control on resistor
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