(Jtag) boundary scan test - a practical approach - harry bleeker - peter van den eijnden - frans de jong - kluwer academic
ARM7TDM
BTW 2010 An IEEE 1149.7 Update : Standard Reduced-pin and Enhanced-functionality Test Access Port and Boundary-Scan Architecture Adam W Ley ASSET InterTech,
Presenter : Chien-Hung Chen Tsung-Cheng Lin Kuan-Fu Kuo 20090331 EICE team Open On-Chip Debugger Ch6. Design and Architecture.
The Hierarchical Scan Description Language (HSDL) was developed by to complement BSDL.
TAP (Test Access Port) JTAG course June 2006 Avraham Pinto.
National Sun Yat-sen University Embedded System Laboratory
