The Hierarchical Scan Description Language

(HSDL) was developed by

to complement BSDL.

HSDL using the same subset of VHSIC Scan Description

Language (VHDL) statements as BSDL.

BSDL focuses on describing only IEEE 1149.1 compliant

devices.

It does not address IEEE 1149.1 at the board, system, or

multi-chip module levels .

BSDL also needs a few device-level features added to better

support interactive debug .

Manipulating test registers as a stream of bits is not easy, and

determining the values on device pin buses or on fields within test

data registers by looking at binary or hexadecimal output is

impossible.

HSDL picks up where BSDL stops, describing additional attributes of IEEE 1149.1

devices and how IEEE 1149.1 devices are connected at the

board and system level.

HSDL addresses a number of deficiencies in both BSDL and

Configuration Files.

It supports all the features of BSDL for industry compatibility, providing support for automatic

test-pattern generation, validation, and synthesis tools.

HSDL also supports all the convenience features of Configuration Files, providing the ability to describe

boards, name subsets of test registers, create symbol tables for test registers

or fields that use symbolic, named values, prevent illegal states from being

established, and so forth.

For automated tools, HSDL includes new features such as

those for describing different status values captured by a test register and designating them as "pass"

or "fail" values.

For interactive use, HSDL includes new features such as

those for adding descriptive text to each item in the entity.

HSDL is a strict superset of BSDL: All statements that are part of HSDL device entities but not

part of BSDL are optional .

Thus, BSDL is an acceptable input to an

HSDL translator!!!

HSDL device entities can be made acceptable to a BSDL translator

simply by feeding them to the BSDL translator and deleting all the new statements that cause syntax errors, with no loss or change in

meaning.

HSDL uses the BSDL entity and package in new ways:

Entities in HSDL describe modules as well as devices .

)A module is any level of architecture above the device level, including

boards, multichip modules, backplanes, subsystems, and systems(.

In addition, HSDL provides two new packages used to indicate

that an entity is an HSDL device or module.

BSDL is great for describing how IEEE 1149.1 is

implemented in a device, but stops there…

HSDL provides a method for describing how IEEE 1149.1 devices are connected at the board, module, and system

levels!

HSDL module statements use much of the same syntax as

BSDL .

New statements have been added to describe the members and scan paths of the module and to simplify interactive use.

HSDL employs the same subset of VHDL statements used by BSDL.

However, the VHDL statements are used in more flexible ways in HSDL

than in BSDL.

For example, BSDL onlyattaches attributes to the entity. HSDL attaches attributes to the entity, the ports, and to Symbol

Table and Path constants.

These three different VHDL items are used in the same

manner in HSDL as they are inBSDL.

HSDL has two types of entities, however: device entities and

module entities.

A device entity describes an IEEE 1149.1 device, with test registers, instructions, and a

TAP.

A module entity describes an IEEE 1149.1 module, which contains other device and

module entities arranged along a scan path.

EXAMPLES…

ENTITY DESCRIPTION

The entity statement names the entity, such as the module name (e.g.,

BOARD). An entity description begins with an entity statement and terminates

with an end statement :

entity BOARD is {statements to describe the entity go here} end BOARD;

GENERIC PARAMETER(Unchanged from BSDL)

A generic parameter may come

from outside the entity or it may be defaulted, such as a package type

(e.g., "UNDEFINED").

generic

)PHYSICAL_PIN_MAP : string := "UNDEFINED ("

LOGICAL PORT DESCRIPTION (Unchanged from BSDL)

The port description gives logical names to the I/O pins (system and TAP pins), and denotes their nature such as input, output, bidirectional,

and so on. port (TDI:in bit;

TDO:out bit; TMS:in bit; TCK:in bit;(

USE STATEMENTS

The use statement refers to external definitions found in

packages and package bodies .

use STD_1149_1_1990.all;use HSDL_module.all;

PIN MAPPING(S)(Unchanged from BSDL)

The pin mapping provides a mapping of logical signals onto the physical pins of a particular entity.

attribute PIN_MAP of BOARD : entity is PHYSICAL_PIN_MAP;

constant PINOUT1 : PIN_MAP_STRING=: " TDI:1, TDO:2, TMS:3, TCK:4, GND:5;"

SCAN PORT IDENTIFICATION(Unchanged from BSDL)

The scan port identification statements define the entity's TAP.

attribute TAP_SCAN_IN of TDI : signal is TRUE;attribute TAP_SCAN_OUT of TDO : signal is TRUE;attribute TAP_SCAN_MODE of TMS : signal is TRUE;attribute TAP_SCAN_CLOCK of TCK : signal is

) 5.0e6, LOW ;(

PATH DESCRIPTION

Module paths are intended to describe the netlist of TAP signals

(scan paths) on the board

constant boardpath1 : STATIC_PATH=: " U1, U2;"

end BOARD;

And there are many more…