L. Greiner 1PXL Sensor and RDO review – 06/23/2010
STAR
PXL System Hardware Architecture
L. Greiner 2PXL Sensor and RDO review – 06/23/2010
STARTalk Outline
• Revisit Requirements.• Overall Architecture.• Design Choices.• Summary.
L. Greiner 3PXL Sensor and RDO review – 06/23/2010
STAR PXL System Requirements
• Interface to the sensors for readout and control.
• Triggered detector system fitting into existing STAR infrastructure (Trigger, DAQ, etc.)
• Deliver full frame events to STAR DAQ for event building at approximately the same rate as the TPC (1 kHz for DAQ1000).
• Have live time characteristics such that the Pixel detector is live whenever the TPC is live. (PXL adds ≤ 5% additional dead time)
• Reduce the total data rate of the detector to a manageable level (< TPC rate of ~1MB / event).
• Reliable, cost effective, etc.
• Provide additional functionality for sensor testing including production probe testing.
L. Greiner 4PXL Sensor and RDO review – 06/23/2010
STARPixel Detector Characteristics
• Two concentric layers at 2.5 & 8 cm radii• 10 sensors/ladder, 4 ladders/module (arm), 10 modules/detector.• MAPS Pixel technology• Sensor spatial resolution < 10 μm • Coverage 2π in φ and |η|<1• Over 400 M pixels on ~0.16 m2 of Silicon• 0.37 % radiation length/layer • MCS limited resolution • Thinned silicon sensors (50 μm thickness)• Air cooled• Sensor power dissipation ~170 mW/cm2
• Quick extraction and detector replacement• Mechanical stability and insertion reproducibility within a 20 μm
window• Integration time <200 μs (L=8×1027)• Radiation environment at the level of up to 20k – 90k rad/year and
1011 -1012/cm2 Neq /year
L. Greiner 5PXL Sensor and RDO review – 06/23/2010
STAR System Constraints
• We need FPGA processing to do zero suppression (Phase-2) and event building. This necessitates moving the processing out of the high radiation area. (SEU)
• The constraint of locating the event fast pre-processing hardware ~7m from the sensors (in a lower radiation area) requires a driver/mass termination board located between the sensors and the processing hardware. This is required for mechanical and signal integrity reasons.
• This provides additional benefit that the main part of the electronics is in an area that is serviceable during a cave access.
• This leads to a 3 main component architecture.
L. Greiner 6PXL Sensor and RDO review – 06/23/2010
STAR PXL Hardware Architecture
80sensor data
5JTAG, RSTB
clk, START, SPEAK, marker8
LADDERMass Termination Board
LU Power Regulation
V5 Interface Motherboard
Temp diode2
Analog, Dig power, GND3
1 of 4
1 of 4
ana, dig, bufpower, gnd
4 3
320 sensor data
40JTAG, RSTB
clk, STARTSPEAK, marker8
Temp diode (I2C)4
LU senseand reset
LU sense and reset12
SIU
Fib
ers
gnd1
STA
R T
CD pw
r, g
nd
2
CM
OS
i/o
LVD
S i/
o
diff
anal
og in
pwr,
gnd
US
B
pwr,
gnd
in
Buf pwr2
clk returnclk return22
RDO motherboard Mass Termination Board
Ladder
L. Greiner 7PXL Sensor and RDO review – 06/23/2010
STARLadder1 of 4
80se
nsor
dat
a
5JT
AG
, RS
TB
STA
RT
, SP
EA
K, m
arke
r3
Tem
p di
ode
Ana
log,
Dig
pow
er, G
ND
3
sensors
clk,
clk
retu
rn
sensor data
clk, clk returnbu
f pow
er, G
ND
2LVDSbuffer
4
LVDS=>TTL
2 2
PXL Hardware Architecture
L. Greiner 8PXL Sensor and RDO review – 06/23/2010
STAR
80sensor data
5JTAG, RSTB
clk, START, SPEAK,clk return8
Mass Termination Board
Temp diode2
Analog, Dig, buf power, GND5
ana, dig, bufpower, gnd
53
320 sensor data
40JTAG, RSTB
clk, START, SPEAK,clk return
8
Temp diode4
LU senseand reset
LU sense and reset12
gnd1
pwr, gnd 2
pwr,
gnd
in
LVDSbuffer
LVDS=>TTL
marker
ADC
8 marker
x4
x4
x4
x4
x4
x4x4
2LVDSbuffer
LVDSbuffer
PXL Hardware Architecture
L. Greiner 9PXL Sensor and RDO review – 06/23/2010
STAR
V5 Interface Motherboard320 sensor data
40JTAG, RSTB
clk, START, SPEAK, marker, clk return
16
Temp diode4S
IU F
iber
s
gnd1
STA
R T
CD
CM
OS
i/o
LVD
S i/
o
diff
anal
og in
pwr,
gnd
US
B
Virtex-5LVDSbuffer
PMC
Busswitch
LU s
ense
and
res
et
12
TTL =>PECL ADC
QuickUSB
SRAM
Busswitch
PXL Hardware Architecture
L. Greiner 10PXL Sensor and RDO review – 06/23/2010
STARFunctional Data Path – One Ladder
buffer
JTAG, CLK, CTL, markers
buffer
LU protected power
Digital hit data
10 sensors
• After power-on and configuration, the sensors are run continuously. • Triggering is handled in the next stage of the RDO.
1 Ladder
Develop readout electronics (WBS 1.2.2.5)
L. Greiner 11PXL Sensor and RDO review – 06/23/2010
STARFunctional Data Path – Phase-1
• Each received trigger enables an event buffer for one frame.
• The system is dead-time free up to the hardware buffering limit.
Highly Parallel FPGA based RDO system
• 40 sensor outputs/ladder
• 1 sector / RDO board EventBuffer
EventBuffer
1
2
EventBuilder
RDOBuffer
SIU
DAQPC
Disk
80 independent sensor data chains
One per RDO board
address counter (zero suppression)
160 MHzbinary data
160 independent sensor data chains
L. Greiner 12PXL Sensor and RDO review – 06/23/2010
STARFunctional Data Path – PXL Sensor
• 20 sensor outputs/ladder
• 1 sector / RDO board
Highly Parallel FPGA based RDO system
• Same hardware with reconfigured firmware
EventBuffer
EventBuffer
1
2
EventBuilder
RDOBuffer
SIU
DAQPC
Disk
160 MHz Address only data
80 independent sensor data chains
One per RDO board
L. Greiner 13PXL Sensor and RDO review – 06/23/2010
STARRDO System Design – Physical Layout
1-2 mLow mass twisted pair
6 m - twisted pair
Sensors / Ladders / Sectors(interaction point)
LU Protected Regulators,Mass cable termination
RDO Boards
DAQ PCs(Low Rad Area)
DAQ Room
PowerSupplies
Platform 30 m
100 m - Fiber optic30 mControl
PCs
30 m
L. Greiner 14PXL Sensor and RDO review – 06/23/2010
STARPXL RDO Basic Unit
2m6m
RDO PC100m
• 4 ladders per sector• 1 Mass Termination Board (MTB) per sector• 1 sector per RDO board• 10 RDO boards in the PXL system
Develop readout electronics (WBS 1.2.2.5)
L. Greiner 15PXL Sensor and RDO review – 06/23/2010
STAR Ladder Constraints
• 10 sensors to give required eta coverage
• Radiation length budget dedicated to cable/sensor assembly (0.17%) in low mass region.– Sensors thinned to 50 µm (X/X0 ~0.053%)– Al conductor 2 sided cable (X/X0 ~0.08%)
• Mechanical stiffener between cable and sector tube.
• Buffering for all signals to/from ladder.
• Fine twisted pair wire interface to ladders.
L. Greiner 16PXL Sensor and RDO review – 06/23/2010
STAR Ladder Design
The ladder consists of three main elements
10 x sensors
adhesive
Kapton flex cable
adhesive
Carbon fiber stiffener plate
• Thinning sensors to 50 µm is a standard commercial process.• The adhesive is a 50 µm acrylic film adhesive.• The carbon fiber stiffener plate is a basket weave 90º prepreg.• The flex cable is the component that requires a significant
development effort.
L. Greiner 17PXL Sensor and RDO review – 06/23/2010
STAR Flex Cable Development
There are 4 stages to the development process• Stage1 – Infrastructure Testing Board - evaluate the general design
of running 10 sensors on a ladder and find and test the working envelope of bypass capacitance and power supply and ground connection
• Stage 2 – FR-4 ladder cable prototype with Cu - Taking the knowledge gained in the Infrastructure Test Phase, we now attempt to fit the readout cable traces into the required size of the ladder readout cable.
• Stage 3 – Kapton ladder cable prototype with Cu – Translate above design to kapton flex.
• Stage 4 – Kapton ladder cable with Al – production prototype for the final ladder cable.
http://rnc.lbl.gov/hft/hardware/docs/cd1/PXL_flex_cable_and_sys_test_v2.doc
L. Greiner 18PXL Sensor and RDO review – 06/23/2010
STARFlex Cable Development
Low mass Sensor regionDriver region
Side view (exaggerated vertical scale)
Top View
• 2 layer Al conductor cable in low mass region• 0.004” (100 µm) traces and 0.004” (100 µm) spaces• 70% fill factor• Conductor thickness in low mass region is 21 µm (Cu) or 32 µm (Al)• Minimum required conductor trace width 1.325” (33.65 mm) of 46.16 mm available. • Bond wire connection between Al and Cu cable sections.
Low mass region calculated X0 for Al conductor = 0.073 %Low mass region calculated X0 for Cu conductor = 0.232 %
Preliminary Design: Hybrid Copper / Aluminum conductor flex cable
L. Greiner 19PXL Sensor and RDO review – 06/23/2010
STAR MTB Design
• Services 1 sector (4 ladders)• Buffers for all signals to and from ladders• ADC for temperature measurement of sensors• LU protected power daughter-card for each ladder• PLL to regenerate 50% duty cycle clock
L. Greiner 20PXL Sensor and RDO review – 06/23/2010
STARRDO motherboard design constraints
• 320 input data pins for Phase-1/2 sensor data / sector.• 160 input data pins for Final sensor data / sector.• JTAG, sensor CLK, etc. generation.• IODELAY function (Xilinx Virtex).• ALICE DDL interface to STAR DAQ.• STAR trigger interface.• USB interface• Sensor testing capabilities (one development platform)
– 8 ch ADC (50 MHz)– Fast SRAM for full frame event capture– Misc logic inputs for control / triggering (beam tests)
L. Greiner 21PXL Sensor and RDO review – 06/23/2010
STAR RDO motherboard designThe RDO board is a 2 board design
Virtex-5Daughtercard
JTAG interfaceRDO MB int.
RDO Motherboard
Sensor data interfaceSensor control interface
Virtex-5 interfaceSTAR Trigger interface
QuickUSB interfacePMC interface (DDL)
8 ch 50 MHz 12b ADC144Mb SRAM
Auxiliary logic interface
L. Greiner 22PXL Sensor and RDO review – 06/23/2010
STAR RDO motherboard designThe RDO board is a 2 board design
XilinxAFX-FF1760-500
Xilinx XC5VLX330
10,638 Kb block RAM1200 i/o
Custom Motherboard
6 layerStandard PCB “5 on 5”No BGA
L. Greiner 23PXL Sensor and RDO review – 06/23/2010
STARRDO motherboard design comments
• The complete RDO system for PXL consists of 10 RDO motherboard assemblies.
• Investment in a ≥ 16 layer custom RDO motherboard with BGA Xilinx V-5 is not warranted for this quantity.
• Additional testing functionality need not be loaded for production RDO boards.
• This design allows for a single development platform through the full project life cycle.
L. Greiner 24PXL Sensor and RDO review – 06/23/2010
STAR Parts Specifications
MAPS sensorFIN1108 Fairchild LVDS 8 Port RepeaterSN74LVC126A TI Quad Bus buffer gateSN65LVDS2 TI Single LVDS receiver
FIN1108 Fairchild LVDS 8 Port RepeaterSN65LVDT14 TI Interconnect Extender Chipset w/ LVDSSN65LVDT41 TI Interconnect Extender Chipset w/ LVDSAD7997 Analog Devices 8-ch, 10-bit I2C ADCCY7B9950 Cypress 200MHz PLL Clock BufferMIC37152 MICREL 1.5A LDO Voltage RegulatorAD626 Analog Devices single supply diff. amplifierAD8611 Analog Devices single supply comparatorpolyfuses
Ladder components
MTB components
Highradiation
area
Moderateradiation
area
L. Greiner 25PXL Sensor and RDO review – 06/23/2010
STAR Simple Data Rates
Item Number
Bits/address 20
Integration time 200 µs
Luminosity 8 × 1027
Hits / frame on Inner sensors (r=2.5 cm) 246
Hits / frame on Outer sensors (r=8.0 cm) 24
Final sensors (Inner ladders) 100
Final sensors (Outer ladders) 300
Event format overhead TBD
Average Pixels / Cluster 2.5
Average Trigger rate 1 kHz
Item Number
Bits/address 20
Integration time 640 µs
Luminosity 3 × 1027
Hits / frame on Inner sensors (r=2.5 cm) 295
Hits / frame on Outer sensors (r=8.0 cm) 29
Phase-1 sensors (Inner ladders) 100
Phase-1 sensors (Outer ladders) 300
Event format overhead TBD
Average Pixels / Cluster 2.5
Average Trigger rate 1 kHz
Phase-1/2 Final (Ultimate)
Raw data rate from sensors = 32 GB/secData rate to storage = 237 MB/sec Data rate to storage = 199 MB/sec(Scaled to full size detector) (199 kB/event)Note: Data rates for hit data only for Au-Au central collisions including peripheral collision electrons. Sensor noise is not included.
Item Number
Bits/address 20
Integration time 640 µs
Luminosity 3 × 1027
Hits / frame on Inner sensors (r=2.5 cm) 295
Hits / frame on Outer sensors (r=8.0 cm) 29
Phase-1 sensors (Inner ladders) 100
Phase-1 sensors (Outer ladders) 300
Event format overhead TBD
Average Pixels / Cluster 2.5
Average Trigger rate 1 kHz
Item Number
Bits/address 20
Integration time 200 µs
Luminosity 8 × 1027
Hits / frame on Inner sensors (r=2.5 cm) 246
Hits / frame on Outer sensors (r=8.0 cm) 24
Final sensors (Inner ladders) 100
Final sensors (Outer ladders) 300
Event format overhead TBD
Average Pixels / Cluster 2.5
Average Trigger rate 1 kHz
L. Greiner 26PXL Sensor and RDO review – 06/23/2010
STARSummary
• We have a well developed system architecture that is driven by the tracking, mechanical and testing constraints.
• Highly parallel system based on ladder and sector units.
• FPGA based data receiver and processing.
• Leverages commercial Xilinx development boards mated to a custom motherboard.
• Single architectural unit to provide for all required development and testing.
L. Greiner 27PXL Sensor and RDO review – 06/23/2010
STARBackup
L. Greiner 28PXL Sensor and RDO review – 06/23/2010
STARPXL Detector Design
Ladder with 10 MAPS sensors (~ 2×2 cm each)
MAPSRDObuffers/drivers
4-layer kapton cable with aluminium traces
Mechanical support with kinematic mounts
Cabling and cooling infrastructure
Detector extraction at one end of the cone
New beryllium beam pipe (800 µm thick, r = 2.5 cm)
2 layers10 modules4 ladders/module
L. Greiner 29PXL Sensor and RDO review – 06/23/2010
STARSensor Generation and RDO Attributes
Mimostar–2 30 µm pixel, 128 x 128 array1.7 ms integration time1 analog outputMimostar–330 µm pixel, 320 x 640 array2.0 ms integration time2 analog outputsPhase–130 µm pixel, 640 x 640 array640 µs integration time, CDS4 binary digital outputsPXL Sensor (Ultimate)18.4 µm pixel, 1024 x 1088 array≤ 200 µs integration time, CDS,zero suppression2 digital outputs (addresses)
Sensor Sensor RDO
50 MHz readout clockJTAG interface, control infrastructureADCs, FPGA CDS & cluster findingzero suppression ≤ 4 sensor simultaneous readout
160 MHz readout clockJTAG interface, control infrastructurezero suppression40 sensor simultaneous readout
160 MHz readout clockJTAG interface, control infrastructure400 sensor simultaneous readout(full system)
DO
NE
PR
OTO
TYP
ED
Gen
1
1
2
3
L. Greiner 30PXL Sensor and RDO review – 06/23/2010
STARSensor / RDO Services (preliminary)
240 W 180W 300W
1350W (AC)
1100W (AC)
LaddersMTB
Platform(racks)
RDOCrate
DAQ Room
4800 × 42 AWG (TP)160 × 24 AWG (TP)
40 × 0.42” dia. (50 TP cable)20 × 16 AWG
10 × fiber optic cable pair
10 × USB2 × TCD (10 TP)28 × 12 AWG
2m
6m
~100m
PP
~30m
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