MOS-AK meeting, Leuven, September 2004
University of Wales
Power Device Compact Modelling
Phil Mawby
University of Wales Swansea
MOS-AK meeting, Leuven, September 2004
University of Wales
Outline Thermal Compact Models Electrical Compact Models
MOSFET PiN Diode NPTIGBT PTIGBT
Model Validation Examples
MOS-AK meeting, Leuven, September 2004
University of Wales
ET compact models of the semiconductor devices as a connection between electrical and thermal networks
Physically Based Electro-Thermal Compact Modelling Approach
MOS-AK meeting, Leuven, September 2004
University of Wales
Structure diagram of the ET compact model
Electro-Thermal Modelling Strategy
MOS-AK meeting, Leuven, September 2004
University of Wales
Thermal Compact Models – Thermal Networks
Dyna m ic The rm a l Ne two rk
Fo ste r’s ne two rk
C a ue r’s ne two rk
Star-shaped resistance network
RthTj
Pd iss
Tj= Ta + RthPd iss
Tj
Rth1
Rth2
Rth3
Sta tic The rm a l Ne two rk
MOS-AK meeting, Leuven, September 2004
University of Wales
Extraction of the RC Thermal Network Parameters: Thermal Transient Response Function
MOS-AK meeting, Leuven, September 2004
University of Wales
Extraction of the RC Thermal Network Parameters: Thermal Transient Response Function
First step is to obtain thermal transient response function of the device for a step function excitation.
MOS-AK meeting, Leuven, September 2004
University of Wales
Extraction of the RC Thermal Network Parameters: Thermal Transient Response Function
3D FEM prediction of the SML5020BN device temperature distribution after t=1000s
MOS-AK meeting, Leuven, September 2004
University of Wales
Extraction of the RC Thermal Network Parameters: Thermal Transient Response Function
Temperature [oC]
0 20 40 60 80 100 120 140
Dio
de V
olta
ge [m
V]
250
300
350
400
450
500
550
600
SML5020 Internal Diode Temperature Characterisation
MOS-AK meeting, Leuven, September 2004
University of Wales
Deconvolving above equation by the fixed function exp(z-exp(z)), Y(x) spectrum can be extracted from the transient response.
zzzYzAdz
dexpexp
Extraction of the RC Thermal Network Parameters: Deconvolution Method
MOS-AK meeting, Leuven, September 2004
University of Wales
Thermal Transient Response Function: SML5020BN MOSFET
MOS-AK meeting, Leuven, September 2004
University of Wales
Thermal Transient Response Function: STY15NA100 MOSFET
MOS-AK meeting, Leuven, September 2004
University of Wales
Cross sectional view of HEXFETThe introduction of the polysilicon-gate allowed the structure to be self aligned, and allows a cellular structure which increases the packing density.
This increases the active channel to total area ratio significantly compared to rectangular cell or striped structures
Fairly economical process – 6/7 masks cf. 20-28 for CMOS
Note whole of upper surface is coated with Source metal. This makes processing and packaging easier.
Typical cell densities are greater than 2M/in2 (300K/cm2)
Source contact
MOS-AK meeting, Leuven, September 2004
University of Wales
SEM of trench structure
Presented ISPSD 2001
J.Zeng et.al. – Fairchild
Ultra dense trench 1.1m trench spacing – 0.18m.cm2
MOS-AK meeting, Leuven, September 2004
University of Wales
Where does RDS(ON) come from?
N- epitaxial layer
Gate
Source
Rdrift
Rjfet
Rsub
RaRchanRsource
RDS(ON) is made up of the series combination of all the parts of the device between the source and drain where there is a voltage drop
Some of these components are negligible in some voltage ranges
An approximate value can be arrived at using hand calculations.
RDS(ON) = Rsource + Rchan + Ra + Rjfet + Rdrift + Rsub
Drain
Rcontact
Rcontact
Note: all calculation carried out per unit area
MOS-AK meeting, Leuven, September 2004
University of Wales
Electrical Compact Models:Power MOSFET
MOS-AK meeting, Leuven, September 2004
University of Wales
voltage, VDS [V]
0 2 4 6 8 10
drai
n cu
rren
t, I D
[A]
0
5
10
15
20
measurementssimulation
VGS = 4.3V
VGS = 4.8V
VGS = 5.3V
Power MOSFET SML5020BN (Semelab plc.)
MOS-AK meeting, Leuven, September 2004
University of Wales
time, t [s]
0 20 40 60 80 100
Dra
in C
urre
nt [A
]
-5
0
5
10
15
20
25
Dra
in V
olta
ge
[V]
0
100
200
300
400
500
Ga
te V
olta
ge
[V]
0
2
4
6
8
____ simulations____ measurements
Power MOSFET SML5020BN (Semelab plc.)
MOS-AK meeting, Leuven, September 2004
University of Wales
Electrical Compact Models:PiN Diode Compact Model
MOS-AK meeting, Leuven, September 2004
University of Wales
PiN Diode Compact Model: Plasma Decay During Turn-off
0.000 0.002 0.004 0.006 0.008 0.010
0
1
2
3
4
5
6
n- Basep+ n+
1.519s
1.305s
1.122s
0.852s
0.632s
0.502 s
0 s
Base Width (cm)
Exc
ess
Ca
rrie
r C
once
ntr
atio
n (x
10
17cm
-3)
A K
Plasma Shape Prediction: Compact Model
Plasma Shape Prediction: FEM
0 20 40 60 80 100
Exc
ess
Car
rier
Con
cent
ratio
n (c
m-3
)
0
1e+17
2e+17
3e+17
4e+17
5e+17
6e+17
0 s
0.502 s
0.632s
0.852s
1.122s
1.305s
1.519s
MOS-AK meeting, Leuven, September 2004
University of Wales
PiN Diode Compact Model: Diode Turn-off
time, t [s]
0.0 0.1 0.2 0.3 0.4 0.5 0.6
curr
ent,
I A [
A]
-10
-8
-6
-4
-2
0
2
4
6
8
10
12
14
volt
age,
VA
[V
]
-100
-80
-60
-40
-20
0
20
IA, Experiment
IA, Compact model
VA, Compact model
VA, Experiment
Diode BYT 12PI-1000 (ST Microelectronics)
Extracted values of the diode parameters: A=0.1cm-2,
W=0.00632cm, =1.418x10-7s, Nd=1x1014cm-3,Vbi= 1V,
Irp0=1x10-11A, Iln0=1x10-12A, Np= 1x1020 cm-3, = 5x10-5cm
MOS-AK meeting, Leuven, September 2004
University of Wales
Electrical Compact Models:Non Punch Through IGBT Compact Model
MOS-AK meeting, Leuven, September 2004
University of Wales
Electrical Compact Models:Punch Through IGBT Compact Model
MOS-AK meeting, Leuven, September 2004
University of Wales
Electrical Compact Models:NPTIGBT and PTIGBT Compact Model ParametersA Total IGBT active area (cm2)
ADG Gate-drain overlap area (cm2)BVn Breakdown voltage index BVf Breakdown voltage multiplication constantCGS Total gate-source oxide capacitance (nF)COXD Total gate-drain overlap oxide capacitance
(nF)ILN0 Electron end leakage saturation current (A)KPLIN Transconductance in linear region (A/V2)KPSAT Transconductance in saturation region
(A/V2)ND Base region doping density (cm-3)Np Gaussian peak doping density (cm-3)VBI Junction built in potential (V)VTD Gate-drain overlap area threshold voltage
(V)VTH Threshold voltage (V)W Base region width (cm) Channel length modulation parameter (V-1) Transverse field factor (V-1) Doping spreading factor (cm) Ambipolar lifetime (s)
P Hole lifetime inside the buffer layer (s)WB Buffer layer width (cm) nF Emitter efficiencyNB Buffer layer doping density (cm-3)
MOS-AK meeting, Leuven, September 2004
University of Wales
IGBT Compact Model: Clamped Inductive Load Circuit – Gate Controlled Turn-off
Value for the Vaa is chosento be greater (500V) than themaximum clamping voltageVclamp (300V).
Clamp inductive load circuit
MOS-AK meeting, Leuven, September 2004
University of Wales
Clamped Inductive Load Circuit – Gate Controlled Turn-off: At the beginning of the turn-off process, as soon as gate voltage decreases below VTH the MOS channel is turned-off. Then, the channel current (Ich), which is an electron current, decreases abruptly and the anode voltage starts to rise. When the anode voltage reaches the clamp voltage (VA = Vclamp), it stays constant. The remaining current tail will decay with a longer time constant via carrier recombination and diffusion. As suggested by the arrow, the higher the clamping voltage (Vclamp) the higher will be the initial current tail size.
time [s]
16 17 18 19 20 21 22 23 24
anod
eCur
rent
[A]
0
1
2
3
4
5
6
7
8
Vclamp = 100V
Vclamp = 200V
Vclamp = 300V
time [s]
16 17 18 19 20 21 22 23 24
an
od
eV
olta
ge
[V]
0
50
100
150
200
250
300
350
Vclamp = 100V
Vclamp = 200V
Vclamp = 300V
Simulated NPTIGBT anode current and voltage turn-off waveforms
MOS-AK meeting, Leuven, September 2004
University of Wales
Clamped Inductive Load Circuit – Gate Controlled Turn-off:
Carrier concentration at the left (anode) plasma edge decay during NPTIGBT turn-off - carrier concentration decreases monotonically during turn-off
time [s]
14 15 16 17 18 19 20 21 22
p l [cm
-3]
0.0
2.0e+16
4.0e+16
6.0e+16
8.0e+16
1.0e+17
1.2e+17
1.4e+17
1.6e+17
NPTIGBT
Vclamp = 200V
MOS-AK meeting, Leuven, September 2004
University of Wales
Clamped Inductive Load Circuit – Gate Controlled Turn-off:
Simulated PTIGBT anode current and voltage turn-off waveforms –
PTIGBT has a shorter turn-off time than a corresponding NPTIGBT since the carriers are cleared away from the PTIGBT base by the depletion region as it reaches the buffer layer.
time [s]
16 17 18 19 20 21
ano
deC
urr
ent [
A]
0
1
2
3
4
5
6
7
8
Vclamp = 100V
Vclamp = 200V
Vclamp = 300V
time [s]
16 17 18 19 20 21
anod
eVol
tage
[V]
0
50
100
150
200
250
300
350
Vclamp = 100V
Vclamp = 200V
Vclamp = 300V
MOS-AK meeting, Leuven, September 2004
University of Wales
IRG4BC20UD (International Rectifier) IGBT
Turn-On
time [s]
0.0 0.1 0.2 0.3 0.4 0.5 0.6
VA [
V]
-100
0
100
200
300
400
500
I A [
A]
-3
0
3
6
9
12
15
-------Experiment
-------Compact Model
Anode current and voltage turn-on waveforms
Turn-Off
time [s]
0.0 0.1 0.2 0.3 0.4 0.5 0.6
VA [
V]
-100
0
100
200
300
400
500
I A [A
]
-3
0
3
6
9
12
15
-------Experiment
-------Compact Model
Anode current and voltage turn-off waveforms
MOS-AK meeting, Leuven, September 2004
University of Wales
ET PiN Diode Simulation
MOS-AK meeting, Leuven, September 2004
University of Wales
ET PiN Diode Simulation
Anode Current vs. time
Anode Voltage vs. time
MOS-AK meeting, Leuven, September 2004
University of Wales
Step-Up Converter: Schematic of an Electro-Thermal Model
f=20kHz
MOS-AK meeting, Leuven, September 2004
University of Wales
Step-Up Converter: Drain Voltage Vs. Time
MOS-AK meeting, Leuven, September 2004
University of Wales
Step-Up Converter: Output Voltage and Junction Temperature
MOS-AK meeting, Leuven, September 2004
University of Wales
Synchronous Buck Converter: Topology and Typical Power Losses
+
Vin
Q 1
Q 2
L
C
R
Vo
+
C o ntro l FET Q 1 36%
Sync hro no us FETQ 2 23%
inp ut c a p a c ito r30%
ind uc to r 10%m isc e lla ne o us 1%
MOS-AK meeting, Leuven, September 2004
University of Wales
Isolated Forward Converter: Topology and Typical Power Losses
+
Vin
Q s1
L
C
RVo
+
Q p
Q s2
N:1
Prim a ry M O SFET16%
Se c o nd a ry M O SFETs35%
tra nsfo rm e r22%
ind uc to r 10%m isc e lla ne o us 8%
b ia s 9%
MOS-AK meeting, Leuven, September 2004
University of Wales
Conclusions
MOSFET model is simple cf. deep sub micron
Electro Thermal interactions are keyBipolar Plasma modelling is very
challengingLong real times for simulations
MOS-AK meeting, Leuven, September 2004
University of Wales
Aknowledgement
Thanks to Dr.P.Igic
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