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JTAG
AN IEEE 1149.1 STD
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OVERVIEW
In today's complex systems, testability is an increasingconcern in almost every application and in every areaof application development. Manufacturers thatthoroughly address the issue of testability at the
device, board, and system levels deliver moreconsistently reliable and cost-effective products to themarketplace.
This means building in test capabilities in every phase
of development and deployment, including designverification, hardware and software integration,manufacturing, and in the field.
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JTAG HISTORY In the 1980s, the Joint Test-Action Group (JTAG) formed by representatives from
makers and users of components and boards, recognized that only a cooperativeeffort could address the mounting testability problems in a coordinated way.
Its mandate was to propose design structures that semiconductor makers wouldincorporate into device designs to aid in testing boards and systems.
In 1990 the IEEE adopted the proposal as IEEE Standard 1149.1-1990- BOUNDARY
SCAN. Its stated purpose was to test interconnections between Integrated Circuits (ICs)
installed on boards, modules, hybrids, and other substrates. Manufacturersadopting the standard could also test the IC itself .
In 1993 a new revision to the IEEE Std. 1149.1 standard was introduced (titled1149.1a) and it contained many clarifications, corrections, and enhancements. In1994, a supplement containing a description of the Boundary-Scan Description
Language (BSDL) was added to the standard. Since that time, this standard hasbeen adopted by major electronics companies all over the world.
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Applications are found in high volume, high-endconsumer products, telecommunicationproducts, defense systems, computers,peripherals, and avionics. In fact, due to its
economic advantages, some smaller companiesthat cannot afford expensive in-circuit testers areusing boundary-scan.
The boundary-scan test architecture provides a
means to test interconnects between integratedcircuits on a board without using physical testprobes.
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What is boundary-scan?
Boundary-scan, as defined by the IEEE Std.-1149.1standard, is an integrated method for testinginterconnects on printed circuit boards (PCBs) that areimplemented at the integrated circuit (IC) level.
The inability to test highly complex and dense printed
circuit boards using traditional in-circuit testers andbed of nail fixtures was already evident in the mideighties.
Due to physical space constraints and loss of physicalaccess to fine pitch components and BGA devices,fixturing cost increased dramatically while fixturereliability decreased at the same time.
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DIGITAL BOUNDARY SCAN (IEEE Std.
1149.1)
Basic Concept Standard 1149.1 defines a test access protocol and a
boundary-scan architecture for digital integratedcircuits and the digital portions of mixed
analog/digital integrated circuits. the name boundary scan is due to the insertion ofa
boundary-scan cell to each I/O pin of the originalcircuit and the chaining of these cells into a shiftRegister called the boundary-scan register.
Chips complying with this standard can be readilyintegrated into a PCB with their I/O accessible throughthe boundary-scan registers.
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JTAG ARCHITECTURE
Architecture IEEE Standard 1149.1 is a testing standard.
However it is described as a collection of design rulesapplied principally at the IC level that allow software toalleviate the growing cost of designing and producingdigital systems. The primary benefit of the standard isits ability to transform extremely difficult printedcircuit board testing problems that could be attackedwith ad-hoc testing methods into well-structured
problems that software can easily and swiftly dealwith.
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BOUNDARY SCAN HARDWARE
The boundary-scan circuitry can be divided into four mainhardware
components:
A test access port (TAP), which consists of four mandatory
terminals
test data input (TDI), test data output (TDO),test mode select (TMS), and test clock (TCK)and oneoptional terminal, test reset (TRST)
A TAP controller (TAPC)
An instruction register (IR) and its associated decoder
Several test data registers, including the mandatoryboundary-scan registerand bypass register, and someoptional miscellaneous registers, such as the device-IDregister, and some design-specific test data registers.
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BOUNDARY SCAN ARCHITECTURE
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The test access port, which defines the bus protocol of the boundary scan, consistsof additional I/O pins necessary for each chip employing the standard.
The TAP controller is a 16-state, finite-state machine that controls each step of theboundary-scan operations. Each instruction to be carried out by the boundary-scan
architecture must be serially loaded into the instruction register through the test
data input (TDI) pin. The test signals to configure the boundary-scan-related testhardware for the current test instruction are provided by the associated decoder.
The test data registers are used to store test data or some system-relatedinformation (such as the chip ID, company name, etc.).
(such as the chip ID, company name, etc.).
In addition to the hardware components, IEEE Std. 1149.1 also defines a set of
test instructions, including four mandatory ones (BYPASS, SAMPLE, PRELOAD,
and EXTEST) and several optional ones, including INTEST, RUNBIST, CLAMP,
IDCODE, USERCODE, and HIGHZ. It also allows the users to define their own
instructions.
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TYPICAL TEST PROCEDURE
A boundary-scan test instruction is shifted intothe IR through the TDI.
The instruction is decoded by the decoderassociated with the IR to generate the requiredcontrol signals so as to properly configure the testlogic.
A test pattern is shifted into the selected dataregister through the TDI and then applied to the
logic to be tested. The test response is captured into some data
register.
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The captured response is shifted out through
the TDO for observation and, at the same
time, a new test pattern can be scanned in
through the TDI.
Steps 3 to 5 are repeated until all test patterns
are shifted in and applied, and all test
responses are shifted out.
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Test Access Port and Bus Protocols
Test clock input
(TCK) is a clock input to synchronize the test operationsbetween the various parts of a chip or between differentchips on a PCB.
This input must be independent of the system clocks sothe serial test data path between components of a chip ordifferent chips can be used independently of the systemclocks, which may vary significantly in frequency from onecomponent to another; so the board interconnect testingcan be properly carried out; and so the shifting and
capturing of test data can be executed concurrently withnormal system operation, thereby facilitating onlinesystem monitoring for a design without changing thestate of the on-chip system logic.
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Test data input
is an input to allow test instructions and test
data to be serially loaded into the instruction
register and the various test data registers,
respectively.
Values presented at TDI are clocked into the
selected register on a rising edge of TCK.
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Test data output
TDO) is an output to allow various test data to
be driven out.
changes in the state of the signal driven
through TDO should occur only on the falling
edge of TCK.
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Test mode select (TMS) is the sole test controlinput to the TAP controller.
All boundary-scan test operations such as
shifting, capturing, and updating of test data arecontrolled by the test sequence applied to thisinput.
Signals presented at TMS are sampled by the TAP
controller on the rising edge of TCK. This input should also be driven to logic 1 when it
is inactivated.
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Test reset (TRST) is an optional pin used to reset the TAPcontroller.
TRST pin is implemented, the TAP controller can beasynchronously reset to the TestlogicReset controllerstate when a logic 0 is applied at TRST.
This in turn will reset other boundary-scan logic to the staterequired by the TestLogicReset state.
This pin should not be used to reset the system logic so thetest logic can be reset independently of the on-chip system
logic. If this input is omitted, the system must have some circuitry
that can reset the TAP controller during power-on.
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BOUNDARY-SCAN REGISTER (BSR)
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TAP Controller
The TAP controller (TAPC) is a 16-state, finite-statemachine added on the IC die itself.
It recognizes the communication protocol and generatesinternal control signals used by the remainder of theBoundary Scan logic.
It recognizes the communication protocol and generatesinternal control signals used by the remainder of theBoundary Scan logic.
The TAP controller is driven by TCK and TMS only; no
other signals affect TAP controller. They program the TAPController as a 16-state machine, generating clock andcontrol signals for the instruction and data registers.
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Only two events can trigger a change of controller state:
a test-clock rising edge,
system power-up.
Movement through the state machine is controlled by thevalue of TMS, a set-up time prior to the rising edge of
TCK. The 1s and 0s adjacent to each state transitionarc show the value that must be present on TMS atthe time of the next rising edge of TCK
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The main functions of the TAPC include:
Resetting the boundary-scan architecture
Providing control signals to load instructions into
the instruction register
Providing signals to perform test functions such
as Capture and Update (application) of test data
Providing control signals to shift test data fromTDI to TDO
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The 16 states can be divided into three parts.
The first part (the 2 states at left)
contains the reset and the Run-Test/Idle states,
the second (the 7 states in the middle) and third(the 7 states at right) parts control the operations
of the data and instruction registers, respectively.
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JTAG TAP State definitions
Test-Logic-Reset For a target device in the stable Test-Logic-Reset state, the test
logic is reset and is disabled so that the normal logic function ofthe device is performed. The instruction register is reset to anopcode that selects the optional IDCODE instruction, if
supported, or the BYPASS instruction. Certain data registers alsocan be reset to their power-up values.
Whenever a 0 signal is applied to the TRSTport, the TAPCenters this state.
The TAPC can also be synchronously reset; whatever state
the TAP controller is in, it will return to this state if a logic 1is applied to TMS for five consecutive TCK cycles (i.e., fiverising edges of TCK).
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Run-Test/Idle
For a target device, Run-Test/Idle is a stable
state in which the test logic can be actively
running a test or can be idle.
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Select-DR-Scan, Select-lR-Scan
For a target device, no specific function is
performed in the Select-DR-Scan and Select-
lR-Scan states, and the TAP controller exits
either of these states on the next TCK cycle.These states allow the selection of either data-
register scan or instruction-register scan.
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Capture-DR
For a target device in the Capture-DR state,
the selected data register can capture a data
value as specified by the current instruction.
Such capture operations occur on the risingedge of TCK, upon which the Capture-DR state
is exited.
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Shift-DR
For a target device, upon entry to the Shift-DRstate, the selected data register is placed inthe scan path between TDI and TDO, and on
the first falling edge of TCK, TDO goes fromthe high-impedance state to an active state.TDO outputs the logic level present in theleast-significant bit of the selected data
register. While in the stable Shift-DR state,data is shifted serially through the selecteddata register on each TCK cycle.
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Exit1-DR, Exit2-DR
For a target device, the Exit1-DR and Exit2-DR
states are temporary states that end a data-
register scan. It is possible to return to the
Shift-DR state from either Exit1-DR or Exit2-DRwithout recapturing the data register. On the
first falling edge of TCK after entry to Exit1-DR,
TDO goes from the active state to the high-impedance state.
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Pause-DR
For a target device, no specific function is
performed in the stable Pause-DR state. The
Pause-DR state suspends and resumes data-
register scan operations without loss of data.
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Update-DR
For a target device, if the current instruction
calls for the selected data register to be
updated with current data, such update
occurs on the falling edge of TCK, followingentry to the Update-DR state.
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Capture-IR
For a target device in the Capture-IR state, the
instruction register captures its current status
value. This capture operation occurs on the
rising edge of TCK, upon which the Capture-IRstate is exited.
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Shift-IR
For a target device, upon entry to the Shift-IRstate, the instruction register is placed in thescan path between TDI and TDO, and on the
first falling edge of TCK, TDO goes from thehigh-impedance state to an active state. TDOoutputs the logic level present in the least-significant bit of the instruction register. While
in the stable Shift-IR state, instruction data isshifted serially through the instruction registeron each TCK cycle.
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Exit1-IR, Exit2-IR
For a target device, the Exit1-IR and Exit2-IR
states are temporary states that end an
instruction-register scan. It is possible to
return to the Shift-IR state from either Exit1-IRor Exit2-IR without recapturing the instruction
register. On the first falling edge of TCK after
entry to Exit1-IR, TDO goes from the activestate to the high-impedance state.
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Pause-IR
For a target device, no specific function is
performed in the stable Pause-IR state, in
which the TAP controller can remain
indefinitely. The Pause-IR state suspends andresumes instruction-register scan operations
without loss of data.
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Update-IR
For a target device, the current instruction is
updated and takes effect on the falling edge of
TCK, following entry to the Update-IR state.
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