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Introduction to the
ThumbInstruction Set
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History The 4th generation of ARM cores came out in 1996. The
main innovation in this version of the architecture wassupport for Thumb 16-bit compressed instruction set.
Thumb code takes 40% less space compared to regular32-bit ARM code but is slightly less efficient.
In 1999, the 5th generation of the ARM architectureintroduced digital signal processing and Java byte codeextensions to the ARM instruction set. The mostpopular implementation of this architecture is the IntelXScale processor. It is used in a variety of high-endembedded devices, including network processors,
smart-phones. The 6th generation of the ARM architecture was
released in 2001 introducing SIMD instruction setextension, improved Thumb instruction set andmultiprocessor support.
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What is Thumb?
Thumb is a compressed, 16-bitrepresentation of a subset of theARM instruction set
primarily to increase codedensity
also increases performance insome cases
It is not a complete architecture allThumb-aware cores also supportthe ARM instruction set
therefore the Thumb
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The Thumb bit
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Thumb provides a subset of the mostcommonly used 32-bit ARM instructionswhich have been compressed into 16-bitwide opcodes. On execution, these 16- bit instructionscan be either decompressed to full 32-
bit ARM instructions or executed directlyusing a dedicated Thumb decoding unit Although Thumb code uses 40% more
instructions than equivalent 32-bit ARMcode, it typically requires 30% lessspace. Thumb code is 40% slower than ARMcode; therefore Thumb is usuall used
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Example
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BLX v2 branch with link andexchange
BX v1 branch with exchange
CMN v1 compare negative two32-bit values
CMP v1 compare two 32-bitintegers
EOR v1 logical exclusive OR oftwo 32-bitvalues
LDM v1 load multiple 32-bitwords from
memory to ARM
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LDR v1 load a single value from a
virtual addressin memory
LSL v1 logical shift left
LSR v1 logical shift right
MOV v1 move a 32-bit value into aregister
MUL v1 multiply two 32-bit values
MVN v1 move the logical NOT of 32-bit value into
a register
NEG v1 negate a 32-bit value
ORR v1 logical bitwise OR of two 32-
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PUSH v1 pushes multiple registersto the
stack ROR v1 rotate right a 32-bit value SBC v1 subtract with carry a 32-
bitvalue
STM v1 store multiple 32-bitregisters to
memory STR v1 store register to a virtual
address inmemory
SUB v1 subtract two 32-bit values
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ARM-ThumbInterworking ARM-Thumb interworking is the name given to
the method of linking ARM and Thumb codetogether for both assembly and C/C++.
It handles the transition between the twostates. Extra code, called a veneer, is
sometimes needed to carry out the transition. ATPCS defines the ARM and Thumb procedurecall standards.
To call a Thumb routine from an ARM routine,the core has to change state. This state change
is shown in the T bit of the cpsr. The BX and BLX branch instructions cause a
switch between ARM and Thumb state whilebranching to a routine. The BX lr instruction
returns from a routine, also with a state switchif necessary.
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There are two versions of the BX or BLXinstructions: an ARM instruction and a Thumbequivalent.
The ARM BX instruction enters Thumb state only ifbit 0 of the address in Rn is set to binary 1;otherwise it enters ARM state. The Thumb BXinstruction does the same.
Syntax: BX Rm
BLX Rm | label
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InstructionsSyntax:
Rd, Rm
Rd, Rn #immediate
Rd,#immediate
Rd,Rn,Rm
ADD Rd,pc,#immediate
ADD Rd,sp,#immediate
sp, #immediate
Rd,Rs
Rn,Rm
CMP Rn,#immediate
MOV Rd,Rn
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Single-Register Load-Store
Instructions
Syntax: {} Rd, [Rn,#immediate]
LDR{} Rd,[Rn,Rm]
STR{} Rd,[Rn,Rm]
LDR Rd,[pc,#immediate]
Rd,[sp,#immediate]
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Multiple-Register Load-storeInstructions
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Stack Instructions
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Software InterruptInstruction
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Thumb Decoding
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