1
FYSE400 ANALOG ELECTRONICS
LECTURE 4
FET Circuits
2
DISCRETE COMPONENT FET
FET (Field-Effect Transistor)
MOSFET (Metal-Oxide_Semiconductor FET)
Enhancement-modeDepletion-mode
P-channelN-channel P-channelN-channel
JFET (Junction Field-Effect Transistor)
Depletion-mode
P-channelN-channel
p-channeln
n
Drain
Source
Gate
n-channelp p
Drain
Source
Gate
D
S
G
D
S
G
p-substrate
n
n
D
S
G
D
SG
©Loberg University of Jyväskylä
3
Drain voltage
Supply Quisent ac instant ac rms ac+dc instant ac+dc average
Drain current
Gate voltage
Gate current
Source voltage
Source current
DDV DQV dv dV Dv DV
DDI DQI di dI Di DI
GGV GQV gv gV Gv GV
GGI GQI gi gI Gi GI
SSV SQVsv sV Sv SV
SSI SQI si sI Si SI
Symbols in FET-amplifiers
DISCRETE COMPONENT FET
©Loberg University of Jyväskylä
4
JFETDISCRETE COMPONENT FET
n-channel
Drain
Source
Gatep p
VGG1
0+-
ID1
0+-
--
+
+
VDD
Drain
Source
Gatep p
VGG2
0+-
ID2
0+-
--
+
+
VDD
n-channel
A biased n-channel JFET
1D2D1GG2GG IIVV
Large signal analysis
©Loberg University of Jyväskylä
5
DISCRETE COMPONENT FET JFET
A biased n-channel JFET
DSSI
VDS
VGS= 0V
0IVV D)off(GSGS
Vp
ID
VGS= -1V
Pinch-off when VGS= -1V
Breakdown
Drain Characteristic Curve
Breakdown p)off(GS VV
Pinch-off voltageVp when VGS=0
Cutoff voltage VGS(off)
0VV GS)off(GS DSSD II0
Input range for VGS when VDS > Vp
Large signal analysis
©Loberg University of Jyväskylä
6
DISCRETE COMPONENT FET JFET
A biased n-channel JFET
Pinch-off voltage Vp
Family of drain characteristic curves for 2N5484
2N5484
VGS= 0V
VGS= -0.2V
VGS= -0.4V
VGS= -0.6V
VGS= -0.8V
VGS= -1V
VDS
Assumption: VGS= 0V
Ohmic region
Breakdown
V1.1V )off(GS
DSSI
Active region
Example of typical rf JFET 2N5484
Large signal analysis
Active operation region
©Loberg University of Jyväskylä
Data sheet of 2N5484
7
VGS
0
VDS
IDID
-0.2-0.4-0.6-0.8-1-1.2
Transfer characteristic curve for
2N5484 when VDS = 3V.
V15.1V )off(GS
DSSIVGS= 0V
VGS= -0.2V
VGS= -0.4V
VGS= -0.6V
VGS= -0.8V
DISCRETE COMPONENT FET
A biased n-channel JFET
JFET
Example of typical rf JFET 2N5484
2
)off(GS
GSDSSD
V
V1II
Approximation
The slope of drain characteristic
in active region is zero.
Example : VGS(off) = -1.15V and -1V < VGS < 0
Large signal analysisActive region
©Loberg University of Jyväskylä
8
DISCRETE COMPONENT FET
A biased n-channel JFET
JFET
Large signal analysisActive region
The four basic biasing schemes
Self bias Voltage-divider bias Constant current-source bias Constant voltage bias
D
S
G
DR
GR
DDV
N
D
SG
DR
GR SR
DDV
N
0VGN
D
S
G
DR
2R SR
DDV
N
1R
D
SG
DR
GR
DDV
N
GGV
©Loberg University of Jyväskylä
9
DISCRETE COMPONENT FET JFET
A biased n-channel JFET Large signal analysis
SELF-BIAS
D
S
G0VGN
DR
GR SR
DDV
SQI
N
00VRI GSQSSQ
0RIVRIV SSQDSQDDQDD
DQSQ II
SDQGSQ RIV
SDDQDDDSQ RRIVV
0IGQ
Active region
©Loberg University of Jyväskylä
10
DISCRETE COMPONENT FET JFET
A biased n-channel JFET Large signal analysis
SELF-BIAS
Transfer characteristic curve for
2N5484 when VDS = 3V.
VGS0
ID [mA]
-0.2-0.4-0.6-0.8-1-1.2
0.5
1.5
2.5
3.5
1.4 mA
DQGSQSSDQGSQ IVRRIV
S
DQ
DSQDD
D RI
VVR
JFET 2N54842
)off(GS
GSQ
DSSDQV
V1II
If we know parameters VGS(off) and IDSS , we can
solve VGSQ by using the following equation.
Or graphical analysis : We can solve VGSQ by using the
transfer characteristic curve.
GS
S
D VR
1I
Self-bias dc LOAD LINE
Active region
©Loberg University of Jyväskylä
11
DISCRETE COMPONENT FET
A biased n-channel JFET Large signal analysis
JFET
Transfer characteristic curve for
2N5484 when VDS = 3V.
VGS0
ID [mA]
-0.2-0.4-0.6-0.8-1-1.2
0.5
1.5
2.5
3.5
1.4 mA
JFET 2N5484
SELF-BIAS EXAMPLE
VDSQ= 3VAssumptions :
Typically mA4.1I2
1I DSSDQ
V15.1V )off(GS mA3IDSS
V364.013
4.1V15.1VGSQ
260mA4.1
V364,0RS
k9.1260mA4.1
VV6R
DSQ
D
Active region
©Loberg University of Jyväskylä
12
DISCRETE COMPONENT FET
A biased n-channel JFET Large signal analysis
JFET
VOLTAGE-DIVIDER BIAS
SQDQ II D
S
G0VGN
DR
2R SR
DDV
SQI
N
1R
SNV
DQII
DD
21
2GN V
RR
RV
GSGNSN VVV
On biaspoint Q :
2
)off(GS
GSQ
DSSDQV
V1II
SGSGND RVVI
DSS
DQ
)off(GSGSQI
I1VV
0RRIVV SDDDSDD
GS
S
GN
S
D VR
1V
R
1I
Voltage-divider bias dc LOAD LINE
Active region
©Loberg University of Jyväskylä
13
V364.0I
I1VV
DSS
DQ
)off(GSGSQ
V036.1VRIVRVVI GSQSDQGNQSGSQGNQDQ
V4.1RIV SDQSNQ
M68.7V036.1
V036.1V9M1
V
VVRRV
RR
RV
GNQ
GNQDD
21DD
21
2GN
k29.3k1mA4.1
V3V9R
I
VVR0RRIVV S
DQ
DSQDD
DSDDDSDD
DISCRETE COMPONENT FET
A biased n-channel JFET Large signal analysis
JFET
VOLTAGE-DIVIDER BIAS EXAMPLE
Active region
©Loberg University of Jyväskylä
VDSQ= 3VAssumptions :
Typically mA4.1I2
1I DSSDQ
V15.1V )off(GS mA3IDSS
k1RS M1R2
14
mA4.1IDQ
V3VDSQ
k1RS
Assumptions :
V036.1VGNQ
VVSNQ 4.1
V364.0VGSQ
k29.3RD
M68.7R1
Calculated
values:
DISCRETE COMPONENT FET
A biased n-channel JFET Large signal analysis
JFET
VOLTAGE-DIVIDER BIAS EXAMPLE
Active region
©Loberg University of Jyväskylä
M1R2
Simulated bias point values
2R
1R
SR
DR
15
Transfer characteristic curve for
2N5484 when VDS = 3V.
VGS0
ID [mA]
-0.2-0.4-0.6-0.8-1-1.2
0.5
1.5
2.5
3.5
1.4 mA
JFET 2N5484
mA04.1R
VI
S
GND
V04.1VV GNGS
Large signal analysis
Graphical analysis
DISCRETE COMPONENT FET
A biased n-channel JFET
JFET
VOLTAGE-DIVIDER BIAS EXAMPLE
GS
S
GN
S
D VR
1V
R
1I
Active region
©Loberg University of Jyväskylä
16
Large signal analysis
DISCRETE COMPONENT FET
A biased n-channel JFET
JFET
CONSTANT CURRENT-SOURCE BIAS
Active region
D
S
G0VGN
DR
GR
OR
DDV
mA4.1ISQ
N
0IGQ
Assumption :
Ideal current-source
Constant ID=1.4 mA
Constant VDN
Limited to source follower type applications
Current-source must be bypassed with capacitor
to get drain ac-signal.
VGS0
ID [mA]
-0.2-0.4-0.6-0.8-1-1.2
0.5
1.5
2.5
3.5
1.4 mA
JFET 2N5484
Slope = 0
Full bypass
©Loberg University of Jyväskylä
17
Large signal analysis
DISCRETE COMPONENT FET
A biased n-channel JFET
JFET
CONSTANT CURRENT-SOURCE BIAS EXAMPLE
Active region
Output: DRAIN signal
Bypass capacitor
Simulation with BYPASS CAPACITOR
Input: GATE ac-signal Vpp= 20mV
©Loberg University of Jyväskylä
18
Large signal analysis
DISCRETE COMPONENT FET
A biased n-channel JFET
JFET
CONSTANT CURRENT-SOURCE BIAS EXAMPLE
Active region
Simulation without BYPASS CAPACITOR
Input: GATE
ac-signal Vpp= 20mV
Output: DRAIN
ac-signal Vpp=0
Output: SOURCE
ac-signal Vpp= 20mV
©Loberg University of Jyväskylä
19
D
SG
DR
GR
DDV
N
GGV
Large signal analysis
DISCRETE COMPONENT FET
A biased n-channel JFET
JFET
CONSTANT VOLTAGE BIAS
Active region
VGS0
ID [mA]
-0.2
-0.4
-0.6-0.8-1-1.2
0.5
1.5
2.5
3.5
1.4 mA
JFET 2N5484
Bias dc LOAD LINE
GGV
DRAIN VOLTAGE VDQN = 4.34V
DRAIN CURRENT IDQ = 1.42mA
N
©Loberg University of Jyväskylä
20
Large signal analysis
DISCRETE COMPONENT FET
Q-Point Stability of a biased n-channel JFET
JFET
The transfer characteristic of JFET can differ considerably from one device to another of same type.
Datasheet 2N5484
Active region
©Loberg University of Jyväskylä
21
Large signal analysis
DISCRETE COMPONENT FET
Q-Point Stability of a biased n-channel JFET
JFET
Transfer characteristic curve for
2N5484
VGS
0
ID [mA]
-0.5-1.5-2-2,5-3
2
4
5
2DI
1GSV
3
11DI
1DI
biasdividervoltageDbiasselfD II
2Q
1Q
1Q
mA5I (max)DSS
mA1I (min)DSS
1GSV2GSV
-1
The drain current IDQ is much more stable with VOLTAGE-DIVIDER bias.
Active region
©Loberg University of Jyväskylä
22
Large signal analysis
DISCRETE COMPONENT FET
Q-Point Stability of a biased n-channel JFET
JFET
Active region
SELF-BIAS WITH CURRENT-SOURCE
The drain current IDQ is essentially independent of VGS .
Increased Q-point stability.
Biasing with the constant-current source.
D
S
G0VGN
DR
GR
DDV
SQI
N
DQI
Transfer characteristic curve for
2N5484
VGS
0
ID [mA]
-0.5-1.5-2-2,5-3
2
4
5
3
12Q 1Q
mA5I (max)DSS
mA1I (min)DSS
V3V (max)GSoff
-1
V3.0V (min)GSoff
Note!
©Loberg University of Jyväskylä
23
DISCRETE COMPONENT FET
Large signal analysis
JFET
Active region
DQ
E
EE
E
BEEEE I
R
V
R
VVI
BEEE VV
0VRIV EEEEBE
D
S
G0VGN
DR
GR
DDV
EI
DQI
ER
EEV
N
SELF-BIAS WITH CURRENT-SOURCE EXAMPLE
Q-Point Stability of a biased n-channel JFET
©Loberg University of Jyväskylä
24
DISCRETE COMPONENT FET
Large signal analysis
JFET
Active region
SELF-BIAS WITH CURRENT-SOURCE EXAMPLE
Q-Point Stability of a biased n-channel JFET
mA4.1k10
V7.0V7.14
R
VVI
E
BEEEE
VD = 4.40V
IDQ = 1.40mA
©Loberg University of Jyväskylä
25
DISCRETE COMPONENT FET
Large signal analysis
JFET
A biased n-channel JFET Ohmic region
Ohmic region
Slope
DS
DDS
V
IG
DSD
DSDS
G
1
I
VR
Drain-to-source resistance
Drain-to-source resistance is controlled by VGS .VDS
0V 1GS
0V 2GS
2GS3GS VV
3GS4GS VV
ID
Increasing RDS
©Loberg University of Jyväskylä
26
DISCRETE COMPONENT FET Enhancement-mode MOSFET
MOSFET (Metal Oxide Semiconductor Field-Effect Transistor)
Avaustyyppinen
Drain characteristics with
Channel-Length Modulation
n-channel
D
S
G
Drain characteristics of
n-channel enhancement MOSFETDSV
Ohmic region (Linear)
Saturation
region
DI
Subthreshold
Boundary
TOGS VV p-channel
D
S
G
Large signal analysis
©Loberg University of Jyväskylä
27
Ohmic Region
2
DSDSTOGSD VVVV2L
WkI
DSTOGS VVV
Boundary Region
2
DSD VL
WkI
DSTOGS VVV
DS
2
TOGSDS V1VVL
WkI
Saturation RegionDSTOGS VVV
W/L = aspect ratio
W = channel width
L = channel length
VTO = threshold voltage
k = process parameter
Typical values of parameter k
25010 VAto
0nC2
1k
µn = electron mobility
C0 = gate capacitance per unit area fF/µm2
Early voltage = 1/λ
DISCRETE COMPONENT FET Enhancement-mode MOSFET
MOSFET (Metal Oxide Semiconductor Field-Effect Transistor)
Avaustyyppinen
Large signal analysis
©Loberg University of Jyväskylä
28
DISCRETE COMPONENT FET
MOSFET (Metal Oxide Semiconductor Field-Effect Transistor)
Ohmic Region
2
DSDSTOGSD VVVV2L
W
2
KPI
DSTOGS VVV
SPICE MODEL
2TOGSDS VVL
W
2
KPI
Saturation RegionDSTOGS VVV
DS
2
TOGSDS V1VVL
W
2
KPI
Saturation Region with channel-length
modulation
(large signal)
Typical values :
VTO = 0.7V KP = 30 µA/V2
0nCKP
Enhancement-mode MOSFET
©Loberg University of Jyväskylä
29
Sulkutyyppinen
DI
DSV
Ohmic region (Linear)
Saturation
(Forward active)
Boundary
0VGS
0VGS
0V 1GS
1GS2GS VV
Drain characteristics of
n-channel depletion MOSFET
Depletion-mode MOSFET
MOSFET (Metal Oxide Semiconductor Field-Effect Transistor)
DISCRETE COMPONENT FET
n-channel
D
S
G
p-channel
D
S
G
Large signal analysis
©Loberg University of Jyväskylä
30
DISCRETE COMPONENT FET
Avaustyyppinen
Biasing MOSFET EXAMPLE
G
D
S
R1
R2 RS
RD
VDD
Assumption: Early Voltage is very high, λ=0
Bias point in the Saturation RegionDSTOGS VVV
2VA30KP 1LW
B21 Rk100RR
0IGG
820RS
V12VDD
Enhancement-mode MOSFET
D
SVGSQ
VGG
IGGRB
IDQ
SR
Large signal analysis
©Loberg University of Jyväskylä
31
DISCRETE COMPONENT FET
A420VVL
W
2
KPI
2
TOGSQDQ
0RIVV SDQGSQGG
2TOSDQGGDQ VRIVKI
0IRIVKVRIVK2KV DQ
2
SDQTOGGSDQTO
2
GG
V34.6K
IRIVV
DQ
SDQTOGG
Where 2VA152
KPK
Avaustyyppinen
Biasing MOSFET EXAMPLE
Enhancement-mode MOSFET
D
SVGSQ
VGG
IGGRB
IDQ
SR
0IGG
Large signal analysis
©Loberg University of Jyväskylä
32
B21 Rk100RR DD21
1
GG VRRR
1V
k4.189RV
VR B
GG
DD1 k212
RR
RRR
B1
1B2
0RIVV SDQGSQGG V0.6RIVV SDQGGGSQ
Biasing MOSFET EXAMPLE
Enhancement-mode MOSFET
Avaustyyppinen
DISCRETE COMPONENT FET
Large signal analysis
©Loberg University of Jyväskylä
33
Bias point in the Saturation Region DSTOGS VVV
DSTOGSQ VV3.5V7.0V0.6VV
MOSFET stays in the saturation region if VDSQ > 5.3V when IDQ = 420µA
0RIVRIV SDQDSQDDQDD
k15RD
420µA
ID
VDS
5.3V
V0.6VGS
Saturation region
VDD
Load lines
DISCRETE COMPONENT FET
Biasing MOSFET EXAMPLE
Enhancement-mode MOSFET
Avaustyyppinen
Large signal analysis
©Loberg University of Jyväskylä
34
2GS1GS2GS2DS VVVV
21 DSDS II
G1
S
D
S
D
G2
+VDD
R
M2 M1
IDS1
To Load
2DSR II
VGS
MOSFET Sub Circuit Current Mirror
Saturation (Forward active) Region
DSV
V3VGS
V4VGS
V5VGS
V6VGS
1 32 54 6
MOS (M2) resistance characteristic
V1VTO
DI
Identical FETS
Identical MOSFETS Large signal analysis
©Loberg University of Jyväskylä
35
MOSFET Sub Circuit
2GS1GS2GS2DS VVVV
1
2
1DS
2DS
LW
LW
I
I
Different MOSFETs
RK
VVV
RK2
1
RK2
1VV DD2
TO
2
TOTOGS
2TOGS2DS VVKI where
22
2 KP
L
WK
(MOSFET M2)
Assumption : λ = 0
Current Mirror
Different MOSFETS
G1
S
D
S
D
G2
+VDD
R
M2 M1
IDS1
To Load
2DSR II
VGS
12 MM
1
1
2
2
L
W
L
W
Large signal analysis
©Loberg University of Jyväskylä
36
MOSFET Sub Circuit Current Mirror
VDD
IRR
D
S
D
S D
S D
S
IO2
IO3
IO4
M1 M2
M3
M4
VGS
RK
VVV
RK2
1
RK2
1VV DD2
TO
2
TOTOGS
2
KP
L
WK
1
1
2TOGS1DS VVKI
(MOSFET M1)
11
22
1DS
2O
LW
LW
I
I
11
33
1DS
3O
LW
LW
I
I
11
44
1DS
4O
LW
LW
I
I
Different MOSFETS Large signal analysis
©Loberg University of Jyväskylä
37
The End of Part 4
MOSFET Sub Circuit
©Loberg University of Jyväskylä
Top Related