ELEC 256 / Saif Zahir
UBC / 2000
Counters
An (up/down) k-bit counter produces a sequence of k-bit binary numbers in a
response to a COUNT pulse. A k-bit counter can have up to 2k different states
Example: 74163 4-bit synchronous counter
QAQBQCQD
163RCO
PT
ABCD
LOAD
CLR
CLK
01
01
0101
15
3456
14 QA
12 QC11 QD
13 QB
9
1
CLR
107
2
CLK
QD
QC
QB
QA
CLR
CLK
200 400
LogicWorks Timing Simulation
00
00
10
00
01
10
11
11
ELEC 256 / Saif Zahir
UBC / 2000
Design of a 3-Bit Up-Counter
000
001
010
011
100
101
110
111
Present Next FF inputs
C B A C+ B+ A+ TC TB TA
0 0 0 0 0 1 0 0 1 0 0 1 0 1 0 0 1 1 0 1 0 0 1 1 0 0 1 0 1 1 1 0 0 1 1 1 1 0 0 1 0 1 0 0 1 1 0 1 1 1 0 0 1 1 1 1 0 1 1 1 0 0 1 1 1 1 0 0 0 1 1 1
ACB
00 01 11 10
0
1
ACB
00 01 11 10
0
1
ACB
00 01 11 10
0
1
1 1 1 1
1 1 1 1
0 0 0 0
1 1 1 1
0 0 0 0
0 1 1 0
TA=1 TB=A TC=AB
Next-state Logic
ELEC 256 / Saif Zahir
UBC / 2000
Design of a 3-Bit Up-Counter
Flipflop input equations
TA = 1TB = ATC = AB
CLK
C
B
A
200
0
0
0
1
0
0
0
1
0
1
1
0
0
0
1
1
0
1
0
1
1
1
1
1
T QS
R
T QS
R
T QS
R
AB C
\Reset
Count
1
1
ELEC 256 / Saif Zahir
UBC / 2000
Design of a 3-Bit Up-Counter
000
001
010
011
100
101
110
111
Present Next FF inputs
C B A C+ B+ A+ DC DB DA
0 0 0 0 0 1 0 0 1 0 0 1 0 1 0 0 1 0 0 1 0 0 1 1 0 1 1 0 1 1 1 0 0 1 0 0 1 0 0 1 0 1 1 0 1 1 0 1 1 1 0 1 1 0 1 1 0 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0
ACB
00 01 11 10
0
1
ACB
00 01 11 10
0
1
ACB
00 01 11 10
0
1
1 1 1 1
0 0 0 0
0 1 1 0
1 0 0 1
0 0 1 1
0 1 0 1
da = A db = Ab + aB dc = cB+cA+Cba
Use D flipflops
ELEC 256 / Saif Zahir
UBC / 2000
Up-Counter Using D Flipflops
da = A db = Ab + aB dc = cB+cA+Cba
D QS
R
D QS
R
D QS
R
AB C
\Reset
Count
AB
T-FF realization is more efficient - requires less additional combinational logic
ELEC 256 / Saif Zahir
UBC / 2000
Complex-Counter Design Procedure
1. From specification, draw state-transition diagram to show the desired sequence to be realized by counter.2. Choose flipflop type, then use FF excitation-table to derive next-state and FF-input equations.
• Example: Design the following 5-state counter 000
010
011
101
110
C B A C+ B+ A+ TC TB TA
0 0 0 0 1 0 0 1 0 0 0 1 X X X X X X 0 1 0 0 1 1 0 0 1 0 1 1 1 0 1 1 1 0 1 0 0 X X X X X X 1 0 1 1 1 0 0 1 1 1 1 0 0 0 0 1 1 0 1 1 1 X X X X X X
PS NS FF-inputs
Remark: The states that do not appear in the countersquence are treated as don’t care’s!
Using K-maps:
tc = Ac + aCtb = a + B + cta = AbC + Bc
ELEC 256 / Saif Zahir
UBC / 2000
Self-Starting Counters
In previous example, a problem may arise of the counter starts inone of the unused states (001, 100, or 111). Since these states were used as don’t-cares, then depending on how thesedon’t cares were used, counter may exhibit unwanted behavior.
000
010
011
101
110
001
100
111
000
010
011
101
110
111
001
100
Bad DesignCounter may sequence through unwantedstates forever (unless, reset).
Better Design:If starts in an unwanted state, counterwill go (atmost after one clock-cycle)into its normal state sequence.
ELEC 256 / Saif Zahir
UBC / 2000
Self-Starting Counters
C B A C+ B+ A+ TC TB TA
0 0 0 0 1 0 0 1 0 0 0 1 1 1 1 1 1 0 0 1 0 0 1 1 0 0 1 0 1 1 1 0 1 1 1 0 1 0 0 0 1 1 1 1 1 1 0 1 1 1 0 0 1 1 1 1 0 0 0 0 1 1 0 1 1 1 1 0 1 0 1 0
PS NS FF-inputs
000
010
011
101
110
111
001
100
ACB
00 01 11 10
0
1
ACB
00 01 11 10
0
1
ACB
00 01 11 10
0
1
0 0 1 1
1 1 0 0
1 0 1 1
1 1 1 1
0 1 0 1
0 0 0 1
tc = Ac + aC
Next-state Logic
tb = a + B + c ta = AbC + Bc
Another possible state diagramfor a self-starting counter
ELEC 256 / Saif Zahir
UBC / 2000
Counter Design with RS Flipflops
• Example: Design the 5-state self-starting counter using RS flipflops
C B A C+ B+ A+ RC SC RB SB RA SA
0 0 0 0 1 0 X 0 0 1 X 0 0 0 1 X X X X X X X X X 0 1 0 0 1 1 X 0 0 X 0 1 0 1 1 1 0 1 0 1 1 0 0 X 1 0 0 X X X X X X X X X 1 0 1 1 1 0 0 X 0 1 1 0 1 1 0 0 0 0 1 0 1 0 X 0 1 1 1 X X X X X X X X X
PS NS FF-inputs
Q Q+ R S
0 0 X 0 0 1 0 1 1 0 1 0 1 1 0 X
ACB
00 01 11 10
0
1
ACB
00 01 11 10
0
1
ACB
00 01 11 10
0
1
X X 1 X
X 0 X 0
0 0 1 X
X 1 X 0
X 0 X X
X 0 X 1
sc = asb = Bsa = bC
ACB
00 01 11 10
0
1
ACB
00 01 11 10
0
1
ACB
00 01 11 10
0
1
0 0 0 X
X 1 X X
1 X 0 X
X 0 X 1
0 1 0 X
X X X 0
tc = Atb = ab+acta = c
RS-FFexcitation table
ELEC 256 / Saif Zahir
UBC / 2000
Counter Design with JK Flipflops
• Example: Design the 5-state self-starting counter using JK flipflops
C B A C+ B+ A+ JC KC JB KB JA KA
0 0 0 0 1 0 0 X 1 X 0 X 0 0 1 X X X X X X X X X 0 1 0 0 1 1 0 X X 0 1 X 0 1 1 1 0 1 1 X X 1 X 0 1 0 0 X X X X X X X X X 1 0 1 1 1 0 X 0 1 X X 1 1 1 0 0 0 0 X 1 X 1 0 X 1 1 1 X X X X X X X X X
PS NS FF-inputs
Q Q+ J K
0 0 0 X 0 1 1 X 1 0 X 1 1 1 X 0
ACB
00 01 11 10
0
1
ACB
00 01 11 10
0
1
ACB
00 01 11 10
0
1
X X 1 X
X X X 0
X 0 1 X
X 1 X X
X X X X
X 0 X 1
kc = Akb = a + cka = C
jc = ajb = 1ja = bC
JK-FFexcitation table
ACB
00 01 11 10
0
1
ACB
00 01 11 10
0
1
ACB
00 01 11 10
0
1
0 0 X X
X 1 X X
1 X X X
X X X 1
0 1 0 X
X X X X
ELEC 256 / Saif Zahir
UBC / 2000
Counter Design and Timing
A
B
C
RESET
CLK
200 400
JCK
S
R
Q
Q
JCK
S
R
Q
Q
JCK
S
R
Q
Q
01
01
C 1
RESET
B A
CLK
JK-FF Realization
Timing Diagram
ELEC 256 / Saif Zahir
UBC / 2000
Storage Registers
CLK
CLR
D3D2D1D0
Q3
Q2
Q1
Q0
171
D
R
Q
D
R
Q
D
R
Q
D
R
QD3
D2
D1
D0
Q3
Q2
Q1
Q0
CLK
CLR
S=1
S=1
S=1
S=1
K-bit storage register can be realized bythe parallel connection of K D-type flipflops
RS or JK flipflops can be used insteadas long as they implement the D-FF function!
TTL 74171 package:Quadruple D-type Flipflop with Clear
ELEC 256 / Saif Zahir
UBC / 2000
Registers with Input Enable
CLK
CLR
D3D2D1D0
Q3
Q2
Q1
Q0
171CLK
EN
D3D2D1D0
377
Q3Q2Q1Q0
Q7Q6Q5Q4
D7D6D5D4
END0
D7
END0
D7
SystemClock
2:1 0MUX 1
Select
DataBus
74377 74377
In the 74171, register contents maychange with every positive clock edge.
In the 74377, registers contents change (afterthe psoitive edge of CLK) only if EN is asserted (EN=0)
Potential use of 377 packages in a computer system
• Only one of the two 74377 chips can READ from data bus at a time,
ELEC 256 / Saif Zahir
UBC / 2000
Registers with Output Enables
CLK
D3D2D1D0
Q3Q2Q1Q0
Q7Q6Q5Q4
D7D6D5D4
\OE
Tri-StateBuffers
CLK
DCBA
374
QDQCQBQA
QHQGQFQE
HGFE
OE
The 74374 8-bit registerhas tri-stated outputs, whichare enabled by the OE input
OEQA
QH
OEQA
QH
SystemClock
2:1 0MUX 1
Select
DataBus
74374 74374
Input Data Input Data
Potential use of 374 packages in a computer system
• Only one of the two 74374 chips can WRITE to data bus at a time.
ELEC 256 / Saif Zahir
UBC / 2000
Shift Registers
Correct Operation,assuming positiveedge triggered FF
4-Bit Shift-register
FF0 FF1IN
CLK
Q0 Q3D Q D QQ1D Q Q2D Q
FF2 FF3
Serialinput
Serialoutput
IN
Clk
100
Q0
Q1
Q2
Q3
ELEC 256 / Saif Zahir
UBC / 2000
Shift Registers
J
K
QS
R
J
K
QS
R
J
K
QS
R
J
K
QS
R
+\RESET
\RESET+
Q1 Q2 Q3 Q4
Quad right-shift circular shift register using JK flipflops
When RESET=0, Q1 = 1, Q2 = Q3 = Q4 =0
Q1 Q2 Q3 Q4\RESET = 1 1 0 0 0\RESET = 0, Clk 0 1 0 0\RESET = 0, Clk 0 0 1 0\RESET = 0, Clk 0 0 0 1\RESET = 0, Clk 1 0 0 0\RESET = 0, Clk 0 1 0 0. . . . . . . . . . . . . . .
Shift
Also calledRing Counter
ELEC 256 / Saif Zahir
UBC / 2000
Shift-Registers with Parallel Load
0
1 SD Q
0
1 SD Q
0
1 SD Q
0
1 SD Q
IN.0 IN.1 IN.2 IN.3
shift/L
CLK
Q0 Q1 Q2 Q3
2:1 MUX
Operation - following positive edges of CLK:
if shift/L = 1 --> right-shift function is enabled (Q0 <-- SI, Qi <-- Qi-1)
if shift/L = 0 --> parallel-load function is enabled (Qi <-- IN.i )
SI
SI = serial input
ELEC 256 / Saif Zahir
UBC / 2000
Bidirectional Shift-Register
Shift
0
1 SD Q
0
1 SD Q
0
1 SD Q
0
1 SD Q
Q0 Q1 Q2Q4
SLISRI
r/L
SRI: serial right input SLI: serial left input
Operation - following positive edges of CLK:
if r/L = 1 --> right-shift function is enabled (Q0 <-- SRI, Qi <-- Qi-1)
if r/L = 0 --> left-shift function is enabled (Q4 <-- SLI, Qi <-- Qi+1)
ELEC 256 / Saif Zahir
UBC / 2000
Finite State machine (FSM) Design
• FSMs are sequential machines that can have only a fixed number of states.
• Counters are FSMs in which the outputs and the states are identical
• In general the outputs and next states of an FSM are functions of the inputs and present states.
• The specification of output functions leads to two types of FSMs:
– Mealy machines: outputs are functions of inputs and present states
– Moore machines: outputs are functions of present states only
Combinationallogic for outputs
and next-states
R
InputsX
OutputsZ
CLK
CLK
Combinationallogic for
next-statesonly
R
InputsX
OutputsZ
Comb.logic foroutputs
Stateregister
Moore Machine
Mealy Machine
ELEC 256 / Saif Zahir
UBC / 2000
Sequential Parity CheckerCircuit that counts the 1’s in a bit-serial input stream.Odd-parity circuit: asserts its output when input stream contains an odd number of 1’sEven-parity circuit: asserts its output when input stream contains an even number of 1’s
Odd-parity sequential machine
Even[0]
Odd [1]
Reset
11
0
0
D
C
S
R
Q
Q01 Q
Clk
RESET
IN
+
PS input NS Output
0 0 0 00 1 1 01 0 1 11 1 0 1
State-transition table
Realization using a D-FF(a single T-FF can be used instead)
CLK = 1 2 3 4 5 6 7 8 9 10
IN = 0 1 0 1 1 0 0 1 1 0
OUT = 0 0 1 1 0 1 1 1 0 1
Example of input/ouput streams
NS = PS xor INOUT = PS
ELEC 256 / Saif Zahir
UBC / 2000
Finite State machine Design
Design Procedure– Understand problem
» input-output behavior
» define states
– Obtain an abstract representation of the FSM
» state diagrams, state tables
– Perform state minimization
– Perform state assignment:In an FSM with N=2n states, n state variables are needed to encode each state (i.e. each state is encoded by n bits)
– Choose flipflop types to implement the FSM: use flipflop excitation tables to derive the flipflop input equations.
» JK flipflops tend to reduce gate-count
» D flipflops tend to simplify design process
– Implement the FSM: use K-maps or Boolean logic to simplify next-state (or flipflop input) equations; simplify output equations
ELEC 256 / Saif Zahir
UBC / 2000
A Simple Vending Machine
Problem Statement:• Vending machine delivers a package of gum after receiving 15 cents in coins• Machine has a single coin slot and accepts nickels (N) and dimes only (D)• Machine does not give back change; inserting 2 dimes returns one package only
Vending machine controller design
RESET
CLK
N
VendingMachine
FSM
DOPENCoin
Sensor
PackageReleaseMechanism
FSM must remember the total amount that has been received, and releasea gum package when 15 cents (or 20) have been received.The machine sensor will reject any unknown coins
ELEC 256 / Saif Zahir
UBC / 2000
A Simple Vending Machine
Constructing a state-diagramPossible statesS0: initial (0 cents) stateS1: received 5 centsS2: received 10 centsS3: received 15+ cents
S0[0 ¢]
S1[5 ¢]
S2[10¢]
S3[15¢]
N
N
N,D
D
D
Reset
State-Encoding:• The 4 states of the machine must be encoded in binary.• Since we have four states, we need two bits to encode each state (each bit is called a state-variable)
Possible encodings
State Q1 Q0
S0 0 0S1 0 1S2 1 0S3 1 1
State Q1 Q0
S0 0 1S1 1 1S2 1 0S3 0 0
ELEC 256 / Saif Zahir
UBC / 2000
A Simple Vending Machine PS inputs NS outputs
Q1 Q0 D N Q1+ Q0+ OPEN
0 0 0 0 0 0 00 0 0 1 0 1 00 0 1 0 1 0 00 0 1 1 X X X0 1 0 0 0 1 00 1 0 1 1 0 00 1 1 0 1 1 00 1 1 1 X X X1 0 0 0 1 0 01 0 0 1 1 1 01 0 1 0 1 1 01 0 1 1 X X X1 1 0 0 1 1 11 1 0 1 1 1 11 1 1 0 1 1 11 1 1 1 X X X
D-FF implementationD1= Q1+, D0= Q0+
Q1Q0DN
Q1
Q1
D
N
0 0 1 1
0 1 1 1
X X X X
1 1 1 1
Q1Q0DN
Q1
Q1
D
N
0 1 1 0
1 0 1 1
X X X X
0 1 1 1
Q1Q0DN
Q1
Q1
D
N
0 0 1 0
0 0 1 0
X X X X
0 0 1 0
K-Map for D1 K-Map for D0
K-Map for OPEN
d1 = q1 + d + nq0
d0 = nq1 + nQ0 + Nq0 + dq1
open = q1+ q0
ELEC 256 / Saif Zahir
UBC / 2000
Vending Machine FSM Implementation
D Q
D Q
CLK\RESET
OPEN
Q0
Q1
Q1
Q0
\Q0
Q0
Q1
Q1
N
N
N
N
D
D D1
D0
d1 = q1 + d + nq0
d0 = nq1 + nQ0 + Nq0 + dq1
open = q1+ q0
Flipflop (next-state) equationsFSM Implementationwith D flipflops
(Moore machine)
ELEC 256 / Saif Zahir
UBC / 2000
FSM Design for a Vending Machine
JK-FF Implementation
PS inputs NS FF outputs
Q1 Q0 D N Q1+ Q0
+ J1 K1 J0 K0 OPEN
0 0 0 0 0 0 0 X 0 X 00 0 0 1 0 1 0 X 1 X 00 0 1 0 1 0 1 X 0 X 00 0 1 1 X X X X X X X0 1 0 0 0 1 0 X X 0 00 1 0 1 1 0 1 X X 1 00 1 1 0 1 1 1 X X 0 00 1 1 1 X X X X X X X1 0 0 0 1 0 X 0 0 X 01 0 0 1 1 1 X 0 1 X 01 0 1 0 1 1 X 0 1 X 01 0 1 1 X X X X X X X1 1 0 0 1 1 X 0 0 0 11 1 0 1 1 1 X 0 0 0 11 1 1 0 1 1 X 0 0 0 11 1 1 1 X X X X X X X
j1 = d + nq0 k1 = 0
j0 = nQ0 + dq1 k0 = nQ1
open = q1+ q0
ELEC 256 / Saif Zahir
UBC / 2000
Vending Machine FSM Implementation
J Q
Q
CLK\RESET
OPEN
Q0
Q1
D
Q0
\Q0
Q1
N
N
D
K
J
K
\Q1N
0
j1 = d + nq0 k1 = 0
j0 = nQ0 + dq1 k0 = nQ1
open = q1+ q0
FSM implementationwith JK flipflops
(Moore Machine)
ELEC 256 / Saif Zahir
UBC / 2000
Moore and Mealy Machines: State Diagrams
• Complete Moore machine state diagram for vending machine• Outputs are associated with states (graph nodes)
S0 [0]
S1 [0]
S2 [0]
S3 [1]
N
N
N,D
D
D
Reset
Reset
ND/0
ND
ND
Reset
Reset
OPEN
S0
S1
S2
S3
N/0
D/0
D/1
Reset/0
N/0
D/1N/1
Reset/0
ND/0
ND/0
ND/0
Reset/0
Reset/1
OPEN
• Complete Mealy machine state diagram for vending machine• Outputs are associated with inputs along transition arcs
ELEC 256 / Saif Zahir
UBC / 2000
Moore and Mealy Machines: State Tables
PS inputs NS outputs
Q1 Q0 D N Q1+ Q0+ OPEN
0 0 0 0 0 0 00 0 0 1 0 1 00 0 1 0 1 0 00 0 1 1 X X X0 1 0 0 0 1 00 1 0 1 1 0 00 1 1 0 1 1 00 1 1 1 X X X1 0 0 0 1 0 01 0 0 1 1 1 01 0 1 0 1 1 01 0 1 1 X X X1 1 0 0 1 1 11 1 0 1 1 1 11 1 1 0 1 1 11 1 1 1 X X X
PS inputs NS outputs
Q1 Q0 D N Q1+ Q0+ OPEN
0 0 0 0 0 0 00 0 0 1 0 1 00 0 1 0 1 0 00 0 1 1 X X X0 1 0 0 0 1 00 1 0 1 1 0 00 1 1 0 1 1 00 1 1 1 X X X1 0 0 0 1 0 01 0 0 1 1 1 11 0 1 0 1 1 11 0 1 1 X X X1 1 0 0 1 1 11 1 0 1 1 1 11 1 1 0 1 1 11 1 1 1 X X X
Moore machine state table
Outputs are associatedwith states (graph nodes)
S0
S1
S2
S3
S0
S1
S2
S3
Mealy machine state table
Outputs are change with inputs
Vending Machine Example
ELEC 256 / Saif Zahir
UBC / 2000
Binary string Recognizers
Example:Construct an FSM that receives a bit-serial binary input W and asserts its output Z whenever its input string has at least two 1’s in sequence.
Solution:(1,a) - Input-output behavior CLK 1 2 3 4 5 6 7 8 9 A B C D W 0 1 0 1 1 1 0 1 1 1 1 0 0 Z 0 0 0 0 1 1 0 0 1 1 1 0 0
(1.b) - Define states (Moore model) S0: received 0 (most recently) Z=0 S1: received 1 (most recently) Z=0 S2: received two 1’s in sequence Z=1
(2) - State diagram (Moore model)
W=0 1
1 1
0
S0(Z=0)
S1(0)
S2(1)
0
ELEC 256 / Saif Zahir
UBC / 2000
Binary string Recognizers
Example: Binary string recognizer
(3) - State assignment: 3 states means that we need two bits to represent each state
d1 = wq0
d0 = wq0 + wQ1z = q1
State Q1 Q0
S0 0 0S1 0 1S2 1 1
D Q
D Q
CLK
Q0
Q1
W
D1
D0
R
R
Z
CLK
PS IN NS OUT FFQ1 Q0 W Q1+ Q0+ Z D1 D0
0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 10 1 0 0 0 0 0 0 0 1 1 1 1 0 1 1
1 0 0 x x x x x 1 0 1 x x x x x 1 1 0 0 0 1 0 0 1 1 1 1 1 1 1 1
ELEC 256 / Saif Zahir
UBC / 2000
Binary string Recognizers
Example: Binary string recognizer
(1.b) - Define states (Mealy model) S0: received 0 (most recently) S1: received at least one 1 (most recently)
(2) - State diagram (Mealy model)
(3) - State assignment (S0 := 0 , S1 := 1)
W=0/Z=0
1/1
1/0
0/0
S0 S1
PS IN NS OUTQ W Q+ Z D T J K
0 0 0 0 0 0 0 X 0 1 1 0 1 1 1 X 1 0 0 0 0 1 X 1 1 1 1 1 1 0 X 0
Output Z=WQD-FF: D=WT-FF: T=W xor QJK-FF: J=W K=W
D Q
CLK
\RESET
W
Z
ELEC 256 / Saif Zahir
UBC / 2000
Analysis of FSMs
ProblemGiven the hardware schematic of a sequential machine, determine itsstate behavior and output functions.
Example: Analyze the following sequential circuitSolution:1- Find JK input equations
2- Compute next-state equations
J Q
Q
CLK\RESET
Z=B
A
\BX
K
J
K\AX
X
X
a+ = ja A + Ka a = xA + (X+b)a
b+ = jb B + Kb b = xB + (XA+Xa)b
ja = x ka = xB
jb = x kb = x A
z = b
ABX
00 01 11 10
0
1
0 0 1 1
1 1 1 0
K-map for A+
ABX
00 01 11 10
0
1
0 0 1 0
1 1 0 1
K-map for B+
ELEC 256 / Saif Zahir
UBC / 2000
FSM AnalysisAB
X00 01 11 10
0
1
0 0 1 1
1 1 1 0
K-map for A+
ABX
00 01 11 10
0
1
0 0 1 0
1 1 0 1
K-map for B+
A B X A+ B+ Z (=B)
0 0 0 0 0 0 0 0 1 1 1 0 0 1 0 0 0 1 0 1 1 1 1 1 1 0 0 1 0 0 1 0 1 0 1 0 1 1 0 1 1 1 1 1 1 1 0 1
S0
S1
S2
S3
More Machine: output isf function ofpresent state only, Z=B S0
Z=0
S1Z=1
S2Z=0
X=1 S3Z=1
X=0 0
01
1
01
ELEC 256 / Saif Zahir
UBC / 2000
Sequential (Bit-Serial) Adder Design
Sequential adder operation
to add two numbers A=ak ak-1 . . . a1 a0 and B=bk bk-1 . . . b1 b0
- start by adding a0 and a0
- output sum bit s0 and store carry bit c0 so that it is added to bits a1 and b1
in the next clock cycle
- repeat the procedure for
bits ai and bi
(output si and store carry bit ci)
Direct Design
Implement design using
a combinational logic block
that generates next-state and
output functions, and a storage
element (D-FF) to store
present state
D
C
S
R
Q
Q
A
B
Z
1
CLK
\CLR
Clock cycle4 3 2 11 0 0 1
0 1 0 1
1 1 1 0SUM
0 0 0 1
0 0 1 0 C
Presentstate
Nextstate
LSB
Mealy Model
ELEC 256 / Saif Zahir
UBC / 2000
Sequential Adder Design using Formal Methods
Inputs: A, B Output: Z=SUM
States (last carry bit):S0: carry was 0S1: carry was 1
AB=11/Z=0 01/010/011/1
00/001/110/1
00/1
S0 S1
PS IN NS OUT FF
Q A B Q+ Z D J K
0 0 0 0 0 0 0 x 0 0 1 0 1 0 0 x0 1 0 0 1 0 0 x 0 1 1 1 0 0 1 x
1 0 0 0 1 1 x 1 1 0 1 1 0 1 x 0 1 1 0 1 0 1 x 0 1 1 1 1 1 1 x 0
RESET
j = ab k = AB
ABQ
00 01 11 10
0
1
0 0 1 0
X X X X
K-map for J
ABQ
00 01 11 10
0
1
X X X X
1 0 0 0
K-map for K
Z = A xor B xor Q
D= Q
ELEC 256 / Saif Zahir
UBC / 2000
Moore Machine Realization of Sequential Adder
More states are required for Moore Model
S0: C=0 and Z=0 (C=carry, Z:sum) S1: C=0 and Z=1 S2: C=1 and Z=0 S3: C=1 and Z=1
S0Z=0
S2Z=0
RESET
S0Z=0
S2Z=0
00
11
00
11
11
11
00
0110
0110
00
0110
0110
Two flipflops are neededto implement the Moore Modelsequential adder
Ex.:Implement this state diagramusing D, flipflopsand JK flipflops
State Diagram
Top Related