EECS 247 Lecture 12: Data Converter Performance Metrics © 2008 H. K. Page 1
EE247Lecture 12
• Administrative issuesMidterm exam Thurs. Oct. 23rd
o You can only bring one 8x11 paper with your own written notes (please do not photocopy)
o No books, class notes or any other kind of handouts/notes, calculators, computers, PDA, cell phones....
o Midterm includes material covered to end of lecture 14
EECS 247 Lecture 12: Data Converter Performance Metrics © 2008 H. K. Page 2
EE247Lecture 12
• Data converters– Static converter error sources (continued)
• Offset• Full-scale error• Differential non-linearity (DNL)• Integral non-linearity (INL)
– Measuring DNL & INL• Servo-loop• Code density testing (histogram testing)
– Dynamic tests• Spectral testing Reveals ADC errors associated with
dynamic behavior i.e. ADC performance as a function of frequency
EECS 247 Lecture 12: Data Converter Performance Metrics © 2008 H. K. Page 3
0 1 2 3 4 5 6 7 8
0
1
2
3
4
5
6
7
8ADC Transfer CurveReal Ideal
ADC Differential Nonlinearity
DNL = deviation of code width from
Δ (1LSB)
+0.4 LSB DNL error
-0.4 LSB DNL error
1. Endpoints connected
2. Ideal characteristics derived eliminating offset & full-scale error
3. DNL measured code width deviation from 1LSB
0 LSB DNL errorDig
ital O
utpu
t Cod
e
ADC Input Voltage [Δ]
EECS 247 Lecture 12: Data Converter Performance Metrics © 2008 H. K. Page 4
ADC Differential Nonlinearity
• Ideal ADC transitions point equally spaced by 1LSB
• For DNL measurement, offset and full-scale error is eliminated
• DNL [k] (a vector) measures the deviation of each code from its ideal width
• Typically, the vector for the entire code is reported
• If only one DNL # is presented that would be the worst case
EECS 247 Lecture 12: Data Converter Performance Metrics © 2008 H. K. Page 5
ADC DNL
• DNL=-1 implies missing code• For an ADC DNL < -1 not possible undefined• Can show:
• For a DAC DNL < -1 possible
al l iDNL[i] 0=∑
EECS 247 Lecture 12: Data Converter Performance Metrics © 2008 H. K. Page 6
DAC Differential Nonlinearity
EECS 247 Lecture 12: Data Converter Performance Metrics © 2008 H. K. Page 7
DAC Differential Nonlinearity
• To find DNL for DAC– Draw end-point line from 1st point to last– Find ideal LSB size for the end-point corrected
curve– Find segment sizes:
segment [m]=V[m]-V[m-1]
• Unlike ADC DNL, for a DAC DNL can be <-1LSB
segm en t[ m ] V [ LSB ]D NL[ m ]
V [ LSB ]−
=
EECS 247 Lecture 12: Data Converter Performance Metrics © 2008 H. K. Page 8
Impact of DNL on Performance
• Same as a somewhat larger quantization error, consequently degrades SQNR
• How much – later in the course...
• The term "DNL noise", usually means "additional quantization noise due to DNL"
EECS 247 Lecture 12: Data Converter Performance Metrics © 2008 H. K. Page 9
ADC Integral NonlinearityEnd-Point
-1 0 1 2 3 4 5 6 7 8
0
1
6
7
Dig
ital O
utpu
t Cod
e
ADC Input Voltage [Δ]
INL = deviation of codetransition from its ideal location
-1 LSB INL
2
3
4
51. Endpoints connected
2. Ideal characteristics derived eliminating offset & full-scale error (same as for DNL)
3. INL deviation of code transition from ideal is measured
EECS 247 Lecture 12: Data Converter Performance Metrics © 2008 H. K. Page 10
ADC Transfer Function
IdealReal
INL Curve
INLINLMax
INLMax
Input
OutputINL = deviation of code transition from its ideal location
ADC Integral Nonlinearity
INL is also a vector INL[k]If one INL # reported
Worst case INL
Most common End-point:Straight line through the endpoints is usually used as reference,i.e. offset and full scale errors are eliminated in INL calculation
Ideal converter steps found for the endpoint line, then INL is measured Digital
Output
EECS 247 Lecture 12: Data Converter Performance Metrics © 2008 H. K. Page 11
ADC Transfer Function
IdealReal
INL Curve
INL
Input
OutputINL = deviation of code transition from its ideal location
ADC Integral NonlinearityBest-Fit
Best-Fit• A best-fit line (in the least-
mean squared sense) fitted to measured data
• Ideal converter steps found then INL measured
Note: Typically INL #s smaller for best-fit compared to end-point
EECS 247 Lecture 12: Data Converter Performance Metrics © 2008 H. K. Page 12
ADC Integral NonlinearityBest Fit versus End-Point
• Best-Fit
– A best-fit line (in the least-mean squared sense)
– Ideal converter steps is found then INL is measured
-1 0 1 2 3 4 5 6 7 8
0
1
6
7
Dig
ital O
utpu
t Cod
e
ADC Input Voltage [Δ]
-1/2 LSB INL
2
3
4
5
+1/2 LSB INL
Best Fit
End-point INLmax =1LSBBest-fit INLmax =+-1/2LSB
EECS 247 Lecture 12: Data Converter Performance Metrics © 2008 H. K. Page 13
ADC Integral Nonlinearity
m 1
i 1INL[ m] DNL[i]
−
== ∑
Can derive INL by:1-
• Construct uniform staircase between 1st and last transition• INL for each code:
2-• Can show
INL is found by computing the cumulative sum of DNL
T[ m] T[ideal ]INL[m]
W [ideal ]
−=
EECS 247 Lecture 12: Data Converter Performance Metrics © 2008 H. K. Page 14
ADC Differential & Integral NonlinearityExample
m 1
i 1INL[ m] DNL[i]
−
== ∑
Notice:
INL[0] undefined
INL[1]=0
INL[2N-1]=00-7
-0.640.646
-0.37-0.275
0.18-0.554
-0.370.553
0.18-0.552
00.181
--0
INL [LSB]DNL[LSB]
Code #
EECS 247 Lecture 12: Data Converter Performance Metrics © 2008 H. K. Page 15
ADC Differential & Integral NonlinearityExample
--0
0-7
-0.640.646
-0.37-0.275
0.18-0.554
-0.370.553
0.18-0.552
00.181
INL[LSB]
DNL[LSB]
Code #
Code #
DN
L [L
SB
]
0 1 2 3 4 5 6 7
1
0.5
0
-0.5
-1
INL
[LS
B]
0 1 2 3 4 5 6 7
1
0.5
0
-0.5
-1
Max.DNL
Max.INL
EECS 247 Lecture 12: Data Converter Performance Metrics © 2008 H. K. Page 16
DAC Integral Nonlinearity
m 1
i 1INL[ m] DNL[i]
−
== ∑
Can derive INL by:• Connect end points• Find ideal output values• INL for each code:
2-• Can show
INL is found by computing the cumulative sum of DNL
V [ m] V [ideal ]INL[ m]
V [ LSB]
−=
EECS 247 Lecture 12: Data Converter Performance Metrics © 2008 H. K. Page 17
DAC Integral Nonlinearity
EECS 247 Lecture 12: Data Converter Performance Metrics © 2008 H. K. Page 18
DAC DNL and INL
* Ref: “Understanding Data Converters,” Texas Instruments Application Report SLAA013, Mixed-Signal Products, 1995.
EECS 247 Lecture 12: Data Converter Performance Metrics © 2008 H. K. Page 19
Example: INL & DNL
Large INL & Small DNLSmooth variations in transfer curve Small DNL
Large DNL & Small INLAbrupt variations in transfer curve Large DNL
EECS 247 Lecture 12: Data Converter Performance Metrics © 2008 H. K. Page 20
Monotonicity• Monotonicity guaranteed if
| INL | ≤ 0.5 LSBThe best fit straight line is taken as the reference for determining the INL.
• This implies| DNL | ≤1 LSB
EECS 247 Lecture 12: Data Converter Performance Metrics © 2008 H. K. Page 21
Non-Monotonic DAC
000 001 010 011 100 101 110 111
DigitalInput
Analog Output [LSB]
7
6
5
4
3
2
1
0
segment[ m] V [ LSB]DNL[ m]
V [ LSB]
segment[4] V [ LSB]
DNL[4]V [ LSB]
0.5 11.5[ LSB]
12.5 1
DNL[5] 1.5[ LSB]1
−=
−
=
− −= = −
−== =
• DNL< -1LSB for a DACNon-monotonicity
• When can non-monotonicity cause major problems?
-0.52.5
EECS 247 Lecture 12: Data Converter Performance Metrics © 2008 H. K. Page 22
Non-Monotonic ADC
• Code 011 associated with two transition levels !
• For non-monotonic ADC
DNL not defined @ non-monotonic steps
111
110
101
100
011
010
001
000
Digital Output
Analog input
0 Δ 2Δ 3Δ 4Δ 5Δ 6Δ 7Δ
EECS 247 Lecture 12: Data Converter Performance Metrics © 2008 H. K. Page 23
How to measure DNL/INL?
• DAC:– Simply apply digital codes and use a good voltmeter to
measure corresponding analog output
• ADC– Not as simple as DAC need to find "decision levels", i.e.
input voltages at all code boundaries• One way: Adjust voltage source to find exact code trip
points "code boundary servo"• More versatile: Histogram testing
Apply a signal with known amplitude distribution and analyze digital code distribution at ADC output
EECS 247 Lecture 12: Data Converter Performance Metrics © 2008 H. K. Page 24
Code Boundary Servo
C1
ADCInputR2
C2
ADCUnder
Test
VREF
i1
i2
DigitalComp.
A<B
BA≥B
A
InputDigitalCode
ADCOutput
fS
EECS 247 Lecture 12: Data Converter Performance Metrics © 2008 H. K. Page 25
Code Boundary Servo
AD
C D
igita
l Out
put
ADC Analog Input
111
110
101
100
011
010
001
000
Δ 2Δ 3Δ 4Δ 5Δ 6Δ 7Δ
• i1 and i2 are small, and C1 is large, so the ADC analog input moves a small fraction of an LSB each sampling period
• For a code input of 101, the ADC analog input settles to the code boundary shown
EECS 247 Lecture 12: Data Converter Performance Metrics © 2008 H. K. Page 26
Code Boundary ServoGood DVM
C1
R2
C2
ADC
VREF
i1
i2
DigitalComp.
A<B
BA≥B
A
InputDigitalCode
ADCOutput
fS
EECS 247 Lecture 12: Data Converter Performance Metrics © 2008 H. K. Page 27
Code Boundary Servo• A very good digital voltmeter (DVM)
measures the analog input voltage corresponding to the desired code boundary
• DVMs have some interesting properties– They can have very high resolutions (8½ decimal
digit meters are inexpensive)– To achieve stable readings, DVMs average
voltage measurements over multiple 60Hz ac line cycles to filter out pickup in the measurement loop
EECS 247 Lecture 12: Data Converter Performance Metrics © 2008 H. K. Page 28
Code Boundary Servo
• ADCs of all kinds are notorious for kicking back high-frequency, signal-dependent glitches to their analog inputs
• A magnified view of an analog input glitch follows …
Good DVM
R2
C2
ADC
VREF fS
EECS 247 Lecture 12: Data Converter Performance Metrics © 2008 H. K. Page 29
Code Boundary Servo
• Just before the input is sampled and conversion starts, the analog input is pretty quiet
• As the converter begins to quantize the signal, it kicks back charge
time0 1/fS
anal
og in
put
start of conversion
EECS 247 Lecture 12: Data Converter Performance Metrics © 2008 H. K. Page 30
Code Boundary Servo
• The difference between what the ADC measures and what the DVM measures is not ADC INL, it’s error in the INL measurement
• How do we control this error?
time0 1/fS
anal
og in
put
ADC converts this voltage
DVM measures the averageinput including the glitch
EECS 247 Lecture 12: Data Converter Performance Metrics © 2008 H. K. Page 31
Code Boundary Servo
• A large C2 fixes this
• At the expense of longer measurement time
Good DVM
R2
C2
ADC
VREF fS
EECS 247 Lecture 12: Data Converter Performance Metrics © 2008 H. K. Page 32
Histogram Testing
• Code boundary measurements are slow– Long testing time
• Histogram testing– Quantize input with known pdf (e.g. ramp or
sinusoid)– Measure output pdf– Derive INL and DNL from deviation of measured
pdf from expected result
EECS 247 Lecture 12: Data Converter Performance Metrics © 2008 H. K. Page 33
Histogram Test Setup
Ramp
0
VREF
ADC PC
VREF
• Slow (wrt conversion time) linear ramp applied to ADC• DNL derived directly from total number of occurrences of each
code @ the output of the ADC
Time
fS
EECS 247 Lecture 12: Data Converter Performance Metrics © 2008 H. K. Page 34
A/D Histogram Test Using Ramp SignalDigital Output
Analog input
RampTime
n/fs
ADCInput/Output
Example:
ADC sampling rate:fs =100kHz Ts=10μsec
1LSB =10mVFor 0.01LSB measurement resolution:
n =100 samples/code
Ramp duration per code:=100x10μsec=1msec
Ramp slope: 10mV/msec
EECS 247 Lecture 12: Data Converter Performance Metrics © 2008 H. K. Page 35
A/D Histogram Test Using Ramp Signal
Dig
ital O
utpu
t
Analog input
Ramp
Tim
e
n/fs
ADCInput/Output
Example:
Ramp slope: 10mV/msec1LSB =10mVEach ADC code 1msec
fs =100kHz Ts=10μsec
n =100 samples/code#
ofSa
mpl
esPe
r cod
e
DigitalOutput
EECS 247 Lecture 12: Data Converter Performance Metrics © 2008 H. K. Page 36
Ramp HistogramExample: Ideal 3-Bit ADC
0 1 2 3 4 5 6 7 8
0
1
2
3
4
5
6
7ADC characteristicsideal converter
0 1 2 3 4 5 6 70
20
40
60
80
100
120
140
160
180
200
ADC output code
Cod
e C
ount
Dig
ital O
utpu
t Cod
e
ADC Input Voltage [Δ]
EECS 247 Lecture 12: Data Converter Performance Metrics © 2008 H. K. Page 37
Ramp HistogramExample: Real 3-Bit ADC Including Non-Idealities
0 1 2 3 4 5 6 7 8
0
1
2
3
4
5
6
7ADC characteristicsideal converter
+0.4 LSB DNL
-0.4 LSB DNL
+0.4 LSB INL
0 1 2 3 4 5 6 70
20
40
60
80
100
120
140
160
180
200
ADC output codeC
ode
Cou
nt
Dig
ital O
utpu
t Cod
e
ADC Input Voltage [Δ]
EECS 247 Lecture 12: Data Converter Performance Metrics © 2008 H. K. Page 38
Example: 3 Bit ADCDNL Extracted from Histogram
1- Remove “Over-range bins”(0 and full-scale)
2- Compute average count/bin (600/6=100 in this case)
0 1 2 3 4 5 6 70
20
40
60
80
100
120
140
ADC output code
Cod
e C
ount
, End
bin
s re
mov
ed
EECS 247 Lecture 12: Data Converter Performance Metrics © 2008 H. K. Page 39
Example: 3 Bit ADCProcess of Extracting from Histogram
3- Normalize:
- Divide histogram by average count/bin
ideal bins have exactly the average count, which, after normalization, would be 1
Non-ideal bins would have a normalized value greater of smaller than 1 0 1 2 3 4 5 6 70
0.2
0.4
0.6
0.8
1
1.2
1.4
ADC output code
Nor
mal
ized
Cod
e C
ount
EECS 247 Lecture 12: Data Converter Performance Metrics © 2008 H. K. Page 40
Example: 3 Bit ADCDNL Extracted from Histogram
4- Subtract 1 from the normalized code count
5- Result DNL (+-0.4Lsb in this case)
0 1 2 3 4 5 6 7-0.4
-0.3
-0.2
-0.1
0
0.1
0.2
0.3
0.4
ADC output code
DN
L =
Cou
nts
/ Mea
n(C
ount
s) -1
EECS 247 Lecture 12: Data Converter Performance Metrics © 2008 H. K. Page 41
Example: 3-Bit ADCStatic Characteristics Extracted from Histogram
• DNL histogram used to reconstruct the exact converter characteristic (having measured only the histogram)
• Width of all codes derived from measured DNL (Code=DNL + 1LSB)
• INL (deviation from a straight line through the end points)- is found
0 1 2 3 4 5 6 7
0
1
2
3
4
5
6
7
ADC Input VoltageD
igita
l Out
put
Reconstructed ADC Transfer Characteristic
EECS 247 Lecture 12: Data Converter Performance Metrics © 2008 H. K. Page 42
Example: 3 Bit ADCDNL & INL Extracted from Histogram
0 1 2 3 4 5 6 7
0
1
2
3
4
5
6
7
ADC characteristicsIdeal converter
+0.4 LSB DNL
-0.4 LSB DNL
+0.4 LSB INL
1 2 3 4 5 6-1
-0.5
0
0.5
1
DN
L [L
SB]
1 2 3 4 5 6Digital Output Code
INL
[LS
B]
Dig
ital O
utpu
t Cod
e
ADC Input Voltage [Δ]
-1
-0.5
0
0.5
1
EECS 247 Lecture 12: Data Converter Performance Metrics © 2008 H. K. Page 43
Measuring DNL• Ramp speed is adjusted to provide large number of
output/code - e.g. an average of 100 outputs of each ADC code (for 1/100 LSB resolution)
• Ramp test can be quite slow for high resolution ADCs• Example:
16bit ADC & 100conversions/code @100kHz sampling rate
(216or 65,536 codes)(100 conversions/code)
100,000 conversions/sec= 65.6 sec
EECS 247 Lecture 12: Data Converter Performance Metrics © 2008 H. K. Page 44
ADC Histogram Testing Sinusoidal Inputs
• Ramp signal generators linear to only 8 to10bits
Need to find input signal with better purity
• Solution: Use sinusoidal test signal (may need to filter out harmonics)
• Problem: Ideal ADC histogram not flat but has “bath-tub shape”
1000 2000 3000 40000
500
1000
ADC Output- Raw Histogram
ADC output code
Cod
e C
ount
EECS 247 Lecture 12: Data Converter Performance Metrics © 2008 H. K. Page 45
ADC Histogram Test Using Sinusoidal Signals
Sinusoid
At sinusoid midpoint crossings:dv/dt max.
least # of samples
At sinusoid amplitude peaks:dv/dt min.
highest # of samples
ADCInput/Output
Dig
ital O
utpu
t
Analog input
Tim
e
# of
Sam
ples
Per c
ode
DigitalOutput
EECS 247 Lecture 12: Data Converter Performance Metrics © 2008 H. K. Page 46
Histogram TestingCorrection for Sinusoidal PDF
• References:– [1] M. V. Bossche, J. Schoukens, and J. Renneboog,
“Dynamic Testing and Diagnostics of A/D Converters,” IEEE Transactions on Circuits and Systems, vol. CAS-33, no. 8, Aug. 1986.
– [2] IEEE Standard 1057
• Is it necessary to know the exact amplitude and offset of sinusoidal input? No!
EECS 247 Lecture 12: Data Converter Performance Metrics © 2008 H. K. Page 47
DNL/INL Extraction Matlab Program
function [dnl,inl] = dnl_inl_sin(y);
%DNL_INL_SIN
% dnl and inl ADC output
% input y contains the ADC output
% vector obtained from quantizing a
% sinusoid
% Boris Murmann, Aug 2002
% Bernhard Boser, Sept 2002
% histogram boundaries
minbin=min(y);
maxbin=max(y);
% histogram
h = hist(y, minbin:maxbin);
% cumulative histogram
ch = cumsum(h);
% transition levels found by:
T = -cos(pi*ch/sum(h));
% linearized histogram
hlin = T(2:end) - T(1:end-1);
% truncate at least first and last
% bin, more if input did not clip ADC
trunc=2;
hlin_trunc = hlin(1+trunc:end-trunc);
% calculate lsb size and dnl
lsb= sum(hlin_trunc) / (length(hlin_trunc));
dnl= [0 hlin_trunc/lsb-1];
misscodes = length(find(dnl<-0.99));
% calculate inl
inl= cumsum(dnl);
EECS 247 Lecture 12: Data Converter Performance Metrics © 2008 H. K. Page 48
Example: Test Results for DNL & INLUsing Sinusoidal Histogram
0 500 1000 1500 2000 2500 3000 3500 4000-1
0
1
code
DN
L [L
SB]
DNL = +1.3 / -1 LSB, missing code if (DNL<-0.99)
0 500 1000 1500 2000 2500 3000 3500 4000-1
0
1
2
code
INL
[LSB
]
INL = +1.7 / -0.69 LSB
EECS 247 Lecture 12: Data Converter Performance Metrics © 2008 H. K. Page 49
Example: Matlab ADC Model DNL/INL Code Test
% converter model
B = 6; % bits
range = 2^(B-1) - 1;
% thresholds (ideal converter)
th = -range:range; % ideal thresholds
th(20) = th(20)+0.7; % error
fs = 1e6;
fx = 494e3 + pi; % try fs/10!
C = round(100 * 2^B / (fs / fx));
t = 0:1/fs:C/fx;
x = (range+1) * sin(2*pi*fx.*t);
y = adc(x, th) - 2^(B-1);
hist(y, min(y):max(y));
dnl_inl_sin(y);
-30 -20 -10 0 10 20 30-1
-0.5
0
0.5
1
Digital Output
DN
L [L
SB]
DNL = +0.7 / -0.7 LSB
-30 -20 -10 0 10 20 30
0
0.4
0.8
INL
[LSB
]
INL = +0.7 LSB
EECS 247 Lecture 12: Data Converter Performance Metrics © 2008 H. K. Page 50
Histogram Testing Limitations• The histogram (as any ADC test, of course) characterizes one
particular converter. Test many devices to get valid statistics.• Histogram testing assumes monotonicity
E.g. “code flips” will not be detected.• Dynamic sparkle codes produce only minor DNL/INL errors
E.g. 123, 123, …, 123, 0, 124, 124, … look at ADC output to detect
• Noise not detected & averaged outE.g. 9, 9, 9, 10, 9, 9, 9, 10, 9, 10, 10, 10, …
Ref: B. Ginetti and P. Jespers, “Reliability of Code Density Test for High Resolution ADCs,” Electron. Lett., vol. 27, pp. 2231-3, Nov. 1991.
EECS 247 Lecture 12: Data Converter Performance Metrics © 2008 H. K. Page 51
Example: Hiding Problems in the Noise
• INL 5 missing codes
• DNL "smeared out" by noise!
• Always look at both DNL/INL
• INL usually does not lie...
[Source: David Robertson, Analog Devices]
EECS 247 Lecture 12: Data Converter Performance Metrics © 2008 H. K. Page 52
Why Additional Tests/Metrics?
• Static testing does not tell the full story– E.g. no info about "noise“ or high frequency effects
• Frequency dependence (fs and fin) ?– In principle we can vary fs and fin when performing
histogram tests– Result of such sweeps is usually not very useful– Hard to separate error sources, ambiguity– Typically we use fs=fsNOM and fin << fs/2 for
histogram tests• For additional info Spectral testing
EECS 247 Lecture 12: Data Converter Performance Metrics © 2008 H. K. Page 53
DAC Spectural Test or Simulation
• Input sinusoid Need to have significantly better purity compared to DAC linearity
• Spectrum analyzer need to have better linearity than DUT
VoutDAC SpectrumAnalyzer
SinusoidSignal
Generator
ClockGenerator
Device Under Test (DUT)Digital
EECS 247 Lecture 12: Data Converter Performance Metrics © 2008 H. K. Page 54
Direct ADC Spectral Test via DAC
• Need DAC with much better performance compared to ADC under test
• Beware of DAC output sinx/x frequency shaping• Good way to "get started"...
Vin Vout SpectrumAnalyzer
SignalGenerator
ClockGenerator
Device Under Test (DUT)
ADC DAC
EECS 247 Lecture 12: Data Converter Performance Metrics © 2008 H. K. Page 55
Vin PCSignalGenerator
ClockGenerator
Device Under Test (DUT)
DataAcquisition
SystemADC
ADC Spectral Test via Data Acquisition Sytem
EECS 247 Lecture 12: Data Converter Performance Metrics © 2008 H. K. Page 56
Analyzing ADC Outputs via Discrete Fourier Transform (DFT)
• Sinusoidal waveform has all its power at one single frequency
• An ideal, infinite resolution ADC would preserve ideal, single tone spectrum
• DFT used as a vehicle to reveal ADC deviations from ideality
⇒x(t) x(k)
EECS 247 Lecture 12: Data Converter Performance Metrics © 2008 H. K. Page 57
Discrete Fourier TransformThe DFT of a block of N time samples
{x(k)} = {x(0), x(1), x(2),…,x(N-1)}
yields a set of N frequency bins
{Am} = {A0,A1,A2,…,AN-1}
where:
Am = Σn=0
N-1xn WN
mnm = 0,1,2,…,N-1
WN ≡ e-j2π/N
EECS 247 Lecture 12: Data Converter Performance Metrics © 2008 H. K. Page 58
Discrete Fourier Transform (DFT) Properties
• DFT of N samples spaced Ts=1/fs seconds:– N frequency bins from DC to fs– Bin m represents frequencies at m * fs /N [Hz]
• DFT frequency resolution:– Proportional to fs /N in [Hz/bin]
• DFT with N = 2k ( k is an integer) can be found using a computationally more efficient algorithm named:
– FFT Fast Fourier Transform
EECS 247 Lecture 12: Data Converter Performance Metrics © 2008 H. K. Page 59
DFT Magnitude Plots
• Because magnitudes of DFT bins (Am) are symmetric around fS /2, it is redundant to plot ⏐Am⏐’s for m >N/2
• Usually magnitudes are plotted on a log scale normalized so that a full scale sinusoidal waveform with rms value aFS yields a peak bin of 0dBFS:
⏐Am⏐ [dBFS] = 20 log10⏐Am⏐
aFS .N/2
0 fs/2 fs
EECS 247 Lecture 12: Data Converter Performance Metrics © 2008 H. K. Page 60
Matlab ExampleNormalized DFT
fs = 1e6;
fx = 50e3;
Afs = 1;
N = 100;
% time vector
t = linspace(0, (N-1)/fs, N);
% input signal
y = Afs * cos(2*pi*fx*t);
% spectrum
s = 20 * log10(abs(dft(y)/N/Afs*2));
% drop redundant half
s = s(1:N/2);
% frequency vector (normalized to fs)
f = (0:length(s)-1) / N;
0 0.2 0.4 0.6 0.8 1x 10
-4-1
-0.5
0
0.5
1
Time
Ampl
itude
0 0.1 0.2 0.3 0.4 0.5
-300
-200
-100
0
Frequency [ f / fs]
Mag
nitu
de [
dB
FS ]
fx /fs
Top Related