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EECS 247 Lecture 10 Switched-Capacitor Filters © 2007 H. K.

EE247Lecture 10

• Switched-capacitor filters– Switched-capacitor integrators

• LDI integrators• Effect of parasitic capacitance• Bottom-plate integrator topology

– Resonators– Bandpass filters– Lowpass filters

• Termination implementation• Transmission zero implementation

– Switched-capacitor filter design considerations– Effect of non-idealities– Switched-capacitor filters utilizing double sampling technique

EECS 247 Lecture 10 Switched-Capacitor Filters © 2007 H. K. Page 2

Summary of last lecture• Switched-capacitor filters

– Tradeoffs in choosing sampling rate– Effect of sample and hold – Switched-capacitor network electronic noise – Switched-capacitor integrators

• DDI integrators• LDI integrators


LDI Switched-Capacitor Integrator

( )

( )

1/ 2s1I

j T / 2s e s 1j T j T / 2 j T / 2I I

sI

sI

C j TC 1 zin

C CC C1

CC

CC j T

Vo2 z( z ) , z eV

e e e

1j 2 sin T / 2

T / 21sin T / 2

ωω ω ω

ω

ω

ωω ω

−−

−− − +

−

− −

= − × =

= − × = ×

= − ×

= − ×

CI

Ideal Integrator Magnitude Error

No Phase Error! For signals at frequencies << sampling freq.

Magnitude error negligible

-

+

Vin

Vo2

φ1 φ2CI

Cs

φ2

LDI

LDI (Lossless Discrete Integrator) same as DDI but output is sampled ½clock cycle earlier


Switched-Capacitor Filter Built with LDI Integrators( )ωjH

Zeros Preserved

Frequency (Hz) 2fs ffsfs /2


Switched-Capacitor IntegratorParasitic Capacitor Sensitivity

Effect of parasitic capacitors:

1- Cp1 - driven by opamp o.k.

2- Cp2 - at opamp virtual gnd o.k.

3- Cp3 – Charges to Vin & discharges into CI

Problem parasitic capacitor sensitivity

-

+

VinVo

φ1 φ2CI

CsCp3

Cp2

Cp1


Parasitic InsensitiveBottom-Plate Switched-Capacitor Integrator

Sensitive parasitic cap. Cp1 rearrange circuit so that Cp1 does not charge/discharge

φ1=1 Cp1 grounded

φ2=1 Cp1 at virtual ground

Solution: Bottom plate capacitor integrator

Vi+

Cs-

+ Vo

CI

Cp1

Cp2

φ1 φ2

Vi-


Bottom Plate Switched-Capacitor Integrator

12

12

1s s1 1I I

s s1 1I I

C Cz zC C1 z 1 z

C Cz 1C C1 z 1 z

−−

− −

−

− −

− −

− −− −

Note: Different delay from Vi+ &Vi- to either output

Special attention needed for input/output connections to ensure LDI realization

Vi+

Cs-

+ Vo

CIφ1 φ2

Vi-

Vi+on φ1

Vi-on φ2

Vo1on φ1

Vo2on φ2

φ1

φ2

Vo2

Vo1

Output/Inputz-Transform


Bottom Plate Switched-Capacitor Integratorz-Transform Model

12

12

11 1

1 1

z z1 z 1 z

z 11 z 1 z

−−− −

−

− −

− −

−− −

121

z1 z

−

−−

12z−

Input/Output z-transformVi+

Cs-

+ Vo

CIφ1 φ2

Vi-

φ1

φ2

Vo2

Vo1

Vi+

Vi- 12z+ Vo2

Vo1

LDI

s IC C

s IC C−


LDI Switched-Capacitor Ladder Filter

CsCI

12

1z

1 z

−

−−

-+

+ - + -3

1sτ 4

1sτ 5

1sτ

12z

−12z

+

12z

+12z

−

CsCI

−

CsCI

−CsCI

−CsCI

CsCI

Delay around integrator loop is (z-1/2 . z+1/2 =1) LDI function

12

1z

1 z

−

−−

12

1z

1 z

−

−−12z

−

12z

+


Switched-Capacitor LDI Resonator

2s

ω

1s

ω−

C1 1f1 sR C Ceq1 2 2C1 3f2 sR C Ceq3 4 4

ω

ω

= = ×

= = ×

Resonator Signal Flowgraph

φ1 φ2

φ2 φ1


Fully Differential Switched-Capacitor Resonator

φ1 φ2

φ1 φ2

• Note: Two sets of S.C. bottom plate networks for each differential integrator


Switched-Capacitor LDI Bandpass FilterUtilizing Continuous-Time Termination

0s

ω

0s

ω−

C C3 1f0 s sC C4 2C2Q CQ

ω = × = ×

=

Bandpass FilterSignal Flowgraph

CQ

Vi

Vo-1/QVo2Vi

Vo2


s-Plane versus z-PlaneExample: 2nd Order LDI Bandpass Filter

σ

jωs-plane z-plane


Switched-Capacitor LDI Bandpass FilterContinuous-Time Termination

0.1 1 10f0

0

-3dBΔf

Frequency

Mag

nitu

de (d

B)

C1 1f f0 s2 C2f0f Q

C C1 Q1 fs2 C C2 4

π

π

= ×

Δ =

= ×

Both accurately determined by cap ratios & clock frequency


Fifth Order All-Pole LDI Low-Pass Ladder FilterComplex Conjugate Terminations

•Complex conjugate terminations (alternate phase switching)

Termination Resistor

Termination Resistor

Ref: Tat C. Choi, "High-Frequency CMOS Switched-Capacitor Filters," U. C. Berkeley, Department of Electrical Engineering, Ph.D. Thesis, May 1983 (ERL Memorandum No. UCB/ERL M83/31).


Fifth-Order All-Pole Low-Pass Ladder FilterTermination Implementation



Sixth-Order Elliptic LDI Bandpass Filter

TransmissionZero



Use of T-Network

High Q filter large cap. ratio for Q & transmission zero implementationTo reduce large ratios required T-networks utilized


2 1 4

1 2 1 3 4

V C CV C C C C

= − ×+ +

2 1

1 2

V CV C

= −


Sixth Order Elliptic Bandpass FilterUtilizing T-Network

•T-networks utilized for:• Q implemention• Transmission zero implementation

Q implementation

Zero



Effect of Opamp Nonidealities on Switched Capacitor Filter Behaviour

• Opamp finite gain

• Opamp finite bandwidth

• Finite slew rate of the opamp

• Non-linearity associated with opamp output/input characteristics


Effect of Opamp Non-IdealitiesFinite DC Gain


Cs-

+ Vo

CIφ1 φ2

Vi-DC Gain = a

sI s 1

I

1

Cs C C

s C a

o

o a

int g

1H( s ) f

s f

H( s )s

Q a

ωω

≈ −+ ×

−≈

+ ×

⇒ ≈

• Finite DC gain same effect in S.C. filters as for C.T. filters• If DC gain not high enough lowing of overall Q & droop in passband


Effect of Opamp Non-IdealitiesFinite Opamp Bandwidth


Cs-

+ Vo

CIφ1 φ2

Vi-Unity-gain-freq.

= ft

Ref: K.Martin, A. Sedra, “Effect of the Opamp Finite Gain & Bandwidth on the Performance of Switched-Capacitor Filters," IEEE Trans. Circuits Syst., vol. CAS-28, no. 8, pp. 822-829, Aug 1981.

Assumption-Opamp does not slew (will be revisited)Opamp has only one pole only exponential settling

Vo

φ2

T=1/fs

settlingerror

time


Effect of Opamp Non-IdealitiesFinite Opamp Bandwidth

actual idealIk k 1

I s

I t

I s s

t s

C1 e e ZH ( Z ) H ( Z )

C CC f

where kC C f

f Opamp unity gain frequency , f Clock frequency

π

− − −⎡ ⎤− + ×≈ ⎢ ⎥+⎣ ⎦

= × ×+

→ − − →



Cs-

+ Vo

CIφ1 φ2

Vi-Unity-gain-freq.

= ft

Vo

φ2

T=1/fs

settlingerror

time


Effect of Opamp Finite Bandwidth on Filter Magnitude Response

Magnitude deviation due to finite opamp unity-gain-frequency

Example: 2nd

order bandpass with Q=25

fc /ft

|Τ|non-ideal /|Τ|ideal (dB)

fc /fs=1/32fc /fs=1/12

Active RC



Effect of Opamp Finite Bandwidth on Filter Magnitude Response

Example:For 1dB magnitude response deviation:1- fc/fs=1/12

fc/ft~0.04ft>25fc

2- fc/fs=1/32fc/ft~0.022

ft>45fc

3- Cont.-Timefc/ft~1/700

ft >700fc fc /ft

|Τ|non-ideal /|Τ|ideal (dB)

fc /fs=1/32fc /fs=1/12

Active RC



Effect of Opamp Finite Bandwidth Maximum Achievable Q

fc /ft

Max. allowable biquad Q for peak gain change <10%

C.T. filters

Oversampling Ratio



Effect of Opamp Finite Bandwidth Maximum Achievable Q

fc /ft

C.T. filters

Example:For Q of 40 required Max. allowable biquad Q for peak gain change <10%

1- fc/fs=1/32fc/ft~0.02

ft>50fc

2- fc/fs=1/12fc/ft~0.035

ft>28fc

3- fc/fs=1/6fc/ft~0.05

ft >20fcRef: K.Martin, A. Sedra, “Effect of the Opamp Finite Gain & Bandwidth on the Performance of Switched-

Capacitor Filters," IEEE Trans. Circuits Syst., vol. CAS-28, no. 8, pp. 822-829, Aug 1981.


Effect of Opamp Finite Bandwidth on Filter Critical Frequency

Critical frequency deviation due to finite opamp unity-gain-frequency

Example: 2nd

order filterfc /ft

Δωc /ωc

fc /fs=1/32

fc /fs=1/12

Active RC



Effect of Opamp Finite Bandwidth on Filter Critical Frequency

fc /ft

Δωc /ωc

fc /fs=1/32

fc /fs=1/12

Active RC

Example:For maximum critical frequency shift of <1%

1- fc/fs=1/32fc/ft~0.028

ft>36fc

2- fc/fs=1/12fc/ft~0.046

ft>22fc

3- Active RCfc/ft~0.008

ft >125fc

C.T. filters



Opamp Bandwidth Requirements for Switched-Capacitor Filters Compared to Continuous-Time Filters

• Finite opamp bandwidth causes phase lag at the unity-gain frequency of the integrator for both type filters

Results in negative intg. Q & thus increases overall Q and gain @ results in peaking in the passband of interest

• For given filter requirements, opamp bandwidth requirements muchless stringent for S.C. filters compared to cont. time filters

Lower power dissipation for S.C. filters (at low freq.s only due to other effects)

• Finite opamp bandwidth causes down shifting of critical frequencies in both type filters– Since cont. time filters are usually tuned tuning accounts for frequency

deviation– S.C. filters are untuned and thus frequency shift could cause problems

specially for narrow-band filters


Sources of Distortion in Switched-Capacitor Filters

• Distortion induced by finite slew rate of the opamp

• Opamp output/input transfer function non-linearity- similar to cont. time filters

• Distortion incurred by finite setting time of the opamp

• Capacitor non-linearity- similar to cont. time filters

• Distortion due to switch clock feed-through and charge injection


What is Slewing?

oV

Vi+Vi-

φ2

Cs

-

+

Vin

Vo

φ2CI

Cs

CI

CL

Assumption:Integrator opamp is a simple class Atransconductance type differential pairwith fixed tail current, Iss=const.

Iss


oV

Vi+Vi-

φ2

Cs

CI

Iss

What is Slewing?

Io

VinVmax

Imax= -Iss/2

Slope ~ gm

|VCs| > Vmax Output current constant Io=Iss/2 or –Iss/2Constant current charging/discharging CI: Vo ramps down/up Slewing

After VCs is discharged enough to have: |VCs|<Vmax Io=gm VCs Exponential or over-shoot settling

Io

Opamp Io v.s. Vin

Imax= +Iss/2


Distortion Induced by Opamp Finite Slew Rate

Multiple pole settling

One pole settling

Output Voltage

TimeSlewing SettlingSettling (multi-pole)

Vo


Ideal Switched-Capacitor Output Waveform

φ1

φ2

Vin

Vo

Vcs

Clock-

+

Vin

Vo

φ1CI

Cs

-

+

Vin

Vo

φ2CI

Cs

φ2 High Charge transferred from Cs to CI


Slew Limited Switched-Capacitor IntegratorOutput Slewing & Settling

φ1

φ2

Vo-real

Vo-ideal

Clock

Slewing LinearSettling



Distortion Induced by Finite Slew Rate of the Opamp

Ref: K.L. Lee, “Low Distortion Switched-Capacitor Filters," U. C. Berkeley, Department of Electrical Engineering, Ph.D. Thesis, Feb. 1986 (ERL Memorandum No. UCB/ERL M86/12).


Distortion Induced by Opamp Finite Slew Rate

• Error due to exponential settling changes linearly with signal amplitude

• Error due to slew-limited settling changes non-linearly with signal amplitude (doubling signal amplitude X4 error)

For high-linearity need to have either high slew rate or non-slewing opamp

( )( )

( )

o s

o s

2T2ok 2r s

2T 22 oo o3 o s 3

r s r s

8 sinVHD S T k k 4

8 sin fV 8 VHD for f f HDS T 15 15S f

ω

ω

π

ππ

=−

→ = << → ≈



Example: Slew Related Harmonic Distortion

( )o s2T

2o3r s

2oo3

r s

8 sinVHD S T 15

f8 VHD 15S f

ω

π

π

=

≈


Switched-capacitor filter with 4kHz bandwidth, fs=128kHz, Sr=1V/μsec, Vo=3V

12dB


Distortion Induced by Opamp Finite Slew Rate Example

-120

-100

-80

-60

-40

-20

1 10 100 1000

HD

3 [d

B]

(Slew-rate / fs ) [V]

f / fs =1/32

f / fs =1/12

Vo =1V V

o =2V

Vo =1V V

o =2V


Distortion Induced by Finite Slew Rate of the Opamp

• Note that for a high order switched capacitor filter only the last stage slewing will affect the output linearity (as long as the previous stages settle to the required accuracy)

Can reduce slew limited linearity by using an amplifier with a higher slew rate only for the last stageCan reduce slew limited linearity by using class A/B amplifiers

• Even though the output/input characteristics is non-linear as long as the DC open-loop gain is high, the significantly higher slew rate compared to class A amplifiers helps improve slew rate induced distortion

• In cases where the output is sampled by another sampled data circuit (e.g. an ADC or a S/H) no issue with the slewing of the output as long as the output settles to the required accuracy & is sampled at the right time


More Realistic Switched-Capacitor Circuit Slew Scenario

-

+

Vin

Vo

φ2CI

Cs

At the instant Cs connects to input of opamp (t=0+)Opamp not yet active at t=0+ due to finite opamp bandwidth delayFeedforward path from input to output generates a voltage spike at the output with polarity opposite to final Vo step- spike magnitude function of CI, CL , Cs

Spike increases slewing periodEventually, opamp becomes active - starts slewing followed by subsequent settling

CL

Vo

φ2CI

CsCL

t=0+


Switched-Capacitor Circuit Opamp not Active @ t=0+

-

+

Vin

Vo

φ2CI

CsCL

Vo

φ2CI

CsCL

t=0+

( )

( )

0 0

0 0 0

0 0 0 0

0 0 0

t t I Ls Cs Cs s eq eq

I L

t t tI s Iout Cs Cs

I L s eq I L

t t t tL s I eq L s Cs Cs s L Cs Cs

t t ts Iout Cs Cs

s L I L

C CCharg e sharing : C V V C C where CC C

C C CV V VC C C C C C

Assu min g C C C C C C V V C C V V

C CV V VC C C C

Note

− +

+ + −

− + − +

+ − −

= + =+

Δ = = ×+ + +

<< << → ≈ → ≈ + → ≈

→ Δ ≈ × ≈+ +

0 0final t ts sout Cs Cs

I I

C Cthat V V VC C

+ −Δ ≈ − ≈ −


More Realistic Switched-Capacitor Circuit Slew Scenario

-

+

Vin

Vo

φ2CI

CsCL

Vo

φ2CI

CsCL

t=0+

( )0 0

0 0 0

t t I Ls Cs Cs s eq eq

I L

t t ts sCs Cs Cs

I Ls eqs

I L

C CCharg e sharing : C V V C C where CC C

C CV V V C CC C CC C

− +

+ − −

= + =+

= =+ +

+

Notice that if CL is large some of the charge stored on Cs is lost prior to opamp becoming effective operation looses accuracy

Partly responsible for S.C. filters only good for low-frequency applications


More Realistic S.C. Slew Scenario

Vo_realIncluding t=0+spike


Slewing

Spike generated at t=0+

Vo_real

Vo_ideal



Ref: R. Castello, “Low Voltage, Low Power Switched-Capacitor Signal Processing Techniques," U. C. Berkeley, Department of Electrical Engineering, Ph.D. Thesis, Aug. ‘84 (ERL Memorandum No. UCB/ERL M84/67).


Sources of Noise in Switched-Capacitor Filters

• Opamp Noise– Thermal noise– 1/f (flicker) noise

• Thermal noise associated with the switching process (kT/C)– Same as continuous-time filters

• Precaution regarding aliasing of noise required


Extending the Maximum Achievable Critical Frequency

of Switched-Capacitor FiltersConsider a switched-capacitor resonator:

Regular sampling:Each opamp is busy settling only during one of the two clock phases

Idle during the other clock phase

φ1 φ2

φ2 φ1

Note: During φ1 both opamps are idle


Switched-Capacitor Resonator Using Double-Sampling

Double-sampling:

• 2nd set of switches & sampling caps added to all integrators

• While one set of switches/caps sampling the other set transfers charge into the intg. cap

• Opamps busy during both clock phases

• Effective sampling freq. twice THE clock freq. while opamp bandwidth requirement remains the same


Double-Sampling Issues

fclock fs= 2fclock

Issues to be aware of:- Jitter in the clock - Unequal clock phases -Mismatch in sampling caps.

parasitic passbands Ref: Tat C. Choi, "High-Frequency CMOS Switched-Capacitor Filters," U. C. Berkeley, Department of

Electrical Engineering, Ph.D. Thesis, May 1983 (ERL Memorandum No. UCB/ERL M83/31).


Double-Sampled Fully Differential S.C. 6th Order All-Pole Bandpass Filter



Sixth Order Bandpass Filter Signal Flowgraph

γ

1Q

− 0s

ω

inV 1−

0s

ω−

1Q

−0s

ω0s

ω−

0s

ω−0

sω

outV1γ−

γγ−


Double-Sampled Fully Differential 6th Order S.C. All-Pole Bandpass Filter

Ref: B.S. Song, P.R. Gray "Switched-Capacitor High-Q Bandpass Filters for IF Applications," IEEE Journal of Solid State Circuits, Vol. 21, No. 6, pp. 924-933, Dec. 1986.

- Cont. time termination (Q) implementation- Folded-Cascode opamp with fu = 100MHz used- Center freq. 3.1MHz (Measured error >1%), filter Q=55- Clock freq. 12.83MHz effective oversampling ratio 8.27- Measured dynamic range 46dB (IM3=1%)


Switched-Capacitor Filter ApplicationExample: Voice-Band Codec (Coder-Decoder) Chip

Ref: D. Senderowicz et. al, “A Family of Differential NMOS Analog Circuits for PCM Codec Filter Chip,” IEEE Journal of Solid-State Circuits, Vol.-SC-17, No. 6, pp.1014-1023, Dec. 1982.

fs= 1024kHz fs= 128kHz fs= 8kHz fs= 8kHz

fs= 8kHz fs= 128kHz fs= 128kHz

fs= 128kHz


CODEC Transmit Path Lowpass Filter Frequency Response

0 2000 4000 6000 8000-50

-40

-30

-20

-10

0

Frequency (Hz)

Mag

nitu

de (d

B)

Note: fs=128kHz


CODEC Transmit Path Highpass Filter

1000-50

-40

-30

-20

-10

0

Frequency (Hz)

Mag

nitu

de (d

B)

1000010010

Note: fs=8kHz


CODEC Transmit Path Filter Overall Frequency Response

1000-50

-40

-30

-20

-10

0

Frequency (Hz)

Mag

nitu

de (d

B)

1000010010

Low Q bandpass (Q<1) filter shape Implemented with lowpass followed by highpass


CODEC Transmit Path Clocking Scheme

First filter (1st order RC type) performs anti-aliasing for the next S.C. biquad

The first 2 stage filters form 3rd order elliptic with corner frequency @ 32kHz Anti-aliasing for the next lowpass filter

The stages prior to the high-pass perform anti-aliasing for high-pass

Notice gradual lowering of clock frequency Ease of anti-aliasing


SC Filter SummaryPole and zero frequencies proportional to – Sampling frequency fs– Capacitor ratios

High accuracy and stability in responseLong time constants realizable without large R, C

Compatible with transconductance amplifiers– Reduced circuit complexity, power dissipation

Amplifier bandwidth requirements less stringent compared to CT filters (low frequencies only)Issue: Sampled-data filters require anti-aliasing prefiltering


Switched-Capacitor Filters versus Continuous-Time Filter Limitations

Considering overall effects:

• Opamp finite unity-gain-bandwidth

• Opamp settling issues

• Opamp finite slew rate

• Clock feedthru• Switch+ sampling

cap. finite time-constant

Filter bandwidthAssuming constant opamp fu

MagnitudeError

5-10MHz

S.C. Filter

Cont. Time Filter

Limited switched-capacitor filter performance frequency range


SummaryFilter Performance versus Filter Topology

_

1-5%

1-5%

1-5%

1-5%

Freq. Tolerance+ Tuning

<1%40-90dB~ 10MHzSwitched Capacitor

+-40-60%40-70dB~ 100MHzGm-C

+-30-50%50-90dB~ 5MHzOpamp-MOSFET-RC

+-30-50%40-60dB~ 5MHzOpamp-MOSFET-C

+-30-50%60-90dB~10MHzOpamp-RC

Freq. Tolerance

w/o Tuning

SNDRMax. Usable

Bandwidth


Frequency Warping• Frequency response

– Continuous time (s-plane): imaginary axis– Sampled time (z-plane): unit circle

• Continuous to sampled time transformation– Should map imaginary axis onto unit circle– How do S.C. integrators map frequencies?

12s

S.C. 11

1s2

C zH ( z )C zint

C

C j sin f Tint π

−= −−

= −


CT – SC Integrator ComparisonCT Integrator SC Integrator

int

s s

CRCf C

τ = =Identical time constants:

Set: HRC(fRC) = HSC(fSC)

⎟⎟⎠

⎞⎜⎜⎝

⎛=

s

SCsRC f

fff ππ

sin

12s

SC 11

1s2 s

C zH ( z )C zint

C

C j sin f Tint SCπ

−= −−

= −

RC1

12 RC

H ( s )s

jf

τ

π τ

= −

= −


LDI Integration

⎟⎟⎠

⎞⎜⎜⎝

⎛=

s

SCsRC f

fff ππ

sin

• “RC” frequencies up to fs /πmap to physical (real) “SC”frequencies

• Frequencies above fs /π do not map to physical frequencies

• Mapping is symmetric about fs /2 (aliasing)

• “Accurate” only for fRC << fs0 0.1 0.2 0.30

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1

fRC /fs

f SC/f s

1/π

Slope=1

EE247 Lecture 10 - EECS Instructional Support Group …ee247/fa07/files07/lectures/L10_f... ·...

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