Fall 2006
Lillevik 333f06-l25 1University of Portland School of Engineering
EE 333
Computer OrganizationLecture 25
Virtual memoryPage replacement
Translation lookaside buffer (TLB)
Fall 2006
Lillevik 333f06-l25 2University of Portland School of Engineering
EE 333
Memory design goals
• Unlimited memory size– No upper bound on memory addresses– Not practical or possible: cost, implementation
• Infinite memory bandwidth– Zero latency memory accesses– Not practical or possible: cost, laws of physics
• Memory hierarchy can approximate goals
Fall 2006
Lillevik 333f06-l25 3University of Portland School of Engineering
EE 333
Virtual memory
• Programmer sees extremely large memory– Memory divided into pages (1K, 4K, 8K, etc.)– Some pages exist in memory, rest on hard drive
• Pages in use cached in memory– Provides good performance-cost tradeoff– Requires table to map memory pages to disk
(cylinder, head, sector)
– Memory access either hit or miss page
Fall 2006
Lillevik 333f06-l25 4University of Portland School of Engineering
EE 333
Virtual and physical memory
Page table translates
virtual-to-physical
Memory-resident frames
Disk-resident pages
Fall 2006
Lillevik 333f06-l25 5University of Portland School of Engineering
EE 333
OS demand paging
• Bring a page into memory only when it is needed (on first request)– Less I/O needed, less memory needed – Faster response, better performance
• OS (pager) must first check page attributes– Illegal reference error condition– Not-in-memory bring into memory– Memory resident continue
Fall 2006
Lillevik 333f06-l25 6University of Portland School of Engineering
EE 333
Page fault steps• First reference to page: traps/interrupts to OS
page fault (miss)
• OS looks at page table– Invalid reference abort, error condition– Page not in memory
• Get empty frame from free frame list• Copy (write) page into frame• Update page table, set valid bit = 1• Restart instruction
Fall 2006
Lillevik 333f06-l25 7University of Portland School of Engineering
EE 333
Free frames list
Before allocation After allocation
Fall 2006
Lillevik 333f06-l25 8University of Portland School of Engineering
EE 333
What if free frame list is empty?
• Reason– Too many users– Too many programs– Too much data, etc.
• Solution– Find a frame to evict (create space)– May require write-back to disk
Fall 2006
Lillevik 333f06-l25 9University of Portland School of Engineering
EE 333
Page Replacement
1. Find the location of the desired page on disk
2. Find a free frame (algorithm)
- If there is a free frame, use it
- If there is no free frame, use a page replacement algorithm to select a victim frame
- Evict victim frame: write to disk if modified (dirty), write-back
Fall 2006
Lillevik 333f06-l25 10University of Portland School of Engineering
EE 333
Page Replacement, continued.
3. Read the desired page into the (newly) free frame
- Update page table
- Update frame table
4. Restart the process (instruction)
Fall 2006
Lillevik 333f06-l25 11University of Portland School of Engineering
EE 333
Page replacement stepsDMA write
DMA read
Fall 2006
Lillevik 333f06-l25 12University of Portland School of Engineering
EE 333
Page replacement algorithm? (Which page to evict)
Fall 2006
Lillevik 333f06-l25 13University of Portland School of Engineering
EE 333
Paging memory performance
• Similar to cache performance– Hit: memory page is resident– Miss: memory page on disk only
• Access time
diskmemave
ThThT 1
Fall 2006
Lillevik 333f06-l25 14University of Portland School of Engineering
EE 333
Find the access time?Find an expression for the average access time Tave of a memory-hard disk hierarchy? Assume the page rate (hit) is p, memory access time is m, the I/O bus bandwidth is b, the size of a page is s bytes, a page is found dirty (modified) with probability d, and the free page list is always empty (memory full).
diskmemave
TpTpT 1
mTmem
modifiednot modified diskT
read read andback write
Fall 2006
Lillevik 333f06-l25 15University of Portland School of Engineering
EE 333
Find the access time? Continued.
busbusdisk
TdTdT 12
b
sd
b
sd 12
b
sd
b
sdpmp 121
diskave TpmpT 1
Fall 2006
Lillevik 333f06-l25 16University of Portland School of Engineering
EE 333
Problems with paging
• Page table can become enormous– Several OS solutions– Hashing function, inverted page table
• Each memory access requires page table access (another memory access)– Cache the page table– Translation lookaside buffer (TLB)
Fall 2006
Lillevik 333f06-l25 17University of Portland School of Engineering
EE 333
TLB
• Purpose: hardware speed up for page table access
• What it is: small, fast cache of recently used page table entries
• Accesses– Hit: page table value is cached (fast)– Miss: page table value not cached, must read it
from memory
Fall 2006
Lillevik 333f06-l25 18University of Portland School of Engineering
EE 333
Pentium 4 execution engine
Fall 2006
Lillevik 333f06-l25 19University of Portland School of Engineering
EE 333
Find the effective memory access?TLB = 20 ns, mem = 100 ns, hit = 0.8
Fall 2006
Lillevik 333f06-l25 21University of Portland School of Engineering
EE 333
Page replacement algorithm?
• Least recently used (LRU)
• First in, first out (FIFO)• Optimal: lowest page fault rate
• Random
(Which page to evict)
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