ECE 5745 Complex Digital ASIC DesignTopic 3: CMOS Circuits
Christopher Batten
School of Electrical and Computer EngineeringCornell University
http://www.csl.cornell.edu/courses/ece5745
Combinational Logic Sequential State
Part 1: ASIC Design Overview
P P
MM
Topic 1Hardware
DescriptionLanguages
Topic 2CMOS Devices
Topic 3CMOS Circuits
Topic 4Full-Custom
DesignMethodology
Topic 5Automated
DesignMethodologies
Topic 7Clocking, Power Distribution,
Packaging, and I/O
Topic 8Testing and Verification
Topic 6Closing
theGap
Topic 3CMOS Circuits
ECE 5745 T03: CMOS Circuits 2 / 28
Combinational Logic Sequential State
CMOS Logic, State, Interconnect
Combinational
Logic
Sequential
State
Interconnect
ECE 5745 T03: CMOS Circuits 3 / 28
• Combinational Logic • Sequential State
CMOS Logic, State, Interconnect
Combinational
Logic
Sequential
State
Interconnect
Combinational
Logic
ECE 5745 T03: CMOS Circuits 4 / 28
• Combinational Logic • Sequential State
CMOS Inverter Simple RC Model
Vdd
Vin Vout
Close switch when Vin = 0
Close switch when Vin = Vdd
ECE 5745 T03: CMOS Circuits 5 / 28
• Combinational Logic • Sequential State
CMOS Inverter Simple RC Model
6.375 Spring 2006 • L04 CMOS Transistors, Gates, and Wires • 11
A simple RC model for the inverter can provide significant insight
Reff = Reff,N = Reff,PCg = Cg,N + Cg,PCd = Cd,N + Cd,P
Vin Vout Vin
Cg CdReff
Reff
Vout
ECE 5745 T03: CMOS Circuits 6 / 28
• Combinational Logic • Sequential State
CMOS Inverter Layout
6.375 Spring 2006 • L04 CMOS Transistors, Gates, and Wires • 10
The most basic CMOS gate is an inverter
Vin Vout
WN/LN
WP/LP
A Y
VDD
GND
PMOS
NMOS
ECE 5745 T03: CMOS Circuits 7 / 28
• Combinational Logic • Sequential State
CMOS Inverter
6.375 Spring 2006 • L04 CMOS Transistors, Gates, and Wires • 9
The most basic CMOS gate is an inverter
Vin Vout
WN/LN
WP/LP
Let’s make the following assumptions1. All transistors are minimum length2. All gates should have equal rise/fall
times. Since PMOS are twice as slow as NMOS they must be twice as wide to have the same effective resistance
3. Normalize all transistor widths to minimum width NMOS
2Į
1Į
ECE 5745 T03: CMOS Circuits 8 / 28
• Combinational Logic • Sequential State
Series Transistors
Adapted from [Weste’11]
ECE 5745 T03: CMOS Circuits 9 / 28
• Combinational Logic • Sequential State
Parallel Transistors
Adapted from [Weste’11]
ECE 5745 T03: CMOS Circuits 10 / 28
• Combinational Logic • Sequential State
Series/Parallel Transistor Networks are Natural Duals
6.375 Spring 2006 • L04 CMOS Transistors, Gates, and Wires • 20
Series and parallel MOSFET networks provide natural duals of each other
A BAA
B
AA
BA B
Conducts if A=1 OR B=1Conducts if A=1 AND B=1Conducts if A=1
Conducts if A=0 AND B=0Conducts if A=0 OR B=0Conducts if A=0
ECE 5745 T03: CMOS Circuits 11 / 28
• Combinational Logic • Sequential State
CMOS Static Logic Style
6.375 Spring 2006 • L04 CMOS Transistors, Gates, and Wires • 19
More complicated gates use more transistors in pullup/pulldown networks
For every set of input logic values, either pullup or pulldown
network makes connection to VDD or GND
– If both connected, power rails would be shorted together
– If neither connected, output would float (tristate logic)
VDD
VOUT
Pullup network, connects output to VDD, contains only PMOS
Pulldown network, connects output to GND, contains only NMOS
Input NInput 1
Input 0
ECE 5745 T03: CMOS Circuits 12 / 28
• Combinational Logic • Sequential State
NAND/NOR Static CMOS Logic Gates
6.375 Spring 2006 • L04 CMOS Transistors, Gates, and Wires • 21
NAND and NOR gates illustrate the dual nature of the pullup/pulldown networks
A
B(A.B)
BA
(A.B)
A
B(A+B)
AB (A+B)
NAND Gate NOR Gate
ECE 5745 T03: CMOS Circuits 13 / 28
• Combinational Logic • Sequential State
Approach for Designing More Complex Gates
I Goal is to create a logic function f (x1, x2, ...)
. We can only implement inverting logic with one CMOS stage
I Implement pulldown network. Write PD = f (x1, x2, ...)
. Use parallel NMOS for OR of inputs
. Use series NMOS for AND of inputs
I Implement pullup network. Write PU = f (x1, x2, ...) = g(x1, x2, ...)
. Use parallel PMOS for OR of inverted inputs
. Use series PMOS for AND of inverted inputs
ECE 5745 T03: CMOS Circuits 14 / 28
• Combinational Logic • Sequential State
Complex Logic Gate Example
6.375 Spring 2006 • L04 CMOS Transistors, Gates, and Wires • 23
Designers can use a methodical approach to build more complex gates
A
B
C(A+B).C
C)BA(f ��
C)BA(PD ��
C)BA(
C)BA(
C)BA(PU
��
��
��
ECE 5745 T03: CMOS Circuits 15 / 28
• Combinational Logic • Sequential State
Single- vs. Multi-Stage Static CMOS Logic
Adapted from [Weste’11]
ECE 5745 T03: CMOS Circuits 16 / 28
• Combinational Logic • Sequential State
Multiple Stages of Static CMOS Logic
Each design has different delay,area, and energy trade-offs
Adapted from [Weste’11]
ECE 5745 T03: CMOS Circuits 17 / 28
• Combinational Logic • Sequential State
CMOS Pass-Transistor Logic Style
Adapted from [Weste’11]
ECE 5745 T03: CMOS Circuits 18 / 28
• Combinational Logic • Sequential State
CMOS Transmission Gate Multiplexer
Adapted from [Weste’11]
ECE 5745 T03: CMOS Circuits 19 / 28
• Combinational Logic • Sequential State
CMOS Tri-State Buffers
Vdd
A Y
En
EnGnd
Adapted from [Weste’11]
ECE 5745 T03: CMOS Circuits 20 / 28
• Combinational Logic • Sequential State
Various Multiplexer Implementations
Each design has different delay,area, and energy trade-offs
Simple first-order analysis can helpsuggest some of these trade-offs
Adapted from [Weste’11]
ECE 5745 T03: CMOS Circuits 21 / 28
• Combinational Logic • Sequential State
Larger Tri-State Multiplexers
Adapted from [Weste’11]
ECE 5745 T03: CMOS Circuits 22 / 28
Combinational Logic • Sequential State •
CMOS Logic, State, Interconnect
Combinational
Logic
Sequential
State
Interconnect
Sequential
State
ECE 5745 T03: CMOS Circuits 23 / 28
Combinational Logic • Sequential State •
Level-High Latch
Adapted from [Weste’11]
ECE 5745 T03: CMOS Circuits 24 / 28
Combinational Logic • Sequential State •
Positive-Edge Triggered Flip-Flop
Adapted from [Weste’11]
ECE 5745 T03: CMOS Circuits 25 / 28
Combinational Logic • Sequential State •
Positive-Edge Triggered Flip-Flop
Adapted from [Weste’11]
ECE 5745 T03: CMOS Circuits 26 / 28
Combinational Logic Sequential State
Take-Away Points
I We have reviewed basic CMOS circuit implementations. Combinational Logic: static CMOS, pass-transistor, tri-state buffers. Sequential State: latches, flip-flops
I In the next two sections, we will explore various methodologies whichenable mapping designs written in a hardware-description languagedown into these circuits
I In the next part of the course, we will explore the details of how toquantitatively evaluate the cycle time, area, and energy of thesecircuits
ECE 5745 T03: CMOS Circuits 27 / 28
Combinational Logic Sequential State
Acknowledgments
I [Weste’11] N. Weste and D. Harris, “CMOS VLSI Design: A Circuitsand Systems Perspective,” 4th ed, Addison Wesley, 2011.
ECE 5745 T03: CMOS Circuits 28 / 28
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