ATLAS hardware-based Endcap Muon Trigger for future upgrades22nd IEEE Real Time Conference
October 12-23, 2020
Yuya Mino (Kyoto University) on behalf of the ATLAS Collaboration
22nd IEEE Real Time Conference Yuya Mino
IntroductionFuture upgrades are planned for new physics searches and standard model precision studies with higher energy and luminosity. Run 3 : Increase center-of-mass energy to 14 TeV with an instantaneous
luminosity to 2 × 1034 cm-2s-1 (Higher energy) HL-LHC : Planned to start the operation in 2027 with an instantaneous
luminosity of 5.0 - 7.5 × 1034 cm-2s-1 (Higher luminosity)
2
Run 2 Long shutdown 2 Run 3 Long shutdown 3 Run4 - 5...… 2018 2019 2020 2021 2022 2023 2024 2025 2026 2027 …
* First trigger level is renamed Level-1→ Level-0 after Run3
LHC HL-LHC
Continuous upgrades of the hardware-based (Level-1/0*) endcap muon trigger is required to cope with the high event rate.
PhaseⅠ upgrade
PhaseⅡ upgrade
13 TeV13 - 14 TeV 14 TeV Energy
2 × nominal Lumi 5 - 7.5 × nominal Lumi2 × nominal Lumi
InstantaneousLuminosity
190 fb-1 350 fb-1 3000 - 4000 fb-1
22nd IEEE Real Time Conference Yuya Mino
Muon system in Run 2Muon detector system consists of 4 types of detectors for triggering and precision tracking.
3
2008 JINST 3 S08003
Figure 1.4: Cut-away view of the ATLAS muon system.
1.4 Muon system
The conceptual layout of the muon spectrometer is shown in figure 1.4 and the main parametersof the muon chambers are listed in table 1.4 (see also chapter 6). It is based on the magneticdeflection of muon tracks in the large superconducting air-core toroid magnets, instrumented withseparate trigger and high-precision tracking chambers. Over the range |h | < 1.4, magnetic bendingis provided by the large barrel toroid. For 1.6 < |h | < 2.7, muon tracks are bent by two smallerend-cap magnets inserted into both ends of the barrel toroid. Over 1.4 < |h | < 1.6, usually referredto as the transition region, magnetic deflection is provided by a combination of barrel and end-capfields. This magnet configuration provides a field which is mostly orthogonal to the muon trajec-tories, while minimising the degradation of resolution due to multiple scattering. The anticipatedhigh level of particle flux has had a major impact on the choice and design of the spectrome-ter instrumentation, affecting performance parameters such as rate capability, granularity, ageingproperties, and radiation hardness.
In the barrel region, tracks are measured in chambers arranged in three cylindrical layersaround the beam axis; in the transition and end-cap regions, the chambers are installed in planesperpendicular to the beam, also in three layers.
– 11 –
Thin Gap Chamber (TGC) Multi-wire proportional chamber Covers the endcap region (1.05 < |η| < 2.7)
Resistive Plate Chamber (RPC) Covers the barrel region (|η| < 1.05)
Monitored Drift Tube (MDT) Placed inside (|η| < 2.0) and outside (|η| < 2.7) the magnetic field
Cathode Strip Chamber (CSC) Placed only inside the magnetic field (2.0 < |η| < 2.7) Used to cope with high event rate
22nd IEEE Real Time Conference Yuya Mino
Level-1 muon trigger in Run 2pT threshold is set for Level-1 muon trigger to select events with high-pT muons from interesting physics processes.
Level-1 muon trigger rate in Run 2 is dominated by ① Triggers by low pT muons below the pT threshold. ② Triggers by charged particles emerging from the endcap toroid magnets. (Fake muons) ➡ New coincidence logic developed in Run 3 and HL-LHC to reduce ① & ②.
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1.2 ATLAS muon spectrometer
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TGCs
Figure 1.1: Two R-Z views of of the present (Run 1/2) ATLAS muon spectrometer layout. The green(blue) chambers labelled BIS/BIL, BMS/BML, BOS/BOL, BEE (EIS/EIL, EES/EEL, EMS/EML,EOS/EOL) are MDT chambers in the barrel (endcap) regions of the spectrometer. The TGCs, RPCs,and CSCs are shown in red, white, and yellow, respectively. Top: One of the azimuthal sectors thatcontain the barrel toroid coils (small sector). Bottom: One of the sectors in-between the barrel toroidcoils (large sector).
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muon
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ATLAS L1Muon Trigger Public Results
22nd IEEE Real Time Conference Yuya Mino
Hardware-based online triggeringBasic concept of endcap muon hardware trigger : Position difference (dR, dφ) in the TGC BW calculated on the front-end boards. dR, dφ information is handed over to a Look-Up-Table (LUT) implemented on trigger processor board to calculate pT of the muon candidates. (TGC BW coincidence) Require hits in the inner muon detector to reduce fake muons. (Inner coincidence)
5
第 2章 ATLAS エンドキャップミューオントリガー 32
出力する。1つのチップで 1トリガーセクターを担当するので、1つの FPGA が持つ LUT の数は 1トリガーセクターにおける RoIの数と一致し、Endcap 領域では 148個、Forward 領域では 64個である。
Fig. 3.17: TGC トリガーの判定方法。low-pT 及び high-pT でのコインシデンス処理を表している [17]。
3.2.5 Coincidence Window(CW)
レベル 1 ミューオントリガーでは閾値を複数設定してミューオンの pT を pt1 ~ pt6 の 6
段階に分ける。Coincidence Window (CW) とは SL に届いた (∆R, ∆φ) の組に対してそれが 6 段階のどの pt に相当するかをマップしたものである。CW は SL に Look Up Table
として実装されており、SL は ∆R, ∆φ 情報をアドレスに変換して対応する pT の値を読み出す。Fig. 3.18 は CW の一例であり、(∆R, ∆φ) と pT との対応を図示したものである。
Fig. 3.18: High-pT CW の一例。pt2(水色) は pT > 6 GeV、pt4(緑) は pT > 11 GeV、pt5(オレンジ) は pT > 15 GeV、pt6(赤) は pT > 20 GeV を意味する。(pt3 (pT > 10
GeV) は使用していない)
32
図 2.14 ある RoI における ∆R ×∆φ の Coincidence Window [6]。∆R、∆φにより出力結果を色分けして示しており、∆Rおよび∆φの小さい部分で高い pTであると判定していることがわかる。pT 計算の結果は 3-bit にエンコードされて出力される。
SL上でのトリガーロジックの実装方法を詳しく説明する。図 2.15 に 1トリガーセクター分の実装方法の概念図を示した。6本のG-Link 信号で受信した信号はDecoder部分でトラックの位置の情報 (HIT ID、POS)と方向の情報(∆R、∆φ 、Sign およびH/L 情報)とに分けられる。位置の情報を用いてどの RoI においてヒットがあったのかを判定し、それらの方向情報 11-bit 分を対応する LUT に配分する。LUTでは H/L 、∆R、∆φおよびそれらの符合の情報を用いて、pT と電荷情報の計算を行い、その結果を 4-bit で出力する。その後、EI/FI および Tile Calorimeter の情報を合わせてヒット位置のコインシデンス、Inner Coincidence を取り、最後に 1トリガーセクターに 2イベントまでトラック候補を絞り、後段のMuCTPi に送信する。ここで、Inner Coincidence について説明しておく。これまでに説明したコインシデンスロジックは全て磁場の外側の TGC Big Wheelによるものである。Run-1 では実際に TGC Big Wheel 単体でトリガーを発行していたが、図 2.16 のように、特に |η| の大きい領域においてオフラインでミューオンが再構成されないにも関わらずトリガー判定してしまっている場合が多いことが判明した。この原因は、図 2.17で「フェイク」で示されているようなバックグラウンド事象に対し、トリガー判定をしてしまうことであった。このようなフェイク事象を排除するために、Run-2 では図 2.17に示されるように磁場の内側のいくつかの検出器とのコインシデンスを取っている。1.0 < |η| < 1.3 では EI および Tile Calorimeter と、1.3 < η < 1.9 では FI とコインシデンスを取ることで、フェイクトリガーを大きく削減することができる [7] [8]。現在、EI および FI コインシデンスは実際に ATLAS データ取得に用いられており、Tile Calorimeter コインシ
LUT for Run 2
Low pT
High pT
Low pT
第 3章 ATLAS Level-1 エンドキャップミューオントリガー 31
衝突点
ビーム軸
dRdΦ
Φ
R
dΦ
dR
拡大図
トロイド磁場領域
無限運動量
実際の軌跡
M1M2
M3
z = 13
z = 14z = 14.5
図 3.5 エンドキャップミューオントリガーの概要 [13]。M1、M2、M3で得られたミューオンの飛跡情報を用いる。磁場中での曲がり具合から横運動量を見積もり、設定された閾値に対してトリガー判定を行う。図中の飛跡は µ−のもの。
3.1.3 Level-1 ミューオンエンドキャップトリガー判定の概要
Run-2でのエンドキャップミューオントリガーの概要を図 3.5に示す。衝突で生成されたミューオンは磁場の内側に設置された検出器に信号を残しながら、トロイド磁場に入射する。ミューオンの飛跡は磁場中で η方向に曲げられる。磁場領域を通過したミューオンは TGC BWを通過し、信号を残す。Level-1 エンドキャップミューオントリガーでは pTを計算し、決められた閾値に対してトリガー判定を行う。pTを計算するために 3層のTGC BWで得られた飛跡情報とM3と衝突点を結んだ直線を用いて磁場中での飛跡の曲がり具合を見積もる。この飛跡の曲がり具合は R方向と φ方向で別々に計算され、dRと dφとして表される。この飛跡の曲がり具合が小さいミューオンほど高い pTを持っていることを表しており、飛跡の曲がり具合の情報 (dR, dφ)を pTに変換してトリガー判定を行っている。
3.1.4 エレクトロニクス
TGCで用いられるエレクトロニクスはトリガー判定と検出器のヒット情報の読み出しの 2つの役割を担っている。図 3.6にトリガー信号と読み出しデータの流れの全体図を示す。以下では各エレクトロニクスについて説明する。
Interaction Point
muon track
pT = ∞
beam axistoroidal magnet field
Inner muon detector
Run 3
22nd IEEE Real Time Conference Yuya Mino
Level-1 endcap muon trigger in Run 3New detectors will be installed to measure muons with higher resolution and reduce fake muons. ① New Small Wheel (NSW) - Consists of 8 layers each of small-strip TGC and Micromegas. (Total 16 layers)
② Resistive Plate Chamber BIS78 (RPC BIS78) - Consist of 3 layers of RPC Finer position and angle information combined with TGC BW position to reduce fake muons and re-calculate pT. (①, ②) Coverage of the inner muon detector extended from |η| = 1.9 to 2.4 . (①)
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Inner detector coverage extended
η=1.3TGC EI - Position
Tile Calorimeter - Position
22nd IEEE Real Time Conference Yuya Mino
Coincidence logic with new inner muon detectors in Run 3
Position and angle matching between TGC BW and new inner muon detectors are implemented to measure pT with higher precision.
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22nd IEEE Real Time Conference Yuya Mino
Coincidence logic with new inner muon detectors in Run 3
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Position and angle matching between TGC BW and new inner muon detectors are implemented to measure pT with higher precision.
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22nd IEEE Real Time Conference Yuya Mino
Hardware design of Sector Logic in Run 3Endcap trigger processor board (Sector Logic) is required to have ① Enough I/O ports to handle data from various detectors. ② Large amount of resources to implement new coincidence logic. New Sector Logic (SL) board has been developed.
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NewSL board① Optical interfaces are placed to use GTX*/G-Link connection
② 795 × 36 Kb Block RAM × 20 times the resource compared to the FPGA used in Run 2
GTX For TGC EI, NSW ,BIS78 8 lanes × 6.4 Gbps = 51.2 Gbps
G-Link For TGC BW, Tile 13 lanes × 0.8 Gbps = 10.4 Gbps
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DRAFT
Preliminary Design for Endcap Sector Logic July 10, 2020 - Version 1.0
3 Hardware270
3.1 Overview271
The Endcap SL will be introduced in L0Muon as a part of the ATLAS upgrade for HL-LHC. It receives hits from272
the TGC PS boards, track segments from NSWTP, coincidence outputs of BIS78 RPC from Barrel SL, and273
energy flag for Tile coincidence, indicating whether or not the signal pulse is greater than the threshold [2,274
4]. The Endcap SL sends TCs with pT
thresholds satisfied and NSW track segments to the MDTTP. The275
Endcap SL receives the TCs from the MDTTP, where pT
evaluated with the MDT hits is included if the276
evaluation is possible. The Endcap SL sends mTCs to MUCTPI. In addition, the Endcap SL is responsible277
for the transmission of the TGC hits and the trigger information, including NSW, BIS78 RPC, and Tile data,278
downstream to FELIX for readout. The Endcap SL receives the TTC signals from FELIX. The Endcap SL is279
responsible also for the transmission of the configuration signals to the TGC PS boards.280
The Endcap SL system consists of 48 ATCA blades. An ATCA blade shall process the data for one 24th281
of the coverage in � for one of the positive and the negative sides of ⌘.282
Figure 3.1 shows a simplified block diagram of Endcap SL. Figure 3.2 shows also a block diagram but the283
elements are shown one by one. CERN-developed IPMC shall be used for basic blade control and configura-284
tion at power up through the ATCA shelf manager. The Endcap SL interfaces with the TDAQ servers [6] and285
DCS [8] via MPSoC mezzanine for control and monitoring.286
TGC6FireFlyforreceivers4FireFlyfortransmitters
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Figure 3.1: A simplified block diagram of the Endcap SL.
3.2 FPGA287
The FPGA selected in the preliminary design is Xilinx Virtex UltraScale+ FPGA (XCVU9P-1FLGA2577E).288
This type of FPGA has the following features.289
• System logic cells: 2,586k290
• DSP slices: 6840291
• Memory (Block RAM): 75.9 Mb292
3. Hardware Page 9 of ??
* GTX: multi-gigabit transceivers for Xilinx Kintex-7 FPGAs
Installation is completed and the commissioning is ongoing.
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DRAFT
Preliminary Design for Endcap Sector Logic July 10, 2020 - Version 1.0
3 Hardware270
3.1 Overview271
The Endcap SL will be introduced in L0Muon as a part of the ATLAS upgrade for HL-LHC. It receives hits from272
the TGC PS boards, track segments from NSWTP, coincidence outputs of BIS78 RPC from Barrel SL, and273
energy flag for Tile coincidence, indicating whether or not the signal pulse is greater than the threshold [2,274
4]. The Endcap SL sends TCs with pT
thresholds satisfied and NSW track segments to the MDTTP. The275
Endcap SL receives the TCs from the MDTTP, where pT
evaluated with the MDT hits is included if the276
evaluation is possible. The Endcap SL sends mTCs to MUCTPI. In addition, the Endcap SL is responsible277
for the transmission of the TGC hits and the trigger information, including NSW, BIS78 RPC, and Tile data,278
downstream to FELIX for readout. The Endcap SL receives the TTC signals from FELIX. The Endcap SL is279
responsible also for the transmission of the configuration signals to the TGC PS boards.280
The Endcap SL system consists of 48 ATCA blades. An ATCA blade shall process the data for one 24th281
of the coverage in � for one of the positive and the negative sides of ⌘.282
Figure 3.1 shows a simplified block diagram of Endcap SL. Figure 3.2 shows also a block diagram but the283
elements are shown one by one. CERN-developed IPMC shall be used for basic blade control and configura-284
tion at power up through the ATCA shelf manager. The Endcap SL interfaces with the TDAQ servers [6] and285
DCS [8] via MPSoC mezzanine for control and monitoring.286
TGC6FireFlyforreceivers4FireFlyfortransmitters
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MDT1FireFlyforreceivers1FireFlyfortransmitters
NSW,RPC(BIS78),andTile1FireFlyforreceivers
IPMC ShelfManagerIPMI
Figure 3.1: A simplified block diagram of the Endcap SL.
3.2 FPGA287
The FPGA selected in the preliminary design is Xilinx Virtex UltraScale+ FPGA (XCVU9P-1FLGA2577E).288
This type of FPGA has the following features.289
• System logic cells: 2,586k290
• DSP slices: 6840291
• Memory (Block RAM): 75.9 Mb292
3. Hardware Page 9 of ??
22nd IEEE Real Time Conference Yuya Mino
Firmware implementation for NSW coincidence logic
Each muon candidate from TGC BW is compared with 16 track candidates from NSW.
Limitation on the latency is set to 2 LHC clocks (40 MHz) in Run 3. ①Coincidence is calculated in parallel using two identical LUTs with 320 MHz clock.
→ 2 × 8 = 16 candidates can be processed in 1 LHC clock. ②The best candidate is chosen in the pT selection.
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TGC BW
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pT selection
Track Coincidence
NSW Coincidence
Track Coincidence
pT (4-bit)
pT (4-bit)
pT (4-bit)
pT (4-bit)
RoI (3-bit)
× 8 tracks
× 8 tracks
……
16 NSW segments are split into 2 × segments and are put into two exactly the same LUTs
Choose the highest pT among the 16 candidates
22nd IEEE Real Time Conference Yuya Mino
Performance of Level-1 endcap muon trigger in Run 3Efficiency Rejection power for low pT muons is estimated from a single muon MC simulation sample. Higher reduction for low pT muons relative to Run 2 trigger. ~ 95% relative efficiency for muons with pT > 20 GeV.
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ATLAS Simulation Preliminary
Low pT muons reduced by new coincidence logic
Trigger rate Rejection power for fake muons is estimated from 2017 data. (fake muons cannot be modeled by MC) ~ 90% of fake muons are reduced by new inner muon detectors compared to Run 2 logic. Expected trigger rate in Run 3 is 13 kHz . (~ 53% rate reduction)
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20 GeV≥ T
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ATLAS Preliminary
Fake muons highly reduced by new detectors
ATLAS L1Muon Trigger Public Results ATLAS L1Muon Trigger Public Results
HL-LHC
22nd IEEE Real Time Conference Yuya Mino
Level-0 endcap muon trigger in HL-LHCRequired to reconstruct muon candidates with an improved momentum resolution to suppress trigger rate with minimal efficiency loss. Trigger and readout electronics will be replaced to extend latency and acceptable rate. All TGC hit signals transferred from new boards on the detector side. - Track reconstruction using full-granular information will be enabled. MDT (precision measurement detector) will be included in the first-level trigger to recalculate pT with higher precision.
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Tile Calorimeter - Position
New Small Wheel (NSW) - Position & Angle
TGC EI - Position
Monitored Drift Tube (MDT) - Position & Angle
Detector for precise segment reconstruction Software-based trigger (Run2, Run3)
↓ Hardware-based trigger (HL-LHC)
TGC Big Wheel - Position & Angle
Track reconstruction using all hit signals will be implemented
22nd IEEE Real Time Conference Yuya Mino
TGC track reconstruction
15
Tracks are reconstructed in TGC with a pattern matching algorithm. Comparing the TGC hits with predefined hit-lists for high-pT muons. Each predefined hit pattern has angle and position information associated to a track segment. Coverage of the lowest pT in the
hit-lists is 4 GeVN
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TGC track segment reconstruction
Input(Position ID, 16 bit)
Output(Track segment, 18 bit)
3 4 4 Position𝑎, α𝑎, 𝑝T threshold𝑎3 4 5 Position𝒃, હ𝒃, 𝒑𝐓 thresho𝐥𝐝𝒃
3 5 5 Position𝑐 , α𝑐 , 𝑝T threshold𝑐
Hit ch: B B BÆ M1 Position ID: 3
Hit ch: B C ÆM2 Position ID: 4
Hit ch: C CÆ M3 Positon ID: 5
M1 Coincidence
M2 Coincidence
M3 Coincidence
1. Station coincidence- Take coincidence for each of
o M1, M2, and M3.
2. Segment extraction- Extract segment position and angle
oo from predefined channel list.
• Track segment reconstruction with pattern matching is under study. • Each track segment is connected to a pattern of TGC hits and stored in
channel lists.
July 12th, 2019 EPS-HEP2019, Belgium 8
y
z ~ 6 million patterns for whole TGC region.
Position ηa , Angle Δθa
Position ηb , Angle Δθb
Position ηc , Angle Δθc
① Station Coincidence ② Extraction of track information
3 4 5Position ID
Not
revi
ewed
,for
inte
rnal
circ
ulat
ion
only
TGC track segment reconstruction
Input(Position ID, 16 bit)
Output(Track segment, 18 bit)
3 4 4 Position𝑎, α𝑎, 𝑝T threshold𝑎3 4 5 Position𝒃, હ𝒃, 𝒑𝐓 thresho𝐥𝐝𝒃
3 5 5 Position𝑐 , α𝑐 , 𝑝T threshold𝑐
Hit ch: B B BÆ M1 Position ID: 3
Hit ch: B C ÆM2 Position ID: 4
Hit ch: C CÆ M3 Positon ID: 5
M1 Coincidence
M2 Coincidence
M3 Coincidence
1. Station coincidence- Take coincidence for each of
o M1, M2, and M3.
2. Segment extraction- Extract segment position and angle
oo from predefined channel list.
• Track segment reconstruction with pattern matching is under study. • Each track segment is connected to a pattern of TGC hits and stored in
channel lists.
July 12th, 2019 EPS-HEP2019, Belgium 8
y
z ~ 6 million patterns for whole TGC region.
Not
revi
ewed
,for
inte
rnal
circ
ulat
ion
only
TGC track segment reconstruction
Input(Position ID, 16 bit)
Output(Track segment, 18 bit)
3 4 4 Position𝑎, α𝑎, 𝑝T threshold𝑎3 4 5 Position𝒃, હ𝒃, 𝒑𝐓 thresho𝐥𝐝𝒃
3 5 5 Position𝑐 , α𝑐 , 𝑝T threshold𝑐
Hit ch: B B BÆ M1 Position ID: 3
Hit ch: B C ÆM2 Position ID: 4
Hit ch: C CÆ M3 Positon ID: 5
M1 Coincidence
M2 Coincidence
M3 Coincidence
1. Station coincidence- Take coincidence for each of
o M1, M2, and M3.
2. Segment extraction- Extract segment position and angle
oo from predefined channel list.
• Track segment reconstruction with pattern matching is under study. • Each track segment is connected to a pattern of TGC hits and stored in
channel lists.
July 12th, 2019 EPS-HEP2019, Belgium 8
y
z ~ 6 million patterns for whole TGC region.
TGC tracks extracted in two steps① Take coincidence to set a position in each station.
② Extract track information from the pattern list.
22nd IEEE Real Time Conference Yuya Mino
Hardware design of Sector Logic in HL-LHCEndcap Sector Logic in HL-LHC is required to have ① Enough I/O ports to handle hit data from every TGC channel. (~ 6700 ch) ② A few hundred Mbits of memory resources to reconstruct track segments.
16
Not
revi
ewed
,for
inte
rnal
circ
ulat
ion
only
DRAFT
Preliminary Design for Endcap Sector Logic July 10, 2020 - Version 1.0
3 Hardware270
3.1 Overview271
The Endcap SL will be introduced in L0Muon as a part of the ATLAS upgrade for HL-LHC. It receives hits from272
the TGC PS boards, track segments from NSWTP, coincidence outputs of BIS78 RPC from Barrel SL, and273
energy flag for Tile coincidence, indicating whether or not the signal pulse is greater than the threshold [2,274
4]. The Endcap SL sends TCs with pT
thresholds satisfied and NSW track segments to the MDTTP. The275
Endcap SL receives the TCs from the MDTTP, where pT
evaluated with the MDT hits is included if the276
evaluation is possible. The Endcap SL sends mTCs to MUCTPI. In addition, the Endcap SL is responsible277
for the transmission of the TGC hits and the trigger information, including NSW, BIS78 RPC, and Tile data,278
downstream to FELIX for readout. The Endcap SL receives the TTC signals from FELIX. The Endcap SL is279
responsible also for the transmission of the configuration signals to the TGC PS boards.280
The Endcap SL system consists of 48 ATCA blades. An ATCA blade shall process the data for one 24th281
of the coverage in � for one of the positive and the negative sides of ⌘.282
Figure 3.1 shows a simplified block diagram of Endcap SL. Figure 3.2 shows also a block diagram but the283
elements are shown one by one. CERN-developed IPMC shall be used for basic blade control and configura-284
tion at power up through the ATCA shelf manager. The Endcap SL interfaces with the TDAQ servers [6] and285
DCS [8] via MPSoC mezzanine for control and monitoring.286
TGC6FireFlyforreceivers4FireFlyfortransmitters
12
12
12
12
12
12
12
12
12
12
12
12
12
VirtexUltraScale+
-SectorLogic-ReadoutLogic-Control-Monitoring
AXIC2C ZynqUltraScale+MPSoC
MUCTPI1QSFP+
FELIX1QSFP+
TDAQServers/DCSEthernet
4
4
4
4
MDT1FireFlyforreceivers1FireFlyfortransmitters
NSW,RPC(BIS78),andTile1FireFlyforreceivers
IPMC ShelfManagerIPMI
Figure 3.1: A simplified block diagram of the Endcap SL.
3.2 FPGA287
The FPGA selected in the preliminary design is Xilinx Virtex UltraScale+ FPGA (XCVU9P-1FLGA2577E).288
This type of FPGA has the following features.289
• System logic cells: 2,586k290
• DSP slices: 6840291
• Memory (Block RAM): 75.9 Mb292
3. Hardware Page 9 of ??
① Optical interfaces are placed to use GTY* connection
Schematic of Sector Logic
② 2160 × 36 Kb Block RAM 960 × 288 Kb UltraRAM × 10 times the resource compared to the FPGA used in Run 3
Xilinx Virtex UltraScale+ XCVU9P
For TGC BW, TGC EI ( ~ 6700 ch) 8.0 Gbps/lane
For NSW, RPC BIS78, Tile 6.4 - 9.6 Gbps/lane
For MDT 9.6 Gbps/lane
* GTY: multi-gigabit transceivers for Xilinx UltraScale FPGAs
The design of schematic and layout is ongoing.
22nd IEEE Real Time Conference Yuya Mino
Track Extractor
Station Coincidence
Track reconstruction
RAM Address (12-bit)
M1 3/3 coincidenceM1 2/3 coincidenceM1 1/3 coincidence
M2 2/2 coincidenceM2 1/2 coincidence
M3 2/2 coincidenceM3 1/2 coincidence
M1 hit
M2 hit
M3 hitM3 position ID (2-bit)
M3 position ID (2-bit)
M2 position ID (5-bit)
M2 position ID (5-bit)
M1 position ID (5-bit)
M1 position ID (5-bit)
M1 position ID (5-bit)
RAM Address Generator
TGC Big Wheel Track
information (18-bit)
Firmware implementation for track reconstruction
17
Position IDs are combined to create the RAM address which the hit pattern corresponds to.
RAM
Track corresponding to the RAM address is extracted from RAM.
22nd IEEE Real Time Conference Yuya Mino
Performance of Level-0 endcap muon trigger in HL-LHCEfficiency Expected efficiency of the new trigger algorithm with respect to offline muons in an MC sample. Compared to Run 2 trigger. Higher efficiency (~ 4%) in the plateau region due to the looser coincidence. Better rejection for low pT muons.
18
[GeV]T
Offline muon p0 5 10 15 20 25 30 35 40 45 50
Effic
ienc
y
00.10.20.30.40.50.60.70.80.9
1
Single Muon MCHL-LHC Level-0 trigger
DataRun-2 Level-1 trigger
ATLAS PreliminaryPreliminary 2.4£| µ
h |£20 GeV threshold, 1.05
Trigger rate Estimated trigger rate from Run-2 data taken with random trigger to reproduce higher luminosity expected in HL-LHC. Rate for 20 GeV threshold is about 23 kHz . (constitutes only about 2.3% of the assumed total Level-0 trigger rate of 1 MHz) Further rate reduction in the next step with MDT is expected.
]-1s-2cm34Luminosity [100 1 2 3 4 5 6 7 8
Leve
l-0 m
uon
trigg
er ra
te [k
Hz]
05
101520253035404550
ATLAS PreliminaryData 2016 ZeroBias with event overlaying
2.4£| µh |£20 GeV threshold, 1.05
HL-LHC
ATLAS L0Muon Trigger Public Results
22nd IEEE Real Time Conference Yuya Mino
SummaryContinuous upgrades of the hardware-based (Level-1/0) endcap muon trigger is planned for Run 3 and HL-LHC.
Run 3 New inner muon detectors with fine track information will be installed. New trigger processor board (SL) has been produced for Run 3.
New trigger using new detectors shows higher reduction of low pT muons compared to current trigger system. Estimated Level-1 endcap muon trigger rate for 20 GeV threshold is ~ 13 kHz . (@ 2 × 1034 cm-2s-1)
HL-LHC Trigger and readout electronics will be replaced. Fast track segment reconstruction will be implemented. Preliminary design of the trigger processor board and firmware has been made.
New trigger shows ~ 4% higher efficiency than current trigger system. Estimated Level-0 endcap muon trigger rate for 20 GeV threshold is ~ 23 kHz . (@ 7.5 × 1034 cm-2s-1) Further rate reduction is expected by MDT track trigger.
19
Back up
22nd IEEE Real Time Conference Yuya Mino
Endcap muon trigger system in Run 3
21
第 2章 ATLAS エンドキャップミューオントリガー 40
threshold [GeV]T
p5 10 15 20 25 30 35 40 45
Muo
n le
vel-1
trig
ger r
ate
[Hz]
410
510
610= 14 TeVs -1s-2 cm34 10×L=3
Extrapolationwith 2012-run settingExtrapolationwith Pre-phase1Extrapolationwith Pre-phase1 + NSW
ATLAS
図 2.22 Run-3における Upgrade 前後のトリガーレート。黒い点は Run-1 終了直前のトリガーシステムの場合のトリガーレートを示す。青い四角の点はRun-2終了時点(Phase-1 Upgrade
直前)の場合の、赤い三角の点は NSW のコインシデンスを導入した場合のトリガーレートである。
TGC-BW NSW
BW1 BW2 BW3sTGC1 sTGC2MM1 MM2
2/3 coin. 3/4 coin.
HPT board3-station coin.
Front end board
sTGC trigger processor
MM trigger processor
Sector LogicOther detector
Track information (Δθ, ηNSW, ΦNSW)
Hit information (ηBW, ΦBW, ΔR, ΔΦ)
(ηBW, ΦBW)
muon
IP
(ηNSW, ΦNSW)
(ΔR, ΔΦ)
Δθ
Trigger decisions MUCTPi
(Tile, BIS7/8…)
vector information
Newly developed for Run-3
図 2.23 Phase-1 Upgrade 後のエンドキャップミューオントリガーの概要。BW と NSW の情報を合わせてトリガー判定を行う、新たな Sector Logic ボードの開発が必要である。
22nd IEEE Real Time Conference Yuya Mino
New Small WheelConsist of small-strip TGC and Micromegas sTGC (small strip TGC) - Strips with a 3.2mm pitch for precision readout (Current strip width of TGC is > 15 mm) - Cathode plane on the other side has pads for triggering Micromegas (micro mesh gaseous structure) - Main tracking chamber for precise segment reconstruction - 8 layers are sandwiched by 4 layers of sTGC
22
2014 JINST 9 C03016
Figure 1. Left: MM detector structure of a standard non resistive MM chamber. Right: principle of operationfor a resistive MM chamber with x readout strips of 400µm pitch.
Figure 2. Spark resistant micromegas. Sketch of the resistive and readout strip structure.
was started in 2007, called Muon ATLAS MicroMegas Activity (MAMMA), to explore the poten-tial of the MM technology for its use in LHC detectors. As of May 2013 ATLAS decided to equipthe New Small Wheel (NSW) with MM detectors [4], combining triggering and precision trackingfunctionality in a single device [5].
2 Micromegas detectors in ATLAS
In order to test the micromegas detectors under realistic LHC conditions five small micromegaschambers were installed in the ATLAS detector in February 2012, until the end of the data taking inFebruary 2013 (figure 3). One prototype resistive micromegas detector, with two gas gaps sharing acommon drift plane (namely MBT03 and MBT04), with an active area of 9⇥4.5cm2 was installedin the high-rate environment in front of the electromagnetic end-cap calorimeter (LAr), 3.5m fromthe interaction point in the z direction, at a radius r ⇠ 1m (figure 5 left). Four standard 9⇥10cm2
resistive detectors (R13,16,18,19) were installed on the ATLAS Small Wheel (SW), Cathode StripChamber (CSC) region, at 1.8m distance from the beam pipe (figure 5 right).
In the work presented here we measure the hit rate of the different ATLAS regions wherethe micromegas chambers were installed. We demonstrate also, even with a random trigger, thatrecorded hits in the adjacent chambers can be correlated indicating real particle tracks. We thenstudy the correlation of the MBT chamber’s current with the luminosity of ATLAS demonstratingthe capability of micromegas detector for luminosity measurement.
– 2 –
4 sTGC detector technology and
performance
In Chapter 2 the requirements for the triggering system in the NSW have been defined. Thetriggering detectors should provide bunch crossing identification, requiring good time resolution,and good angular resolution, better than 1 mrad, for online reconstructed segments, which in turnentails fairly good online spatial resolution. The sTGC detector provides both capabilities as willbe demonstrated in this chapter and for this reason is regarded as the main triggering detectorin the NSW. It provides also a fair spatial resolution for the offline tracking that will help theprecision tracking, specially during the HL-LHC phase.
4.1 sTGC
The basic Small strip Thin Gap Chamber sTGC structure is shown in Fig. 4.1(a). It consistsof a grid of 50µm gold-plated tungsten wires with a 1.8mm pitch, sandwiched between twocathode planes at a distance of 1.4mm from the wire plane. The cathode planes are made of agraphite-epoxy mixture with a typical surface resistivity of 100 k⌦/⇤ sprayed on a 100µm thickG-10 plane, behind which there are on one side strips (that run perpendicular to the wires) andon the other pads (covering large rectangular surfaces), on a 1.6 mm thick PCB with the shieldingground on the opposite side (see Fig. 4.1(b)). The strips have a 3.2mm pitch, much smaller thanthe strip pitch of the ATLAS TGC, hence the name ’Small TGC’ for this technology.
A similar type of structure was used in the past for the OPAL Pole-Tip calorimeter, where 400detectors were constructed and run for 12 years.
The TGC system, used in the present ATLAS muon end-cap trigger system, has passed a longphase of R&D and testing. The basic detector design for the NSW has two quadruplets 35 cmapart in z. Each quadruplet contains four TGC’s, each TGC with pad, wire and strip readout.
(a) a (b) b
Figure 4.1: The sTGC internal structure.
37
sTGC Micromegas
Notreviewed,forinternalcirculationonly
DR
AFT
Pre
lim
ina
ry
De
sig
nfo
rE
nd
ca
pS
ecto
rL
og
icJu
ly1
0,
20
20
-V
ers
io
n1
.0
3H
ard
ware
27
0
3.1
Overview
27
1
The
Endcap
SL
willbe
introduced
inL0M
uon
as
apartofthe
AT
LA
Supgrade
for
HL-LH
C.Itreceiv
es
hits
from
27
2
the
TG
CP
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track
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ents
from
NS
WT
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ence
outputs
of
BIS
78
RP
Cfrom
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and
27
3
energy
flag
for
Tile
coin
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ence,
indic
atin
gw
hether
or
not
the
sig
nal
puls
eis
greater
than
the
threshold
[2,
27
4
4].
The
Endcap
SL
sends
TC
sw
ith
pT
threshold
ssatis
fied
and
NS
Wtrack
segm
ents
to
the
MD
TT
P.
The
27
5
Endcap
SL
receiv
es
the
TC
sfrom
the
MD
TT
P,
where
pT
evalu
ated
with
the
MD
Thits
isin
clu
ded
ifthe
27
6
evalu
atio
nis
possib
le.
The
Endcap
SL
sends
mT
Cs
to
MU
CT
PI.
In
additio
n,
the
Endcap
SL
isresponsib
le2
77
for
the
transm
issio
nof
the
TG
Chits
and
the
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ger
info
rm
atio
n,
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IS
78
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27
8
dow
nstream
to
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for
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nals
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.T
he
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79
responsib
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rthe
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issio
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nals
to
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28
0
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consis
ts
of
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AT
CA
bla
des.
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AT
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de
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28
1
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for
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positiv
eand
the
negativ
esid
es
of⌘.
28
2
Fig
ure
3.1
show
sa
sim
plified
blo
ck
dia
gram
ofE
ndcap
SL.F
igure
3.2
show
sals
oa
blo
ck
dia
gram
butthe
28
3
ele
ments
are
show
none
by
one.
CE
RN
-develo
ped
IP
MC
shall
be
used
for
basic
bla
de
controland
configura-
28
4
tio
nat
pow
er
up
through
the
AT
CA
shelf
manager.
The
Endcap
SL
interfa
ces
with
the
TD
AQ
servers
[6]
and
28
5
DC
S[8]via
MP
SoC
mezzanin
efo
rcontroland
monitorin
g.
28
6
TGC
6FireFlyforreceivers
4FireFlyfortransmitters
12
12
12
12
12
12
12
12
12
12
12
12
12
VirtexUltraScale+
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onitoring
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IPMC
ShelfM
anager
IPMI
Fig
ure
3.1:
Asim
plified
blo
ck
dia
gram
ofthe
Endcap
SL.
3.2
FP
GA
28
7
The
FP
GA
sele
cted
inthe
prelim
inary
desig
nis
Xilin
xV
irtex
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cale
+F
PG
A(X
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28
9
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2,586k
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DRAFT
Pre
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ary
De
sig
nfo
rE
nd
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ecto
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og
ic
Ju
ly
10
,2
02
0-
Ve
rs
io
n1
.0
3H
ard
ware
27
0
3.1
Overview
27
1
The
Endcap
SL
willbe
introduced
in
L0M
uon
as
apartofthe
AT
LA
Supgrade
for
HL-LH
C.Itreceives
hits
from
27
2
the
TG
CP
Sboards,
track
segm
ents
from
NS
WT
P,
coincidence
outputs
of
BIS
78
RP
Cfrom
BarrelS
L,
and
27
3
energy
flag
for
Tile
coincidence,
indicating
whether
or
not
the
signal
pulse
is
greater
than
the
threshold
[2,
27
4
4].
The
Endcap
SL
sends
TC
sw
ith
pT
thresholds
satisfied
and
NS
Wtrack
segm
ents
to
the
MD
TT
P.
The
27
5
Endcap
SL
receives
the
TC
sfrom
the
MD
TT
P,
where
pT
evaluated
with
the
MD
Thits
is
included
if
the
27
6
evaluation
is
possible.
The
Endcap
SL
sends
mT
Cs
to
MU
CT
PI.
In
addition,
the
Endcap
SL
is
responsible
27
7
for
the
transm
ission
of
the
TG
Chits
and
the
trigger
inform
ation,
including
NS
W,
BIS
78
RP
C,
and
Tile
data,
27
8
dow
nstream
to
FE
LIX
for
readout.
The
Endcap
SL
receives
the
TT
Csignals
from
FE
LIX
.T
he
Endcap
SL
is
27
9
responsible
also
for
the
transm
ission
ofthe
configuration
signals
to
the
TG
CP
Sboards.
28
0
The
Endcap
SL
system
consists
of
48
AT
CA
blades.
An
AT
CA
blade
shallprocess
the
data
for
one
24th
28
1
ofthe
coverage
in�
for
one
ofthe
positive
and
the
negative
sides
of⌘.
28
2
Figure
3.1
show
sa
sim
plified
block
diagram
ofE
ndcap
SL.F
igure
3.2
show
salso
ablock
diagram
butthe
28
3
elem
ents
are
show
none
by
one.
CE
RN
-developed
IP
MC
shallbe
used
for
basic
blade
controland
configura-
28
4
tion
at
pow
er
up
through
the
AT
CA
shelf
manager.
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Endcap
SL
interfaces
with
the
TD
AQ
servers
[6]
and
28
5
DC
S[8]via
MP
SoC
mezzanine
for
controland
monitoring.
28
6
TGC
6FireFlyforreceivers
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12
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1FireFlyforreceivers
IPMC
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IPMI
Fig
ure
3.1:
Asim
plified
block
diagram
ofthe
Endcap
SL.
3.2
FP
GA
28
7
The
FP
GA
selected
in
the
prelim
inary
design
is
Xilinx
Virtex
UltraS
cale+
FP
GA
(X
CV
U9P
-1F
LG
A2577E
).
28
8
This
type
ofF
PG
Ahas
the
follow
ing
features.
28
9
•S
ystem
logic
cells:
2,586k
29
0
•D
SP
slices:
6840
29
1
•M
em
ory
(B
lock
RA
M):75.9
Mb
29
2
3.
Ha
rd
wa
re
Pa
ge
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f?
?
Notreviewed,forinternalcirculationonly
DRAFT
Pre
lim
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ary
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sig
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rE
nd
ca
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ecto
rL
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ic
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ly
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,2
02
0-
Ve
rs
io
n1
.0
3H
ard
ware
27
0
3.1
Overview
27
1
The
Endcap
SL
willbe
introduced
in
L0M
uon
as
apartofthe
AT
LA
Supgrade
for
HL-LH
C.Itreceives
hits
from
27
2
the
TG
CP
Sboards,
track
segm
ents
from
NS
WT
P,
coincidence
outputs
of
BIS
78
RP
Cfrom
BarrelS
L,
and
27
3
energy
flag
for
Tile
coincidence,
indicating
whether
or
not
the
signal
pulse
is
greater
than
the
threshold
[2,
27
4
4].
The
Endcap
SL
sends
TC
sw
ith
pT
thresholds
satisfied
and
NS
Wtrack
segm
ents
to
the
MD
TT
P.
The
27
5
Endcap
SL
receives
the
TC
sfrom
the
MD
TT
P,
where
pT
evaluated
with
the
MD
Thits
is
included
if
the
27
6
evaluation
is
possible.
The
Endcap
SL
sends
mT
Cs
to
MU
CT
PI.
In
addition,
the
Endcap
SL
is
responsible
27
7
for
the
transm
ission
of
the
TG
Chits
and
the
trigger
inform
ation,
including
NS
W,
BIS
78
RP
C,
and
Tile
data,
27
8
dow
nstream
to
FE
LIX
for
readout.
The
Endcap
SL
receives
the
TT
Csignals
from
FE
LIX
.T
he
Endcap
SL
is
27
9
responsible
also
for
the
transm
ission
ofthe
configuration
signals
to
the
TG
CP
Sboards.
28
0
The
Endcap
SL
system
consists
of
48
AT
CA
blades.
An
AT
CA
blade
shallprocess
the
data
for
one
24th
28
1
ofthe
coverage
in�
for
one
ofthe
positive
and
the
negative
sides
of⌘.
28
2
Figure
3.1
show
sa
sim
plified
block
diagram
ofE
ndcap
SL.F
igure
3.2
show
salso
ablock
diagram
butthe
28
3
elem
ents
are
show
none
by
one.
CE
RN
-developed
IP
MC
shallbe
used
for
basic
blade
controland
configura-
28
4
tion
at
pow
er
up
through
the
AT
CA
shelf
manager.
The
Endcap
SL
interfaces
with
the
TD
AQ
servers
[6]
and
28
5
DC
S[8]via
MP
SoC
mezzanine
for
controland
monitoring.
28
6
TGC
6FireFlyforreceivers
4FireFlyfortransmitters
12
12
12
12
12
12
12
12
12
12
12
12
12
VirtexUltraScale+
-SectorLogic
-ReadoutLogic
-Control
-Monitoring
AXIC2C
Zynq
UltraScale+
MPSoC
MUCTPI
1QSFP+
FELIX
1QSFP+
TDAQServers/DCS
Ethernet
4444
MDT
1FireFlyforreceivers
1FireFlyfortransmitters
NSW,RPC(BIS78),andTile
1FireFlyforreceivers
IPMC
ShelfManager
IPMI
Fig
ure
3.1:
Asim
plified
block
diagram
ofthe
Endcap
SL.
3.2
FP
GA
28
7
The
FP
GA
selected
in
the
prelim
inary
design
is
Xilinx
Virtex
UltraS
cale+
FP
GA
(X
CV
U9P
-1F
LG
A2577E
).
28
8
This
type
ofF
PG
Ahas
the
follow
ing
features.
28
9
•S
ystem
logic
cells:
2,586k
29
0
•D
SP
slices:
6840
29
1
•M
em
ory
(B
lock
RA
M):75.9
Mb
29
2
3.
Ha
rd
wa
re
Pa
ge
9o
f?
?
4 layer 8 layer 4 layer
sTGC Micromegas sTGC
muon
Position resolution : ~ 30 μm Angle resolution : ~ 0.3 mrad
22nd IEEE Real Time Conference Yuya Mino
Block diagram of SL firmware in Run 3
23
ATLAS Phase-I UpgradeLevel-1 Endcap Muon Trigger
Full Design ReportDraft 0.51, September 4, 2020 03:21
4 Firmware for the Sector Logic488
4.1 Overview489
A diagram for the Sector Logic firmware is shown in Figure 33. The firmware has two main490
data flow, Trigger line and Readout line. Each of these 2 functions are referred to as “Trigger491
Firmware” and “Readout Firmare” in Figure 33. Other than these two main data flow part, there492
are Data Receiver and Data Transmitter part, which include GTX RX and TX inteface and delaylogic for the received data.493
BW Coinci- dence
12 optical inputs
via GTX
14 optical inputs
via G-Link
TTC signals
Trigger Buffer
Zero- Suppress SiTCP
16-bit
16-bit
……
total 202-bit
1582-bit
160-bit
48-bit
16-bit 16-bit 8-bit to Ethernet PHY
……
160-bit
delay
16-bitdelay
delay
delay
delay
delay
delay
delay
delayID
Counter
GTX
RX interface
Inner Coin. (η:Θ)
Derando-mizer
GTX
TX interface
to SFP+ Module
160-bit
Trigger Firmware
Readout Firmware
LHC 40MHz Clock
G-Link Recovery Clock
GTX RXUSRCLK
GTX TX USRCLK
Readout 160MHz Clock
TCP/IP 125MHz System Clock
Clock Source
112-bit
112-bit
112-bit
decoder
decoder
decoder
decoder
track selector
× 38…
4-bit
alignment and
decoder
4-bit
4-bit
1-bit
1-bit
4-bit
SSC
Inner Coin. (η:φ)
pT merger (BW-Inner Coin.)
Level-1 Buffer (TGC BW)Level-1 Buffer (Inner)
3-bit
Coincidence Clock (160 MHz or 320 MHz)
Figure 33: Overview of the New Sector Logic firmware.
Figure 34 is the more detailed diagram for the top-module of the New Sector Logic firmware.Data width and the connection between each sub-mudule is shown in detail. Different line colorin the diagram correspond to different clock domain.494
The function of each sub-mudules are explained in the following sections.495
31
22nd IEEE Real Time Conference Yuya Mino
Readout logic in Run-3
24
Trigger Buffer
Zero- Suppress SiTCP
1582-bit
160-bit
48-bit
16-bit 16-bit 8-bit to Ethernet PHY
160-bit
ID Counter
Derando-mizer
Readout Firmware
Level-1 Buffer (TGC BW)Level-1 Buffer (Inner)
Readout 160 MHz clockLHC 40 MHz clockTCP/IP 125 MHz system clock
Not
revi
ewed
,for
inte
rnal
circ
ulat
ion
only
DRAFT
Preliminary Design for Endcap Sector Logic July 10, 2020 - Version 1.0
3 Hardware270
3.1 Overview271
The Endcap SL will be introduced in L0Muon as a part of the ATLAS upgrade for HL-LHC. It receives hits from272
the TGC PS boards, track segments from NSWTP, coincidence outputs of BIS78 RPC from Barrel SL, and273
energy flag for Tile coincidence, indicating whether or not the signal pulse is greater than the threshold [2,274
4]. The Endcap SL sends TCs with pT
thresholds satisfied and NSW track segments to the MDTTP. The275
Endcap SL receives the TCs from the MDTTP, where pT
evaluated with the MDT hits is included if the276
evaluation is possible. The Endcap SL sends mTCs to MUCTPI. In addition, the Endcap SL is responsible277
for the transmission of the TGC hits and the trigger information, including NSW, BIS78 RPC, and Tile data,278
downstream to FELIX for readout. The Endcap SL receives the TTC signals from FELIX. The Endcap SL is279
responsible also for the transmission of the configuration signals to the TGC PS boards.280
The Endcap SL system consists of 48 ATCA blades. An ATCA blade shall process the data for one 24th281
of the coverage in � for one of the positive and the negative sides of ⌘.282
Figure 3.1 shows a simplified block diagram of Endcap SL. Figure 3.2 shows also a block diagram but the283
elements are shown one by one. CERN-developed IPMC shall be used for basic blade control and configura-284
tion at power up through the ATCA shelf manager. The Endcap SL interfaces with the TDAQ servers [6] and285
DCS [8] via MPSoC mezzanine for control and monitoring.286
TGC6FireFlyforreceivers4FireFlyfortransmitters
12
12
12
12
12
12
12
12
12
12
12
12
12
VirtexUltraScale+
-SectorLogic-ReadoutLogic-Control-Monitoring
AXIC2C ZynqUltraScale+MPSoC
MUCTPI1QSFP+
FELIX1QSFP+
TDAQServers/DCSEthernet
4
4
4
4
MDT1FireFlyforreceivers1FireFlyfortransmitters
NSW,RPC(BIS78),andTile1FireFlyforreceivers
IPMC ShelfManagerIPMI
Figure 3.1: A simplified block diagram of the Endcap SL.
3.2 FPGA287
The FPGA selected in the preliminary design is Xilinx Virtex UltraScale+ FPGA (XCVU9P-1FLGA2577E).288
This type of FPGA has the following features.289
• System logic cells: 2,586k290
• DSP slices: 6840291
• Memory (Block RAM): 75.9 Mb292
3. Hardware Page 9 of ??
Trigger decision information from Trigger logic
Not
revi
ewed
,for
inte
rnal
circ
ulat
ion
only
DRAFT
Preliminary Design for Endcap Sector Logic July 10, 2020 - Version 1.0
3 Hardware270
3.1 Overview271
The Endcap SL will be introduced in L0Muon as a part of the ATLAS upgrade for HL-LHC. It receives hits from272
the TGC PS boards, track segments from NSWTP, coincidence outputs of BIS78 RPC from Barrel SL, and273
energy flag for Tile coincidence, indicating whether or not the signal pulse is greater than the threshold [2,274
4]. The Endcap SL sends TCs with pT
thresholds satisfied and NSW track segments to the MDTTP. The275
Endcap SL receives the TCs from the MDTTP, where pT
evaluated with the MDT hits is included if the276
evaluation is possible. The Endcap SL sends mTCs to MUCTPI. In addition, the Endcap SL is responsible277
for the transmission of the TGC hits and the trigger information, including NSW, BIS78 RPC, and Tile data,278
downstream to FELIX for readout. The Endcap SL receives the TTC signals from FELIX. The Endcap SL is279
responsible also for the transmission of the configuration signals to the TGC PS boards.280
The Endcap SL system consists of 48 ATCA blades. An ATCA blade shall process the data for one 24th281
of the coverage in � for one of the positive and the negative sides of ⌘.282
Figure 3.1 shows a simplified block diagram of Endcap SL. Figure 3.2 shows also a block diagram but the283
elements are shown one by one. CERN-developed IPMC shall be used for basic blade control and configura-284
tion at power up through the ATCA shelf manager. The Endcap SL interfaces with the TDAQ servers [6] and285
DCS [8] via MPSoC mezzanine for control and monitoring.286
TGC6FireFlyforreceivers4FireFlyfortransmitters
12
12
12
12
12
12
12
12
12
12
12
12
12
VirtexUltraScale+
-SectorLogic-ReadoutLogic-Control-Monitoring
AXIC2C ZynqUltraScale+MPSoC
MUCTPI1QSFP+
FELIX1QSFP+
TDAQServers/DCSEthernet
4
4
4
4
MDT1FireFlyforreceivers1FireFlyfortransmitters
NSW,RPC(BIS78),andTile1FireFlyforreceivers
IPMC ShelfManagerIPMI
Figure 3.1: A simplified block diagram of the Endcap SL.
3.2 FPGA287
The FPGA selected in the preliminary design is Xilinx Virtex UltraScale+ FPGA (XCVU9P-1FLGA2577E).288
This type of FPGA has the following features.289
• System logic cells: 2,586k290
• DSP slices: 6840291
• Memory (Block RAM): 75.9 Mb292
3. Hardware Page 9 of ??
Hit information from TGC BW
Hit information from Inner muon detectors
TTC signals
Clock Source
① L1 Buffer : Stores data from detectors until the L1 Accept signal arrives
② Derandomizer : Buffer data up to ~ 193 events by combining 4 FIFOs
③ Zero Suppress: Data suppression by rejecting “zero” data
④ SiTCP: Data is translated into TCP/IP
22nd IEEE Real Time Conference Yuya Mino
FPGA resource utilization in Run 3
25
Resource Utilization Available Utilization %
LUT 32468 254200 12.77
BRAM 479.50 795 60.31
I/O 401 500 80.20
GTX 12 16 75.00
Resource utilization is calculated by Vivado software. Firmware includes full readout and trigger firmware. BRAMs are mainly used for large LUTs for coincidence logics. TGC BW coincidence : ~ 9.6% NSW coincidence : ~ 24.7% RPC coincidence : ~ 7.5%
22nd IEEE Real Time Conference Yuya Mino
Estimated latency requirement in Run3
26
Latency contributions of New Sector Logic in units of BC (25 ns)
ATLAS Phase-I UpgradeLevel-1 Endcap Muon Trigger
Full Design ReportDraft 0.51, September 4, 2020 03:21
11 Latency1143
The latency numbers are given in Table 19, where the numbers of the TGC-BW have been1144
measured and others are estimated or taken from the R&D. Input signals from TGC-BW are1145
delivered to the Sector Logic board at the timing of 37 BCs from pp collisions, while those1146
from NSW are at the timing of 41.1 BCs. Signals from EI-TGC, Tile-calorimeter D-layer cells1147
(D5, D6), or RPC BIS7/8 chambers would be faster than NSW signals (41.1 BCs [11, 12]).1148
The TGC-BW coincidence will be started before arriving the signal from NSW, then the Sector1149
Logic wait about 6 BCs for NSW. The delivery time to the MUCTPI is 53 BCs, which is one BC1150
earlier than one which we have discussed in the Level-1 latency task force [13]. After careful1151
calculation and the integration test with MUCTPI prototype board which we found 4.5 BCs are1152
needed for GTX-TX/RX latency [14], there is no margin to recover the increasing NSW latencyin the Sector Logic anymore.
New Small Wheel Big Wheel TGC (measured)nsec BCs Total nsec BCs Total
TOF from IP to NSW (z=7.9 m) 26 1.05 1.05 TOF from IP to TGC 50 2 2Pad signal jitter in chamber 5 0.2 1.25 Propagation delay on wire/strip 5 0.2 2.2Pad VMM 1.5 2.75 TGC response 2 0.1 2.3Pad TDS, Pad trigger, Strip TDS 8.84 11.48 ASD 5 0.2 2.5Signal Processing on detector 7.6 19.05 Cable to PS-Board 2.5 5Optical Fibre to USA15 racks 11.88 30.9 Variable Delay. Bunch ID. OR 1.5 6.5Signal processing at USA15 3.75 34.65 Variable Delay 1 7.5
3/4 or 2/3 Coincidence Matrix 1 8.5sTGC trigger algorithm 2.25 36.9 LVDS Tx (SN65LV1023) 1 9.5
Cable to HPT board (15m max.) 3 12.5LVDS Rx (SN65LV1224A) 2 14.5
Merge sTGC and MicroMegas 2 38.9 Variable Delay 1 15.5HPT Matrix 2 17.5
Serializer + Optical Tx 1.2 40.1 G-Link Tx (HDMP-1032A) + Optical Tx 1.5 19Optical Fibre to Sector Logic (5 m) 1 41.1 Optical Fibre to Sector Logic (90 m) 18 37
New Sector LogicReceive signal from NSW 41.1 Receive signals from BW 37Optical Rx + De-serializer 2.5 44 Optical Rx + De-serializer 2 39Variable Delay 1 45 TGC R-Phi coincidence (LUT) 2 41Decoding/Alignment of NSW data (LUT) 1 46 Waiting for NSW signals 5 46
BW - NSW coincidence (LUT) 2 48Track selection + pT encoding 1 49Serializer (128 bit/clk., 6.4 Gb/s) + Optical Tx 2 51Optical fibre to MUCTPI (10 m) 2 53
Table 19: Latency contributions of Level-1 Endcap Muon trigger in units of BC. The NSWlatency is obtained from [11, 12].
1153
We also measured the trigger latency of the Sector Logic firmware between time when datais received, processed, and output to MUCTPI by GTX, as shown in Table 20.1154
96 11 Latency
Latency to process NSW signals
New Sector Logic will receive NSW signals 41.1 BCs after bunch crossing Deserializing and decoding will take ~ 4.5 BCs after receiving signals NSW coincidence will start at 46 BCs after bunch crossing
Coincidence between TGC BW and NSW must be finished in 2 BCs (50 ns)
22nd IEEE Real Time Conference Yuya Mino
Level-0 endcap muon trigger system
27
8.3.2 Improvement of the Trigger Performance
Figure 8.4: A simplified block diagram of the proposed Level-0 Muon Trigger System for HL-LHC.The top and bottom parts show the diagrams for the barrel and the endcap, respectively.
(see Section 8.5) is proposed to improve the robustness and redundancy of the trigger byperforming a combined track segment reconstruction by sTGC and MM.
8.3.2 Improvement of the Trigger Performance
Improvements in trigger performance will be achieved by increasing the detector accept-ance, the trigger logic, and the momentum resolution. The upgrade of the muon systemtowards Phase-II includes the addition of RPCs in the barrel inner station as described inRef. [8.1]. By allowing for coincidences of hits in the RPCs in the inner and outer stations,the acceptance gaps in the barrel trigger system which are caused by the non-instrumentedregions in the barrel middle station due to the presence of the structures of the barrel toroidcoils will be closed. The expected value of the product of the acceptance and the efficiencyof the muon trigger in the barrel region is more than 90% depending on the coincidencecriteria. The Barrel Sector Logic in the new design includes the coincidence of the addi-
181
① Sector Logic (SL) receives hit and track information from TGC, NSW, RPC and Tile, and provides track candidates to MDT trigger processor.
② MDT trigger processor recalculates the track candidate pT with better momentum resolution using MDT hits, and sends them back to SL.
③ SL sends the final candidates to MUCTPI.
① ① ① ① ①②
③
22nd IEEE Real Time Conference Yuya Mino
Block diagram of SL firmware in HL-LHC
28
Not reviewed, for internal circulation only
DRAFT
Prelim
inaryD
esignforE
ndcapS
ectorLogicJuly
10,2020-Version
1.0
GTY RX
interfaceDelay Mask
Formatting
(TGC)
Formatting
(RPC,Tile,
NSW)
TGC front-end board
RPC board
Tile board
NSW Trigger Processor
Wire segment
reconstruction
Strip segment
reconstruction
Wire/strip
coincidence
Inner
coincidence
Track
selector
GTY TX
Interface
MDT Trigger
Processor
Trigger Logic
Readout Logic
TGC data readout
Trigger data readout
FELIX
InterfaceFELIX
MDT Trigger
Processor
GTY RX
InterfaceDelay Buffer MUCTPI
GTY TX
Interface
Zynq MPSoC Zynq MPSoC
TTC counter
FELIXGTY RX
Interface
PLLRecovery clock
Clock managerJitter cleaner
TGC front-end board
Jitter cleaner40 MHz clock
Forward / Endcap1 / Endcap2
TGC EI
L0A
Monitor
GTY TX
Interface
Mask
Controller
TTC
Figure 4.2: A schematic diagram of the Endcap SL firmware. Clock assigns are not shown in this figure.
4.Firmw
arePage
19of
??
22nd IEEE Real Time Conference Yuya Mino
Estimated FPGA resource utilization in HL-LHC
29
BRAM (Mb) URAM (Mb) HP I/O GTY
Availability 75.9 270.0 448 120
Trigger Logic 20.5 123 - -
Readout Logic 23.8 - - -
Interface - - - 90 - 92
Control/monitor - - O(10) -
Total 44.3 120 O(10) 90 - 92
Estimation based on extrapolation from resource utilization of partially developed firmware. Largest contribution to the URAM utilization is the TGC wire track reconstruction.
22nd IEEE Real Time Conference Yuya Mino
Estimated latency requirement in HL-LHC
30
The TGC track reconstruction is required to be finished in 0.125 μs
Contents Latency
TGC hit signal arrival 0.888 μs
Coincidence of TGC BW 1.013 μs
TGC BW and TGC EI coincidence 1.063 μs
TGC BW and RPC BIS78 coincidence 1.360 μs
NSW track candidate and TileCal signal arrival 1.425 μs
TGC BW and NSW (TileCal) coincidence 1.450 μs
Final selection of track candidate 1.475 μs
Estimated latency contributions of Sector Logic in HL-LHC
0.125 μs… …
22nd IEEE Real Time Conference Yuya Mino
Hardware design of Sector Logic in HL-LHC
Xilinx Virtex UltraScale+ is implemented on a ATCA* blade.
31
Not
revi
ewed
,for
inte
rnal
circ
ulat
ion
only
DRAFT
Preliminary Design for Endcap Sector Logic July 10, 2020 - Version 1.0
3 Hardware270
3.1 Overview271
The Endcap SL will be introduced in L0Muon as a part of the ATLAS upgrade for HL-LHC. It receives hits from272
the TGC PS boards, track segments from NSWTP, coincidence outputs of BIS78 RPC from Barrel SL, and273
energy flag for Tile coincidence, indicating whether or not the signal pulse is greater than the threshold [2,274
4]. The Endcap SL sends TCs with pT
thresholds satisfied and NSW track segments to the MDTTP. The275
Endcap SL receives the TCs from the MDTTP, where pT
evaluated with the MDT hits is included if the276
evaluation is possible. The Endcap SL sends mTCs to MUCTPI. In addition, the Endcap SL is responsible277
for the transmission of the TGC hits and the trigger information, including NSW, BIS78 RPC, and Tile data,278
downstream to FELIX for readout. The Endcap SL receives the TTC signals from FELIX. The Endcap SL is279
responsible also for the transmission of the configuration signals to the TGC PS boards.280
The Endcap SL system consists of 48 ATCA blades. An ATCA blade shall process the data for one 24th281
of the coverage in � for one of the positive and the negative sides of ⌘.282
Figure 3.1 shows a simplified block diagram of Endcap SL. Figure 3.2 shows also a block diagram but the283
elements are shown one by one. CERN-developed IPMC shall be used for basic blade control and configura-284
tion at power up through the ATCA shelf manager. The Endcap SL interfaces with the TDAQ servers [6] and285
DCS [8] via MPSoC mezzanine for control and monitoring.286
TGC6FireFlyforreceivers4FireFlyfortransmitters
12
12
12
12
12
12
12
12
12
12
12
12
12
VirtexUltraScale+
-SectorLogic-ReadoutLogic-Control-Monitoring
AXIC2C ZynqUltraScale+MPSoC
MUCTPI1QSFP+
FELIX1QSFP+
TDAQServers/DCSEthernet
4
4
4
4
MDT1FireFlyforreceivers1FireFlyfortransmitters
NSW,RPC(BIS78),andTile1FireFlyforreceivers
IPMC ShelfManagerIPMI
Figure 3.1: A simplified block diagram of the Endcap SL.
3.2 FPGA287
The FPGA selected in the preliminary design is Xilinx Virtex UltraScale+ FPGA (XCVU9P-1FLGA2577E).288
This type of FPGA has the following features.289
• System logic cells: 2,586k290
• DSP slices: 6840291
• Memory (Block RAM): 75.9 Mb292
3. Hardware Page 9 of ??
*Advanced Telecommunication Computing Architecture ** Intelligent Platform Management Controller *** Multiprocessor System-on-chip
MPSoC*** mezzanine card : Interface for the ATLAS Run Control, Configuration and Monitoring
Firefly module : Handle 12 channels up to 16 Gbps per channel
QSFP+ module : Handle 4 channels up to 10 Gbps per channel
IPMC** module : Control and configuration at power up through the ATCA shelf manager
22nd IEEE Real Time Conference Yuya Mino
Initial test of track segmentationA test firmware of TGC pattern matching algorithm is implemented in an FPGA to estimate performance.
32
Not
revi
ewed
,for
inte
rnal
circ
ulat
ion
only
Figure 3: Distribution of the polar angle difference Δθ between a track segment reconstructed by a pattern matching algorithm with Thin Gap Chamber (TGC) hits assumed to be used in the Level-0 muon trigger at HL-LHC and a track segment reconstructed by an offline algorithm based on Monitored Drift Tube (MDT) hits. Precise measurement of the track segment angle is profited to determine muon transverse momentum and obtain sharper efficiency turn-on curves. The TGC pattern matching algorithm is implemented in a Virtex UltraScale+ FPGA XCVU9P on an evaluation kit. Test vectors of TGC hits are obtained from Monte-Carlo (MC) sample and used as the FPGA inputs. The FPGA outputs are compared with the offline track segments based on MDT hits. The offline track segment is considered to be a reference, thus the width of Δθ distribution is regarded as resolution of the TGC pattern matching algorithm for muon tracks used in this study. The MC sample includes a muon in each event, and the events are selected by requiring exactly seven TGC hits on the seven layers, i.e. neither missing hits nor cross talks, in a pseudorapidity range 2.13 < η < 2.16. Memory usage of the algorithm in this study corresponds to about one third of the total memory resource of XCVU9P when a full η range of the endcap is included.
[mrad]θΔ-30 -20 -10 0 10 20 30
Entri
es /
2 m
rad
0
50
100
150
200
250
300
350ATLAS Simulation Preliminary
Single muon MC < 2.16µη2.13 <
One hit on each layer
Mean: -0.1 ± 0.1 mradRMS: 2.4 ± 0.1 mrad
Test result with the evaluation kit VCU118. It shows high efficiency and better angular resolution.
Expected memory usage for the full η range is about 100 Mbit, which is one-third of 345.9 Mbit of RAM resources on XCVU9P.
ATLAS L0Muon Trigger Public Results
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