Advanced Digital CircuitsECET 146
Week 2
Professor Iskandar Hack
ET 221B, 481-5733
Week’s Goals
Downloading and Installing Altera’s Quatrus Software Introduction of Altera’s Quatrus II Software including :
Entering Design into Design Software using Schematic Editor
Compiling design to implement into an Altera CPLD Reviewing Report File to Determine:
Chip Utilization Pin outs
Simulating Design
Can you download Altera??
The file is approximately 1.4 Gbyte and if you don’t have a broadband connection don’t attempt to download the file at home.
Your options are (if you want to have the software installed at home or on a laptop) to bring in a blank CD to the lab tech office and request a copy or to use a large (2G or larger) flash drive and download it in the lab.
Downloading Altera’s Max+ Plus II
Go to Altera’s University Download page at https://www.altera.com/support/software/download/altera_design/quartus_we/dnl-quartus_we.jsp
Select Quartusii_50_sp_web_edition_single.exe
Downloading Altera Quartus II
Fill in the questionnaire and submit request
Downloading Altera III
Select Save File when download dialog appears
Downloading Altera III
Select a directory that you will remember to save the file to (Firefox likes to save things to the desktop)
Installing Altera
Open the directory you saved the install file to in Windows Explorer and double click the install file
Installing Altera II
Accept all of the defaults when installing the software.
Installing Altera III
Enter your name and either ‘home’ or Purdue for when asked
Installing Altera IV
Select Complete install
Installing Altera V
Typical install screen
Installing Altera VI
Turn off Talk Back when prompted
Entering Schematic Design
Open the Altera Quatrus II Software and select new and then Block Diagram/Schematic file
Entering Symbols
Draw the schematic by double clicking and selecting the symbols to enter appropriate symbols (note: if you are entering more than one of the same symbol, you can turn on Repeat insert mode)
input (name of symbol
Repeat mode
Entering Wires
Draw wires by moving the cursor over the inputs or outputs of gates (or I/O pads) until a crosshair appears (along with the upside down L) and draw with the left mouse button.
Exercise One
Draw the following schematic
Renaming Pins
Double Click on I/O pins show that they are highlighted and type in new name (the software should automatically highlight the next input pin)
Finish Drawing for Exercise One
Rename all the pins as shown
Save Design
Go to File and select save as and save design as Example1.bdf (note gdf = block design file) on your flash or zip drive if in lab, or in your working directory otherwise. Note, check box – create new project based on this file
Creating the Project I
Say yes to the following dialog box
Creating the Project II
This page is just for information – hit next
Creating the Project III
Take the default on the next dialog box note the name of the project is the same as what you named the file. At this point (for this example) we are done – we can hit Finish
Verify the Project is correct
After setting the project be sure that that the project name matches the file name.
Project NameCurrent File being edited
Notes regarding Project Names
The project name does NOT contain the .bdf extension
Thus if there are more than one type of design file in the project such as wdf (waveform design files) or tdf (text design files) then the system will not know what file goes with the project name.
Therefore you can NOT have a file named Example1.bdf and Example1.tdf in the same directory. This will cause MAJOR problems for the software.
Later in the semester you’ll have projects with more than one file – BEWARE of the names of the files, they must be unique.
Compiling the Project
Hit the hot key on the top of the screen to start compiling your project.
The Compiler
If you did everything right thus far you should see something like this:
Compiler Reports
The compiler creates a number of reports, which at this point would mean nothing to you, but you may want to explore them.
I/O pin info Boolean EQ
Drawing Waveforms for Simulation
We now need to create a new file to hold our simulation input waveforms. This done by hitting new and selecting Other and vector waveform file (vwf)
Entering Nodes
You will need to double click in the node area of the display – this will bring up the following dialog box
Select Node Finder
Entering Nodes II
(1) Start by selecting Pins: all
(2) Then hit List
(3) Move all pins to the rightby hitting >>
(4) Hit OK
Check if all nodes are selected
Verify in the waveform editor that all nodes are shown
Inputs
Output
Change Grid and End Time
Select Edit, Grid time, and change it to 50 nS
Select Edit, End time and change it to 1.6 uS
Grouping Inputs
Select all the inputs, right click, hit ‘Group’ and use inputs[3..0] for the name of the inputs, Hex as radix, and uncheck grey count
Display after Grouping
+ will expand group to show the individual pins- will hide individual pins
Using Count Function
Select the Group, and then hit the count button on the left side of the screen. Take the defaults (start at 0, incr by 1, End value F)
Display after Count
You should see the following after hitting OK
Save Simulation File
Up to now you should have seen that the output is neither high or low. That is because it has not been simulated yet.
In order to simulate you must first save the file as example1.vwf
Leave checked
Simulate
This is the easy part – Hit the simulate button on the top of the screen.
Simulate
Verify Simulation
You should have a value for the output for each input condition.
Manually determine (using techniques from ECET 111) what the output should be for each condition and verify that the output matches that.
Simulation Display
Assignment One Using techniques from ECET 111 design a
circuit (no need to minimize) for the following Boolean expression.
Manually draw up truth table for the equation
Enter the design into the Altera Software and simulate the design
You’ll need to use the following symbols: NOT AND2 OR2 INPUT OUTPUT
Compare the truth table to the simulation Turn in hand drawn schematic, truth table,
print out of the schematic from Altera, and a copy of the simulation.
DCBAX
Top Related