A Requirements-Driven PLD Design Flow MAPLD 2009
Dominic LucidoSr. Applications Engr
•Nucleus Secure Kernel
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Mentor Offers
Complete Electrical Systems Design Automation
•Boardstation•Expedition•Data Management
•Capital Harness System •HDL Designer•Precision synthesis•ModelSim simulator•FormalPro
•Questa adv verification •TestKompress DFT•Calibre phys verification
•SystemVision
PCB DesignPCB Design
FPGA/ASIC DesignFPGA/ASIC Design
EWIS DesignEWIS Design
Electro-Mechanical Electro-Mechanical System SimulationSystem Simulation
Embedded SWEmbedded SW
... is needed by many Safety Critical & Mission Critical Industries:
— Commercial Aviation— Military— Space— Medical Electronics— Automotive— Railway— Robotics— Industrial Controls— Banking Systems— Cruise Ships— Shipping
Requirements Driven Development Process
DO-254 in the Aircraft Certification Process
Timeline ~2 years
FPGA/ASIC•Built to DO-254 standards as reviewed by DER
Review: Principles of DO-254 DO-254 Lifecycle DO-254 Key Concepts
— Detailed planning captured in PHAC
— Requirements driven flow Requirements tracing
— Thorough verification— Flow under strict CM— Audits against PHAC
Internal QA reviews External SOI audits
— Proof of compliance shown through artifacts
5
RequirementsCapture
RequirementsCapture
ConceptualDesign
ConceptualDesign
DetailedDesignDetailedDesign
ImplementationImplementation
ProductionTransitionProductionTransition
DO-254 LifecyclePlanningPlanning PHA
C
PHAC
DO-254 Principles Move to Higher Levels
6
End-Product(System)
RequirementsCustomer
Requirements Management & Tracing
Chip Design & Analysis
Board Design & Analysis
SystemDesign & Analysis
DO-254
DO-254
Managing the Design and Virtual Prototyping Process
Enterprise Requirements
Database
Design IP Verification IP
IP
System Integration/Test
ComponentTest
ArchitectureValidation/Test
FunctionalVerification
RequirementsVerification
RequirementsDefinition
FunctionalDesign
ArchitectureDesign
SystemDesign
ComponentDesign
Advanced Advanced RequirementsRequirements
Tracing Tracing EngineEngine
Overall Objective
Produce a traceable “Verified Implementation” — Requirements Coverage
Demonstrate that all the requirements have been implemented.
— Functional Coverage Demonstrate that the required design functionality has
been fully tested
— Change Tracking and Control Track requirements changes and manage their
impact throughout the development process.
Tracing Requirements into FPGA/ASIC Design
RTL Code— Associate HDL design constructs with design
requirements Verification Plan
— Associate verification requirements with design requirements
Testbench Code— Associate HDL testbench constructs and
coverage items with verification requirements Verification Results
— Associate verification results, such as text logs and coverage databases, with verification requirements.
VH
DL
VH
DL
Verilo
gV
erilog
VH
DL
VH
DL
Verilo
gV
erilog
Log Files
Log Files
The Challenge: Tracing Requirements down into the
Implementation and Verification Details
Wide variety of data to track: System Level Requirements
(DOORs) Subsystem Specification (Word) Design Source (VHDL) Test Plan (Excel) Testbench (SystemVerilog) Simulation Verification Results
(UCDB & text logs) Hardware Test Results
(Instrument &ATE logs)
Tracing Requirements into FPGA/ASIC Design
Tracing Requirements into PCB Design
Schematic— Associate a schematic block with a requirement
Constraints— Associate constraints on a net with a requirement
Layout— Associate an area of a layout with a requirement
Verification Results— Associate results from PCB verfication tools such
as signal integrity, manufacturability and thermal analysis with a requirement
Log Files
Log Files
Tracing Requirements into PCB Design
Tracing Requirements into ESL Design
Functional Model— Associate requirements with a system level
functional model Architectural Model / Virtual Prototype
— Associate requirements with an architectural level model
TLM Model— Associate requirements with a TLM model
Model Verification Results— Associate requirements with results from all
levels of model simulationsLog Files
Log Files
C / C
++
/ SysC
C / C
++
/ SysC
UM
L / C
/ C+
+U
ML
/ C / C
++
TL
M / S
ysCT
LM
/ SysC
Tracing Requirements into ESL Design
Tracing Requirements into EWIS Design
Design— Associate requirements with EWIS design
elements Constraints
— Associate requirements with EWIS constraint definitions
FMEA Results— Associate requirements with results of Failure
Modes and Effects analysis EWIS Verification Results
— Associate requirements with simulation results for DC, transient sneak path and switch state analysis
Log Files
Log Files
CHS
Tracing Requirements into EWIS Design
ESL FlowESL FlowESL FlowESL Flow
EWIS FlowEWIS FlowEWIS FlowEWIS Flow
18FPGA Assurance Workshop, Feb 2009
Requirements Driven Development Process
Customer Level
System Level
Subsystem Level
Module/LRU Level
ASIC/FPGA Level
PCB FlowPCB FlowPCB FlowPCB Flow
ASIC/FPGA ASIC/FPGA FlowFlow
ASIC/FPGA ASIC/FPGA FlowFlow
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Requirements Volatility
Definition— A measure of the number of new, deleted and
changed requirements relative to the total number of requirements
Impact— System Quality— Development Schedules
Measurement— Can be Difficult (An automated tool really helps!)— Powerful project management tool
2020
C / C
++
C / C
++
Design and Testbench Source Files & PCB Design Data
ASCII Test Results
Enterprise Level Requirements Databases
Requirements Documents&Text Files
Requirements Tracing with ReqTracer
Change Impact and Traceability Analysis
Automated Traceability Report
Generation
Requirements-aware Access to Test Result Data
ReqTracerReqTracerReqTracerReqTracer
VH
DL
VH
DL
Verilo
gV
erilog
Text Log Files
Text Log Files
Matlab™Matlab™Matlab™Matlab™
Simulation Results
Tag
Configure ReqTracer to capture existing requirements
Tag new requirements
DesignDesignSpecificationSpecification
REQ_001REQ_001
REQ_002REQ_002
REQ_004REQ_004
REQ_003REQ_003
REQ_005REQ_005
TAGTAG
TAGTAG
TAGTAG
TAGTAG
TAGTAG
DesignDesignSpecificationSpecification
RTLRTLDesignDesign
IMPLEMENTSIMPLEMENTSIMPLEMENTSIMPLEMENTS
Trace
HardwareHardwareRequirementsRequirements
COVERSCOVERSCOVERSCOVERS
COVERS
COVERS
COVERS
COVERS
COVERSCOVERSCOVERSCOVERSIMPLEMENTSIMPLEMENTSIMPLEMENTSIMPLEMENTS
IMPLEMENTS
IMPLEMENTS
IMPLEMENTS
IMPLEMENTS
IMPLEMENTS
IMPLEMENTS
IMPLEMENTS
IMPLEMENTS
40%40% 60%60%
Hardware DesignersHardware Designers
What shall I work on next?
What shall I work on next?
Certification Authority
Certification Authority
Can you prove all requirements are implemented and
tested?
Can you prove all requirements are implemented and
tested?
System ArchitectSystem
Architect
What is this code for?
What is this code for?
Can we make a change and still release on
time?
Can we make a change and still release on
time?
Project ManagerProject
Manager
DesignDesignSpecificationSpecification
RTLRTLDesignDesign
IMPLEMENTSIMPLEMENTSIMPLEMENTSIMPLEMENTS
Monitor/Analyze
HardwareHardwareRequirementsRequirements
COVERSCOVERSCOVERSCOVERS
COVERS
COVERS
COVERS
COVERS
COVERSCOVERSCOVERSCOVERSIMPLEMENTSIMPLEMENTSIMPLEMENTSIMPLEMENTS
IMPLEMENTS
IMPLEMENTS
IMPLEMENTS
IMPLEMENTS
IMPLEMENTS
IMPLEMENTS
IMPLEMENTS
IMPLEMENTS
CHANGECHANGE IMPACTIMPACT
IMPACTIMPACT
IMPACTIMPACT
IMPACTIMPACT
20% 40% 60%60%
System ArchitectSystem
Architect
How risky would it be if I changed
this?
How risky would it be if I changed
this?
Quality ManagerQuality
Manager
Which tests need updating now the
design has changed?
Which tests need updating now the
design has changed?
IMPACTIMPACT
Basic vs. Advanced Requirements Tracing
Basic— DOORS Support— Word/Excel Support— Design Artifact Import — External Filename Ref— Traceability Report— CM Mechanism
Advanced— DOORS Interface— Word/Excel Interface— Text File Interface— Design Data Interfaces— Data Environment Link— Design Tool Interfaces— Requirements Aware Change
Tracking— Traceability Report— Report Library— Programmable Report Generator— IP-Safe Interactive Tracing
Report
Advanced Requirements Tracing
Advanced— DOORS Interface— Word/Excel Interface— Test File Interface— Design Data Interfaces— Data Environment Link— Design Tool Interfaces— Requirements Aware
Change Tracking— Traceability Report— Report Library— Programmable Report
Generator— IP-Safe Interactive Tracing
Report
Traceability Across Design Domains
Enterprise Requirements
Database
Electrical Design Mechanical Design Software Design
IP
EE ME SW
Advanced Requirements
Tracing Engine
WCR, IESF Seattle, May 2009
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Enterprise Requirements
Database
Advanced Requirements
Tracing Engine
Traceability across the Supply Chain
In-House
Supplier B
Supplier A
EE ME
SW
EE ME SW
EE ME SW
IP
WCR, IESF Seattle, May 2009
27
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ReqTracer™
Managing Requirements throughout your Design Flows
Analysis & Analysis & Reporting Reporting
Change Change ManagementManagement
Impact Analysis to Control Schedules
RequirementsRequirementsCapture Capture && Tracing Tracing
XMLASCII
Link Automated Reports, Specs,
Design & Results
Trace Through Deign Implementation &
Testing
Presenter Initials, IESF Seattle, May 2009
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