7/28/2019 1 Digital L2 Intro
1/61
VLSI Design MethodologyVLSI Design Methodology
7/28/2019 1 Digital L2 Intro
2/61
OutlinesOutlines
VLSI Design Flow and Structural DesignVLSI Design Flow and Structural Design
PrinciplesPrinciples
VLSI Design Styles
VLSI Desi n Strate ies
Nitin ChaturvediNitin Chaturvedi VLSI Design Methodology 2
Computer-Aided Design Technology for VLSI
7/28/2019 1 Digital L2 Intro
3/61
Design DomainsDesign Domains
Nitin ChaturvediNitin Chaturvedi VLSI Design Methodology 3
7/28/2019 1 Digital L2 Intro
4/61
Simplified VLSI Design FlowsSimplified VLSI Design Flows
System Specification
Functional(Architecture) Design
Functional Verification
Circuit Design
Circuit Verification
BehavioralBehavioralRepresentationRepresentation
CircuitCircuitRepresentationRepresentation
Nitin ChaturvediNitin Chaturvedi VLSI Design Methodology 4
Logic Design
Logic Verification
Physical Design
Physical Verification
Front EndFront End Back EndBack EndSynthesis PhaseSynthesis Phase Layout PhaseLayout Phase
LogicLogic(Gate(Gate--Level)Level)
RepresentationRepresentation
LayoutLayoutRepresentationRepresentation
7/28/2019 1 Digital L2 Intro
5/61
Design Abstraction levelDesign Abstraction level
Nitin ChaturvediNitin Chaturvedi VLSI Design Methodology 5
7/28/2019 1 Digital L2 Intro
6/61
Four Levels of Design RepresentationFour Levels of Design Representation
BehavioralBehavioralRepresentationRepresentation
Logic (GateLogic (Gate--Level)Level)Re resentationRe resentation
Functional Blocks, FSMFunctional Blocks, FSM
Logic Blocks, GatesLogic Blocks, Gates
Nitin ChaturvediNitin Chaturvedi VLSI Design Methodology 6
CircuitCircuit(Transistor(Transistor--Level)Level)RepresentationRepresentation
LayoutLayoutRepresentationRepresentation
Transistor SchematicsTransistor Schematics
Physical DevicesPhysical Devices
7/28/2019 1 Digital L2 Intro
7/61
Structure Design PrinciplesStructure Design Principles
HierarchyHierarchy:
Divide and conquerDivide and conquer technique involves dividing a module
into sub-modules and then repeating this operation on the sub-modules until the complexity of the smaller parts becomes
manageable.
Nitin ChaturvediNitin Chaturvedi VLSI Design Methodology 7
uu:
The hierarchical decomposition of a large system should result
in not onlysimplesimple, but alsosimilarsimilar blocks, as much as
possible.
Regularity usually reduces the number of different modules
that need to be designed and verified, at all levels of
abstraction.
7/28/2019 1 Digital L2 Intro
8/61
Example of RegularityExample of Regularity
Nitin ChaturvediNitin Chaturvedi VLSI Design Methodology 8
These circuits are built using inverters and triThese circuits are built using inverters and tri--state buffers only.state buffers only.
7/28/2019 1 Digital L2 Intro
9/61
Structured Design Principles (Cont.)Structured Design Principles (Cont.)
ModularityModularity:
The various functional blocks which make up the larger
system must have wellwell--defined functionsdefined functions and interfacesinterfaces.. Modularity allows each block to be designed independently;
All blocks can be combined with ease at the end of the
Nitin ChaturvediNitin Chaturvedi VLSI Design Methodology 9
.
LocalityLocality:
Internal details remain at the local level.
The concept of locality also ensures that connections aremostly between neighboring modules,avoiding longavoiding long--distancedistance
connectionsconnections as much as possible.
7/28/2019 1 Digital L2 Intro
10/61
7/28/2019 1 Digital L2 Intro
11/61
Example (Cont.): LevelExample (Cont.): Level 11
1616--bit Adderbit Adder
Complete LayoutComplete Layout
Nitin ChaturvediNitin Chaturvedi VLSI Design Methodology 11
44--bit Adder with Manchester carrybit Adder with Manchester carry
7/28/2019 1 Digital L2 Intro
12/61
Example (Cont.): LevelExample (Cont.): Level 22
Carry/propagate circuitCarry/propagate circuit Output buffer/latchOutput buffer/latch
Nitin ChaturvediNitin Chaturvedi VLSI Design Methodology 12
44--bit Adder with Manchester Carry Layoutbit Adder with Manchester Carry Layout
Manchester Carry circuitManchester Carry circuit
7/28/2019 1 Digital L2 Intro
13/61
Example (Cont.): LevelExample (Cont.): Level 33
Carry/propagateCarry/propagate
circuit layoutcircuit layout
Nitin ChaturvediNitin Chaturvedi VLSI Design Methodology 13
Manchester carryManchester carry
circuit layoutcircuit layout
Output buffer/latchOutput buffer/latch
circuit layoutcircuit layout
7/28/2019 1 Digital L2 Intro
14/61
OutlinesOutlines
VLSI Design Flow and Structural Design
Principles
VLSI Design StylesVLSI Design Styles
VLSI Desi n Strate ies
Nitin ChaturvediNitin Chaturvedi VLSI Design Methodology 14
Computer-Aided Design Technology for VLSI
7/28/2019 1 Digital L2 Intro
15/61
VLSI Design StylesVLSI Design Styles
Nitin ChaturvediNitin Chaturvedi VLSI Design Methodology 15
7/28/2019 1 Digital L2 Intro
16/61
Nitin ChaturvediNitin Chaturvedi VLSI Design Methodology 16
7/28/2019 1 Digital L2 Intro
17/61
FullFull--Custom DesignCustom Design
Full-custom blocks are carefully crafted in thephysical level to obtain the highest possible
performance.
Nitin ChaturvediNitin Chaturvedi VLSI Design Methodology 17
7/28/2019 1 Digital L2 Intro
18/61
FullFull--Custom Design Key IssuesCustom Design Key Issues
The key to Full-custom design is to exploit thefine-grained regularity and modularity in the
physical level. Manual full-custom design can be very
challen in and time consumin , es eciall if
Nitin ChaturvediNitin Chaturvedi VLSI Design Methodology 18
the low level regularity is not well defined. Development cost are too high!
Design reuse is becoming popular to reduce design
cycle time and development cost.IP blocksIP blocks
Full-custom design is used only in the criticalblocks.
7/28/2019 1 Digital L2 Intro
19/61
FullFull--Custom DRAM ExampleCustom DRAM Example
Nitin ChaturvediNitin Chaturvedi VLSI Design Methodology 19
7/28/2019 1 Digital L2 Intro
20/61
CellCell--Based DesignBased Design
Lego Style Design
All of the commonly used logic cells are
developed, characterized, and stored in astandard cell library.
Nitin ChaturvediNitin Chaturvedi VLSI Design Methodology 20
such as inverters, NAND, NOR, each in severalversions to provide a range of performance.
The inverter gate can have standard size, double size, andquadruple size.
Most popular because of CAD tools availabilityand capability.
7/28/2019 1 Digital L2 Intro
21/61
CellCell--Based Design Key IssuesBased Design Key Issues
Inclusion/Exclusion of a gate variation dependson the objectives of the library.
Standard Library, Low Power Library, etc.
Most challenging task is to how to place the
Nitin ChaturvediNitin Chaturvedi VLSI Design Methodology 21
in a way that meet stringent design goals.
Most advanced CAD tools have place-and-route tools.
In a complex, demanding design, standard-cellbased design approach may be used as a firstpass, then full-custom design where necessary.
7/28/2019 1 Digital L2 Intro
22/61
Example of Standard CellsExample of Standard Cells
Power RailPower Rail
Nitin ChaturvediNitin Chaturvedi VLSI Design Methodology 22
Each cell layout is designed with a fixed height so that a numberEach cell layout is designed with a fixed height so that a numberof cells can be snapped together sideof cells can be snapped together side--byby--side to form rows.side to form rows.
Ground RailGround Rail
7/28/2019 1 Digital L2 Intro
23/61
Example of Stand Cells (Cont.)Example of Stand Cells (Cont.)
Standard CellStandard Cell
Nitin ChaturvediNitin Chaturvedi VLSI Design Methodology 23
Routing ChannelRouting Channel
7/28/2019 1 Digital L2 Intro
24/61
CellCell--Based Design ExampleBased Design Example
Nitin ChaturvediNitin Chaturvedi VLSI Design Methodology 24
7/28/2019 1 Digital L2 Intro
25/61
Nitin ChaturvediNitin Chaturvedi VLSI Design Methodology 25
7/28/2019 1 Digital L2 Intro
26/61
Masked Gate Array (MGA) DesignMasked Gate Array (MGA) Design
Only transistorsOnly transistors
No contacts and metal layersNo contacts and metal layers
Nitin ChaturvediNitin Chaturvedi VLSI Design Methodology 26
One pattern mask forOne pattern mask for
Mass productionMass production
7/28/2019 1 Digital L2 Intro
27/61
MGA Design Key IssuesMGA Design Key Issues
Uncommitted (Unused) transistors or gates are
wasted.
Performance measured as Chip Utilization Factor ~used chip area/total chip area.
Nitin ChaturvediNitin Chaturvedi VLSI Design Methodology 27
ncomm tte ce s can e sacr ces to mproveintercell routing capability
Modern GAs use multiple metal layers for
channel routing
Smaller area, higher density, and routability
7/28/2019 1 Digital L2 Intro
28/61
Example of MGA DesignExample of MGA Design
Nitin ChaturvediNitin Chaturvedi VLSI Design Methodology 28
7/28/2019 1 Digital L2 Intro
29/61
FPGA DesignFPGA Design
An FPGA chip provides thousands of logicgates, organized into logic blocks, with
programmable interconnects. To implement a custom hardware, a user can use
hi h-level hardware ro rammin e. ., HDL .
Nitin ChaturvediNitin Chaturvedi VLSI Design Methodology 29
Program logic table for each logic block.
Program interconnect switch matrices
Program I/O blocks
Programs last as long as the chip is powered-on
7/28/2019 1 Digital L2 Intro
30/61
Field Programmable Gate Array (FPGA)Field Programmable Gate Array (FPGA)
Nitin ChaturvediNitin Chaturvedi VLSI Design Methodology 30
Architecture of Xilinx FPGAsArchitecture of Xilinx FPGAs
7/28/2019 1 Digital L2 Intro
31/61
FPGA (Cont.)FPGA (Cont.)
Nitin ChaturvediNitin Chaturvedi VLSI Design Methodology 31
Simplified block diagram of a CLB by XilinxSimplified block diagram of a CLB by Xilinx
7/28/2019 1 Digital L2 Intro
32/61
XCXC40004000E Configurable Logic BlocksE Configurable Logic Blocks
D Q
SD
EC
S/R
Control
F'
G'
H'
DIN
GFunc.Gen.
G4G3G2G1
C4C1 C2 C3
YQ
H1 DIN S/R EC
2 Four-input function
generators (Look Up
Tables)- 16x1 RAM or
Logic function
RD
D Q
SD
RD
EC
S/R
Control
1
1
F'
G'
H'
DIN
F'
G'H'
H'
HFunc.Gen.
FFunc.Gen.
F4F3F2F1
K
Y
XQ
X
2 Registers- Each can be
configured as Flip
Flop or Latch
- Independent
clock polarity- Synchronous and
asynchronous
Set/Reset
7/28/2019 1 Digital L2 Intro
33/61
Look Up TablesLook Up Tables
Combinatorial Logic is stored in 16x1 SRAM Look Up Tables
(LUTs) in a CLB
Example:
A B C D Z
0 0 0 0 0
Look Up Table
Combinatorial Logic
AB
4-bit address
Nitin ChaturvediNitin Chaturvedi VLSI Design Methodology 33
Capacity is limited by number ofinputs, not complexity
Choose to use each function
generator as 4 input logic (LUT) or as
high speed sync.dual port RAM
0 0 0 1 0
0 0 1 0 0
0 0 1 1 1
0 1 0 0 1
0 1 0 1 1
. . .1 1 0 0 0
1 1 0 1 0
1 1 1 0 0
1 1 1 1 1
CD
Z
GFunc.Gen.
G4G3G2G1
WE
7/28/2019 1 Digital L2 Intro
34/61
FPGA (Cont.)FPGA (Cont.)
Nitin ChaturvediNitin Chaturvedi VLSI Design Methodology 34
Switch matrices and interconnection routing between CLBSwitch matrices and interconnection routing between CLB
7/28/2019 1 Digital L2 Intro
35/61
FPGA Design Key IssuesFPGA Design Key Issues
Chip utilization of an FPGA depends on
GranularityGranularity of the logic block - Size of logic block
Routing capabilityRouting capability - Size of switch matrices
The largest advantage of FPGA-based design is
Nitin ChaturvediNitin Chaturvedi VLSI Design Methodology 35
The time required from the start of the design
process until a functional chip is available
Typical price of FPGA chips is usually higher
than other alternatives of the same design, butfor small-volume production and for fastprototyping
7/28/2019 1 Digital L2 Intro
36/61
HDLHDL--Based DesignBased Design
19801980ssHardware Description Languages (HDL) wereconceived to facilitate the information exchange
between design groups.
19901990ss
Nitin ChaturvediNitin Chaturvedi VLSI Design Methodology 36
introduction of logic synthesizers that can translatethe description in HDL into a synthesized gate-levelnet-list of the design.
20002000ssModern synthesis algorithms can optimize a digitaldesign and explore different alternatives to identifythe design that best meets the requirements.
7/28/2019 1 Digital L2 Intro
37/61
HDLHDL--Based Design MethodologyBased Design Methodology
Nitin ChaturvediNitin Chaturvedi VLSI Design Methodology 37
7/28/2019 1 Digital L2 Intro
38/61
Synthesis flowSynthesis flow
High-Level
Synthesis
Logic
Synthesis
Nitin ChaturvediNitin Chaturvedi VLSI Design Methodology 38
Physical
Design
Fabrication and
Packaging
7/28/2019 1 Digital L2 Intro
39/61
7/28/2019 1 Digital L2 Intro
40/61
VLSI Design StrategiesVLSI Design Strategies
Phenomenal growth rate in VLSI leads to a verycomplex and lengthy development of ICs.
Design complexity increases almost exponentiallyexponentiallywith the number of transistors to be integrated.
Efficient or anization of all efforts is essential to
Nitin ChaturvediNitin Chaturvedi VLSI Design Methodology 40
the survival of a company. Teamwork
Better tools
Innovatives and creativities.
Better StrategiesBetter Strategies
7/28/2019 1 Digital L2 Intro
41/61
Product LifeProduct Life--CycleCycle
Nitin ChaturvediNitin Chaturvedi VLSI Design Methodology 41
Products have a shorter lifeProducts have a shorter life--cyclecycle
7/28/2019 1 Digital L2 Intro
42/61
Comparison of Design StrategiesComparison of Design Strategies
Freedom of Choices.Freedom of Choices.
Custom DesignCustom Design
Nitin ChaturvediNitin Chaturvedi VLSI Design Methodology 42
7/28/2019 1 Digital L2 Intro
43/61
Comparison (Cont.)Comparison (Cont.)
Cell DesignCell Design
Nitin ChaturvediNitin Chaturvedi VLSI Design Methodology 43
FPGA DesignFPGA Design
7/28/2019 1 Digital L2 Intro
44/61
SystemSystem--OnOn--Chip (SOC) DesignChip (SOC) Design
Integrating all or most of the components of a
hybrid system on a single substrate (silicon or
MCM), rather than building a conventionalprinted circuit board.
Nitin ChaturvediNitin Chaturvedi VLSI Design Methodology 44
onsequences:
More compact system realization
Less expensive!
Higher speed / performance Better reliability
7/28/2019 1 Digital L2 Intro
45/61
Example of SOC DesignExample of SOC Design
Nitin ChaturvediNitin Chaturvedi VLSI Design Methodology 45
Digital Video ProcessorDigital Video Processor
7/28/2019 1 Digital L2 Intro
46/61
Example of SOC Design (Cont.)Example of SOC Design (Cont.)
Nitin ChaturvediNitin Chaturvedi VLSI Design Methodology 46
Each functional block can be reused block, IP (IntelectualEach functional block can be reused block, IP (IntelectualProperty) block, or customProperty) block, or custom--designed block.designed block.
7/28/2019 1 Digital L2 Intro
47/61
OutlinesOutlines
VLSI Design Flow and Structural Design
Principles
VLSI Design Styles
VLSI Desi n Strate ies
Nitin ChaturvediNitin Chaturvedi VLSI Design Methodology 47
ComputerComputer--Aided Design Technology for VLSIAided Design Technology for VLSI
CC Aid d i h lAid d i h l
7/28/2019 1 Digital L2 Intro
48/61
ComputerComputer--Aided Design TechnologyAided Design Technology
CAD tools become more and moreindispensable for timely development of ICs.
Remember! CAD tools are good helpers forCAD tools are good helpers fortimetime--consuming and computation intensiveconsuming and computation intensive
echanistic arts o the desi nechanistic arts o the desi n not the creativenot the creative
Nitin ChaturvediNitin Chaturvedi VLSI Design Methodology 48
and inventive parts!and inventive parts! CAD technology divides into three categories:
Synthesis Tools (Synopsys)Synthesis Tools (Synopsys)
Layout Tools (Cadence)Layout Tools (Cadence)
Simulation and Verification ToolsSimulation and Verification Tools
S h i T lS h i T l
7/28/2019 1 Digital L2 Intro
49/61
Synthesis ToolsSynthesis Tools
HighHigh--Level SynthesisLevel Synthesis tools automate the designphase in the top level of the design hierarchy:
Based onHardware-Description Languages (HDL) VHDLVHDL, VerilogVerilog, etc.
Determining the types and quantities of modules to
Nitin ChaturvediNitin Chaturvedi VLSI Design Methodology 49
be included in the design using accurate estimate oflower level design features (area and delay).
Logic Synthesis and optimizationLogic Synthesis and optimization tools can then
be used to customize the design to particularneeds, such as area minimization, low power,etc.
L T lL T l
7/28/2019 1 Digital L2 Intro
50/61
Layout ToolsLayout Tools
Circuit OptimizationCircuit Optimization tools deal with the designin the transistor schematic levels:
Transistor sizing for delay minimization
Reliability issues: process variations, noise.
Nitin ChaturvediNitin Chaturvedi VLSI Design Methodology 50
uu
the design, i.e., how circuits are actually built onthe IC:
Standard Layout CAD tools areFloorplanning,
Place-and-route, and Module generation
Sophisticated Layout CAD tools are goal driven andinclude some degree of optimization functions
Si l ti d V ifi ti T lSi l ti d V ifi ti T l
7/28/2019 1 Digital L2 Intro
51/61
Simulation and Verification ToolsSimulation and Verification Tools
Time spent on debugging and correcting a
design has been increasing exponentiallyexponentially as
each generation passed. Higher penalty is paid if a design flaw is detected
later in the desi n rocess.
Nitin ChaturvediNitin Chaturvedi VLSI Design Methodology 51
Simulation and verification are the most mature areain VLSI CAD
Goal of all simulation tools is to determine if thedesign meets the required specifications at a
particular design stage.
Si l ti T l (C t )Si l ti T l (C t )
7/28/2019 1 Digital L2 Intro
52/61
Simulation Tools (Cont.)Simulation Tools (Cont.)
Simulation tools used at various stages of the
design process are
Behavior simulationBehavior simulation tools
Logic Level simulationLogic Level simulation tools
Nitin ChaturvediNitin Chaturvedi VLSI Design Methodology 52
omp ement og c synt es s an opt m zat on too s.
CircuitCircuit--level simulationlevel simulation tools
SPICE or derivatives such as HSPICE, PSPICE, etc.
Design Rule CheckingDesign Rule Checking tools Layout rule checking,Electrical Rule CheckingElectrical Rule Checking (ERC),
reliability rule checking.
7/28/2019 1 Digital L2 Intro
53/61
Nitin ChaturvediNitin Chaturvedi VLSI Design Methodology 53
LayoutLayout
7/28/2019 1 Digital L2 Intro
54/61
LayoutLayout
Standard Cell Module
Nitin ChaturvediNitin Chaturvedi VLSI Design Methodology 54
Complete Design
Chip
Placement and RoutingPlacement and Routing
7/28/2019 1 Digital L2 Intro
55/61
Placement and RoutingPlacement and Routing
Routing in
FPGA
Detailed Placement and
Routing
Nitin ChaturvediNitin Chaturvedi VLSI Design Methodology 55
Chip FabricationChip Fabrication
7/28/2019 1 Digital L2 Intro
56/61
Chip FabricationChip Fabrication
GDS II
Nitin ChaturvediNitin Chaturvedi VLSI Design Methodology 56
World wide ICWorld wide IC FoundaryFoundary CentresCentres
7/28/2019 1 Digital L2 Intro
57/61
World wide ICWorld wide IC FoundaryFoundary CentresCentres
Nitin ChaturvediNitin Chaturvedi VLSI Design Methodology 57
International Technology Road MapInternational Technology Road Map
7/28/2019 1 Digital L2 Intro
58/61
International Technology Road MapInternational Technology Road Map
Nitin ChaturvediNitin Chaturvedi VLSI Design Methodology 58
World wide Semiconductor vendorsWorld wide Semiconductor vendors
7/28/2019 1 Digital L2 Intro
59/61
World wide Semiconductor vendorsWorld wide Semiconductor vendors
Nitin ChaturvediNitin Chaturvedi VLSI Design Methodology 59
7/28/2019 1 Digital L2 Intro
60/61
Nitin ChaturvediNitin Chaturvedi VLSI Design Methodology 60
ConclusionsConclusions
7/28/2019 1 Digital L2 Intro
61/61
ConclusionsConclusions
Different levels of Abstractions
VLSI Design Flow
Design Methodologies
es gn y es
Nitin ChaturvediNitin Chaturvedi VLSI Design Methodology 61