Introduction

With the consumer drive for more and more

data, worldwide operators are experiencing

an unprecedented need for wireless band-

width growth. Fortunately, the industry – along

with standards bodies such as 3GPP – is evolv-

ing support such demand. LTE has emerged as

the technology of choice for operators to meet

this exponential growth. As LTE deployment

becomes a reality, base station manufacturers

are favoring system-on-chip (SoC) architectures

to keep operator network costs low while main-

taining and improving service.

Supporting a successful LTE transition requires

a number of innovations in base station SoC

design. Texas Instruments (TI) has developed a

powerful and innovative multicore SoC architec-

ture called KeyStone that is designed to optimize

WCDMA and LTE performance while reducing

base station cost and power. For wireless base

station applications, an essential part of KeyStone

is the implementation of configurable coproces-

sors for the physical layer (PHY) or Layer 1 of the

wireless standards. This paper describes how TI’s

TCI6618 wireless system-on chip (SoC), based

on the KeyStone multicore SoC architecture, pro-

vides an optimized PHY LTE solution, streamlines

the development cycle for manufacturers, and

demonstrates the potential for eNodeB solutions

with competitive differentiation, lower capital ex-

penditure and operating expenses.

TMS320TCI6618 - TI’s high-performance LTE physical layer solutionThe exponential growth in the use of mobile data worldwide has posed significant challenges

to wireless operators. Fortunately, wireless technology has continued to evolve, and Long

Term Evolution (LTE) has become the worldwide standard of choice to meet the challenges.

The top 25 worldwide wireless operators have chosen to deploy LTE; some of them started

trials in 2010, with multiple market inflection point growth expected in 2012. LTE promises

better use of the operator’s spectrum by improving spectral efficiency; this means more bits

per Hertz than previous technologies. Operators must deploy LTE solutions at a rate that

keeps up with the data deluge – all while keeping the cost per bit to a minimum, reducing the

carbon footprint, and providing ease of migration from 3G to LTE.

The changes required to LTE systems present new challenges for operators, base station

vendors, and their suppliers. Texas Instruments has developed a powerful and innovative new

system-on-a-chip (SoC) architecture designed to reduce costs for LTE products and enable

manufacturers to benefit from cutting-edge base station technology. The KeyStone multicore

SoC architecture builds upon TI’s field-proven multicore DSP platforms and includes an

innovative new floating-point architecture and coprocessors for 4G systems. Adding to the

computational improvements are innovations to the backplanes and internal data movement,

which are critical to achieving full performance from a high-speed 4G SoC. With TI’s new

architecture, the industry will advance more rapidly towards deployments that enable the

high-value features of 4G systems.

LTE supports flexible channel bandwidths (1.4 – 20 MHz) as well as frequency-division

duplexing (FDD) and time-division duplexing (TDD) to allow flexible deployment around

spectrum ownership. The foundation of the LTE communication protocol stack is the physical

layer (PHY), sometimes referred to as Layer 1. The PHY layer is the basis of solid base

station-to-mobile device connectivity; without great wireless connectivity, calls drop, down-

loads fail, and videos stall.

The advanced PHYs in the TCI6618 are the industry’s gold standard for reliable

performance, and TI’s Layer 1 PHY technology is based on field-proven, configurable

coprocessors that support all popular wireless standards. This enables the migration from

3G to 4G on a common platform, making the transition to 4G appear seamless.

Zhihong LinStrategic marketing manager

Wireless base station infrastructure

Greg WoodApplication manager

Wireless base station infrastructure

W H I T E P A P E R

TMS320TCI6618 - TI’s high-performance LTE physical layer solution February 2011

2 Texas Instruments

LTE is the latest Third Generation Partnership Project mobile standard. LTE realizes major technology

advances over 3G mobile technologies and offers peak downlink rates of at least 100 Mbps and peak uplink

rates of at least 50 Mbps for the 20-MHz spectrum.

The PHY interfaces with Layer 2 (the media access control [MAC] layer) and Layer 3 (the radio resource

control [RRC] layer) and offers data transport services to higher layers. PHY handles channel coding, PHY

hybrid automatic repeat request (HARQ) processing, modulation, multi-antenna processing, and mapping of

the signal to the appropriate physical time-frequency resources.

LTE downlink PHY processing accepts data and control streams from the MAC layer in the form of

transport blocks and begins processing by calculating the cyclic redundancy check (CRC) and attaching it

to the transport block. If the transport block size is larger than the maximum allowable code block size of

6,144 bits, code block segmentation is performed. A new CRC is calculated and attached to each code

block before channel encoding. Figure 1 illustrates the major functional blocks in the LTE downlink.

Antennas Antennas

Resource blockmapping

Resource blockmapping

CRC attach

Code blocksegmentation

Turbo encoding

Rate matchingHARQ combining

Code blockconcatenation

Scrambling

Modulation

Antenna mapping

Transport block (s)Transport block (s)

CRC attach

Code blocksegmentation

Turbo encoding

Rate matchingHARQ combining

Code blockconcatenation

Scrambling

Modulation

Fig. 1 - LTE downlink transport channel processing

LTE radio interface architecture

TMS320TCI6618 - TI’s high-performance LTE physical layer solution February 2011

3Texas Instruments

Turbo encoding provides a high-performance forward-error-correction scheme for reliable transmission;

rate matching performs puncturing or repetition to match the rate of the available physical channel resource;

and HARQ provides a robust retransmission scheme when the user fails to receive the correct data. Bit

scrambling is performed after code-block concatenation to reduce the length of strings of 0s or 1s in a

transmitted signal to avoid synchronization issues at the receiver before modulation.

Various modulation schemes (quadrature phase shift keying [QPSK], 16 QAM [quadtrative amplitude mod-

ulation], or 64 QAM) are used for LTE layer mapping, and precoding supports multi-antenna transmission.

Finally, the resource elements of orthogonal frequency-division multiplexing (OFDM) symbols are mapped to

each antenna port for air transmission.

LTE leverages many advanced technologies used in 3G HSPA+ (high-speed packet access), like turbo coding,

HARQ, and multi-antenna schemes. LTE offers a solution for 20 MHz of 100 Mbps on the downlink, 50 Mbps

uplink and higher with multi-antenna signal processing schemes. TI’s TCI6618 solution supports two sectors

20 MHz, 2x2 multiple input, multiple output (MIMO) solution of 300 Mbps downlink and 150 Mbps on the

uplink, with signal processing overhead for value add and advance algorithms. In addition, LTE uses OFDM

and both downlink and uplink multiple-input/multiple-output (MIMO) technology to provide significant

performance improvements over 3G systems.

OFDM transmission – LTE uses OFDM for radio transmission, providing a robust transmission mechanism

with protection against degradation from severe channel conditions, narrow-band co-channel interference,

and intersymbol interference and fading. It also delivers high spectral efficiency and low sensitivity to time

synchronization errors.

LTE downlink processing uses multicarrier OFDM transmission with a cyclic prefix. In the uplink,

wide-band single carrier OFDM transmission with a cyclic prefix reduces the variation in the instantaneous

power of the transmitted signal. The fast Fourier transform (FFT) provides low complexity and efficient

implementation for OFDM modulation and demodulation.

LTE technology evolution

TCI6618 – the LTE enabler

TMS320TCI6618 - TI’s high-performance LTE physical layer solution February 2011

4 Texas Instruments

IDFT

MIMOchannel

estimation

Softslicer

Descramblerchannel

de-interleaver

Rx bit rateprocessing

User 1 data

User 2 data

IDFT Softslicer

Descramblerchannel

de-interleaverRx bit rateprocessing

UE 1

UE 2

Cyclic prefix

Cyclic prefix

Tx bit rateprocessing

Tx bit rateprocessing

Ref. signal/Data signalseparation

Reference signal processing

Ref. signal/Data signalseparation

Ref. signal/Data signalseparation

Ref. signal/Data signalseparation

Channelinterleaverscrambler

Channelinterleaverscrambler

Modulationmapper

Modulationmapper

DFT

DFT

Resourceelement mapper

Resourceelement mapper

IFFT

IFFT

Cyclicprefix

removalFFT

UL MIMOreceiver

Resourceelement

de-mapper

Cyclicprefix

removalFFT

Resourceelement

de-mapper

Cyclicprefix

removalFFT

Resourceelement

de-mapper

Cyclicprefix

removalFFT

Resourceelement

de-mapper

Fig. 2 - LTE MIMO channel model

MIMO technology – Smart antenna technology using MIMO antennas is adopted in LTE at both the

transmitter and receiver to improve performance. MIMO offers significant increases in data throughput

and coverage without additional bandwidth or transmit power, providing higher spectral efficiency and link

reliability against fading. Figure 2 illustrates the LTE 2x4 uplink MIMO channel model and receiver handling.

Multiple antenna uplink MIMO receiver techniques can help increase the signal-to-noise ratio.

Maximum-ratio combining (MRC) is an effective antenna-combining strategy when the receiver is

primarily impaired by noise. In interference-dominate-channel conditions, a minimum mean square error

(MMSE)-combining technique is a better approach to determine the antenna weighting vector that minimizes

the mean square error. Floating-point implementations of MMSE MIMO equalization can significantly reduce

computational complexity and provide high performance, resulting in an efficient LTE MIMO receiver.

The TCI6618 SoC is a member of TI’s TMS320C66x DSP multicore generation. Based on TI’s new KeyStone

multicore architecture, it is designed for high-performance wireless infrastructure applications and provides

a perfect fit for LTE design challenges. Figure 3 illustrates the features and processing elements of the device.

The KeyStone multicore architecture is the first to provide a high-performance structure for integrating

reduced instruction set computer (RISC) and DSP cores with application-specific coprocessors and I/O.

KeyStone is the first multicore architecture that provides adequate internal bandwidth for nonblocking and

zero-delay access to all processing cores, peripherals, coprocessors, and I/O. This is achieved with four

main hardware elements: Multicore Navigator, TeraNet, Multicore Shared Memory Controller, and Hyperlink.

Multicore Navigator is an innovative packet-based manager that controls 8,192 queues. When tasks are

allocated to the queues, Multicore Navigator provides a hardware-accelerated dispatch that directs tasks

to the appropriate hardware available. The packet-based SoC uses the 2-Tbps capacity of the TeraNet

switched central resource to move packets.

The Multicore Shared Memory Controller allows processing cores to access shared memory directly

without drawing from TeraNet’s capacity, so packet movement cannot be blocked by memory access.

Hyperlink provides a 50-Gbps chip-level interconnect that allows SoCs to work in tandem. Its low-protocol

overhead and high throughput make Hyperlink an ideal interface for chip-to-chip interconnections. Working

with Multicore Navigator, Hyperlink dispatches tasks to tandem devices transparently and executes tasks as

if they are running on local resources.

TCI6618 key features for LTE

Multicore Navigator

IPY 4/Y 6fast path

IPsec/SRTP

GTP/SCTP

IEEE 1588

Network coprocessor

RoHC

QoS

Air ciphering

RLC/MAC

Scheduler Fast path

Layer 2 coprocessor

Layer 1 acceleration

PUCCH

Interleaverde-interleaver

Scramblerde-scrambler

Ratematching

Modulator

Uplink chip rate

Interferencecancellation

Viterbidecoder

Turboencoder

HARQcombining

CRC

Convolutionencode

Ratede-matching

De-modulator

Downlinkchip rate

TFCI CQIdecoder

FFT/DFT

Turbodecoder

Tera

Net

Memory system

Multicore shared memory controller (MSMC)

2MB shared memory

64-bitDDR3EMIF

System elementsPower

management System monitor

Debug EDMA

Peripherals and I/O

SRIO 4x

SGMII2x

UART

Gig Eswitch

SPICPRI/OBSAI

PCIe 2x

I2C Hype

rLin

k

1 MB L2cache

1 MB L2cache

1 MB L2cache

RSA

C66x DSP

CorePac

CorePac

CorePac

CorePac

1 MB L2 cache

RSA

Fig. 3 - TMS320TCI6618 block diagram

TMS320TCI6618 - TI’s high-performance LTE physical layer solution February 2011

5Texas Instruments

C66x cores – The TCI6618 has four 1.2-GHz C66x cores that support both fixed- and floating-point

arithmetic operations. It offers 153.6 GMACs per second for fixed point and 76.8 GFLOPs per second for

floating point at 1.2 GHz. The C66x instruction-set architecture adds 90 new high performance instructions,

especially floating-point instructions and vector-signal-processing instructions, supporting two-way single

instruction multiple data (SIMD) operation for 16-bit data and four-way SIMD for 8-bit data. The very-long-

instruction word architecture supports eight simultaneous issues and is optimized for complex arithmetic and

matrix processing. Its reduced latency floating-point capability, together with a four times improvement in

MAC performance, accelerates LTE MIMO equalization and improves most DSP processing required for LTE.

BCP – A bit rate coprocessor (BCP) is a multi-standard acceleration engine that offloads the entire bit rate

processing in the wireless signal chain. The BCP accelerates the following processing functions:

• Modulation

• Demodulation

• Interleaving

• De-interleaving

• Turboandconvolutionencoding

In addition to offloading the DSP cores from the processing of these functions, the BCP also enables

advanced receiver algorithms such as turbo interference cancellation. Turbo interference cancellation can

increase the SNR by 3 dB, which increases the spectral efficiency up to 40 percent, a key performance

metric for wireless systems. The BCP offloads approximately 15 GHz of DSP cycles while delivering downlink

throughput of 2.2 Gbps and uplink throughput of 1.1 Gbps.

TCP3d – The Turbo-Decoder Coprocessor 3 (TCP3d) is a programmable peripheral for decoding LTE turbo

codes in uplink processing. The inputs into the TCP3d are channel-soft decisions for systematic and parity

bits, while the outputs are hard decisions. TCP3d generates the turbo interleaver table, performs turbo decod-

ing, and supports code-block-based CRC calculations. TCP3d is seven times faster than its prior generation

TCP2 with very small driver overhead. The TCI6618 contains three TCP3d coprocessors with a total through-

put of up to 582 Mbps at six iterations.

TCP3e – The Turbo-Encoder Coprocessor 3 (TCP3e) is a programmable peripheral for encoding LTE turbo

codes for downlink processing. The inputs into the TCP3e are information bits and the outputs are encoded

systematic and parity bits. It supports code-block-based CRC, turbo encoding, and turbo interleaver table

generation. TCP3e can offload 450-Mbycles per second CPU processing at 150 Mbps downlink throughput.

The TCI6618 has four TCP3e coprocessors with a total throughput up to 2572 Mbps.

FFTC – The fast Fourier transform coprocessor (FFTC) is an accelerator that is loosely coupled with the DSP

cores. It is attached to the TeraNet and uses Multicore Navigator to input and output packets requiring FFT

functions. FFTC has cyclic prefix removal and insertion features that can be programmed to ignore or add

TMS320TCI6618 - TI’s high-performance LTE physical layer solution February 2011

6 Texas Instruments

• Ratematching

• Ratede-matching

• CRCattaching

• Decodingofcontrolchannelinformation

samples in the beginning of the packet data; this allows a seamless interface between the antenna interface

and FFTC without requiring software to perform the cyclic prefix handling. FFTC can also apply a frequency

shift of the input data according to LTE requirements. The following use cases illustrate examples where

FFTC is used in LTE:

•Front-endFFTforon-timesymbolprocessing,includingcyclicprefixremovalandfrequencyshift

•DiscreteFouriertransform(DFT)/inversediscreteFouriertransform(IDFT)forchannelestimation

•DFT/IDFTforchannelsounding

•DFT/IDFTforfrequencyoffsetcompensationandestimation

•IDFTforgeneraluserde-mapping

•IFFTfordownlinkandcyclicprefixextension

•DFTandIDFTforphysicalrandomaccesschannel(PRACH)processing

•DFT/IDFTforinterferencerejectioncombiningprocessing

The TCI6618 has three FFTC units with a combined maximum throughput of 1,900 Mcarriers per second.

In a LTE system with 20-MHz bandwidth, 2x2 MIMO configuration, this FFTC cluster offloads more than 1.6

GHz of DSP core processing. In other words, it saves more than one full DSP core of SoC resources.

RSA – The Rake Search Accelerator (RSA) is used for LTE block code decoding. The TCI6618 has two RSAs

tightly coupled on each of two DSP cores. RSA provides hardware acceleration for correlation and search

algorithms, allowing efficient implementation of LTE uplink control information (UCI) over physical uplink

shared channel (PUSCH) decoding. Using RSA saves more than 1 GHz of DSP processing for UCI over PUSCH

decoding algorithm.

AIF2 – The TCI6618 antenna interface 2 (AIF2) is a proprietary peripheral module that supports transfers of

baseband in-phase and quadrature (IQ) data between uplink and downlink baseband DSP cores and high-

speed serial interfaces connecting to a digital radio front end. AIF2 supports LTE frequency-division duplexing

(FDD), time-division duplexing (TDD), and both Common Public Radio Interface (CPRI) and Open Base Station

Architecture Initiative (OBSAI) protocols. AIF2 supports six links; each link has a 6-GHz SERDES and 64

maximum antenna carriers per link.

AIF2 has Multicore Navigator built in and a direct connection to FFTC, which provides low latency antenna

traffic for LTE systems. AIF2 also has programmable radio timers for frame timing and synchronization to

support multiple standards. It provides 12-Gbps maximum Ingress bandwidth and 12-Gbps maximum Egress

bandwidth.

Network coprocessor – The network coprocessor provides Ethernet packet acceleration and security ac-

celeration mainly used in LTE Layer 2 processing. Its built-in CRC engine can be used for LTE PHY transport

block CRC calculation.

Efficient FFTC front-end data dispatching – The KeyStone multicore architecture enables a seamless

interface between AIF2 and FFTC with no intervention required from software running on the DSP core. It also

supports multicore load balancing using the Multicore Navigator infrastructure.

TMS320TCI6618 - TI’s high-performance LTE physical layer solution February 2011

7Texas Instruments

TMS320TCI6618 - TI’s high-performance LTE physical layer solution February 2011

8 Texas Instruments

AIF2 and FFTC are optimally designed for LTE OFDM processing. Both continue the Multicore Navigator’s

packet direct memory access (DMA) engine enabling a DSP core intervention-free data path between AIF2

and FFTC with direct connection through queues.

Figure 4 illustrates the use of Multicore Navigator to achieve load balancing, scheduling, system

partitioning, and memory usage reduction in LTE uplink symbol processing.

In this example, four antenna streams are fed into FFTC, with the partition and scheduling information

programmed into the FFTC input queue descriptors. Each core has three dedicated FFTC output queues

with desired antenna and data symbol information reallocated to dispatch to different cores on a per-packet

basis using Multicore Navigator.

By using Multicore Navigator queue descriptor header protocol-specific information, FFTC output data

is sorted with one queue receiving FFTC output data symbols and one queue receiving the output pilot

symbol. A third queue contains the symbol data that interrupts a core to start data processing. The core

can efficiently process the front-end FFTC data without any data preprocessing overhead. The FFTC provides

load balancing by routing a portion of the data and pilot symbols to each core that will be performing channel

estimation and equalization.

By using Multicore Navigator queues for FFTC output data, Layer 2 memory space can be saved by

employing multisegment host packet descriptors. Undesired guard tones before and after the primary

symbols can be stored in segments of memory that are immediately recycled with each transfer. Only the

useful data (primary symbols) are stored in Layer 2 for later processing. This results in a 50 percent

memory-buffer reduction for FFTC front-end processing. Figure 5 illustrates this memory reduction using

Multicore Navigator queue-linked descriptors.

Fig. 4 - Load balancing, scheduling and system partitioning using Multicore Navigator

L2Core0

FFT outputUplink PHY processing

L2Core1

L2Core2

L2Core3

Queue manager

Data symbol queuePilot symbol queue

Interrupt queue

FFTCAIF

LTE solutions with the TCI6618

TMS320TCI6618 - TI’s high-performance LTE physical layer solution February 2011

9Texas Instruments

Buffer pointer location in L2

Linked buffer descriptorin data symbol queue

Useful data buffers

. . .

. . .

Guard tonelocation

Left guard tone pointer

Data pointer

Right guardtone pointer

Fig. 5 - Memory reduction with Multicore Navigator packet queue

The TCI6618 platform development kit (PDK) contains drivers for the BCP, FFTC, TCP3d, TCP3e, Multicore

Navigator, RapidIO®, network coprocessor, enhanced direct memory access (EDMA), and chip

support library. It enables an excellent out-of-box user experience and shortens R&D development cycles.

TI also provides LTE PHY software, offering building blocks for customer PHY solutions that are highly

optimized for the C66x cores. The BCP offloads the entire bit rate processing and PUCCH format 2, 2a, and

2b decoding in hardware. The LTE library includes software for PUSCH symbol, PUCCH format 1, 1a, and

1b decoding and PRACH receiver processing, and physical downlink shared channel (PDSCH) symbol rate

processing. Figure 6 shows the complete downlink PDSCH handling using the TI LTE library with TCI6618

accelerators.

Fig. 6 - PDSCH processing

ModulationmapperScramblingCode block

concatenationFrom L2 CRC

attachTurbo

encoding

Bit rate processing

Symbol rate processing

FEC blocksegmentation

Ratematching

Primary/secondarysync signalgeneration

Referencesignal generation

Resource mappingpattern generation

Physicalresource mapper Precoding Layer

mappingIFFTAIF

Accelerated by TCI6618 HWLegend

Provided by TCI6618 LTE Lib SW

The FFTC can also be used for channel estimation to offload DSP processing. In LTE, channel estimation is

performed based on a reference signal (the fourth symbol in a resource block) embedded in the uplink frame.

TI’s LTE library software provides channel estimation functions performed at each data-carrying resource

element in a subframe.

The first stage of channel estimation can take advantage of FFTC to construct the frequency smoothing

estimator. Performing IDFT translates channel estimates from the frequency domain to the time domain

and uses a rectangular window to cut off the time-domain channel taps to obtain the time-domain channel.

Optionally, a threshold can be used to reduce the noise. Afterwards, performing a DFT generates the

frequency-domain channel estimates. The second stage of the channel estimates can be calculated on a

per-subcarrier basis through linear interpolation/extrapolation of the estimation results from the first stage.

Figure 8 shows the PUSCH channel estimation process.

TMS320TCI6618 - TI’s high-performance LTE physical layer solution February 2011

10 Texas Instruments

LTE uplink processing requires significant CPU cycles for PUSCH channel estimation and equalization.

Depending on the number of antennas, the C66x expanded instruction set architecture and floating-point

arithmetic computations provide as much as a 4x cycle reduction for the MRC equalizer relative to the

C64x+™ architecture. With floating-point calculations, more efficient algorithms like block-wise matrix

inversion can be used to achieve the same performance – and with up to 5x cycle reduction than the more

complex fixed-point Cholesky decomposition algorithm for the MMSE MIMO equalizer.

The control channel decoding provided by the BCP offloads a large number of software cycles and provides

better performance than algorithms typically used in software. In some cases, this can save up to 1.4 GHz of

DSP processing, equivalent to more than a core of DSP savings. Figure 7 shows PUSCH processing using the

TCI6618 and its highly optimized LTE library software.

Fig. 7 - PUSCH processing

CPRI

To L2

MRC or MMSE MIMO

equalizerFFT IDFTAIF De-channelization Channel

estimationFrequency

offsetcompensation

CRC De-segmentation

Turbodecoding

RSAUCI overPUSCH

Control infoover PUSCH

Rate De-matching HARQ

combining

De-interleavingdescrambling

de-concatination

Accelerated by TCI6618 HW acceleratorsLegend Provided by TCI6618 LTE Lib

Bit rate processing

Symbol rate processing

The FFTC can also be used in PUSCH channel frequency offset compensation and estimation, as well as

in various stages of uplink PRACH processing. Two FFTC accelerators in the TCI6618 can greatly offload LTE

signal processing from DSP cores. By leveraging the TI LTE library software on C66x DSP cores and fully

utilizing TCI6618 hardware accelerators, LTE PHY processing of the Physical Uplink Shared Channel (PUSCH),

Physical Uplink Control Channel (PUCCH), Physical Downlink Shared Channel (PDSCH), Physical Downlink

Control Channel (PDCCH) and Physical Random Access Channel (PRACH) channels can be integrated into a

single TCI6618 device.

The TCI6618 supports FDD LTE for two sectors of 20 MHz bandwidth, 2x2 MIMO with throughput of 150

Mbps downlink and 75 Mbps uplink using advanced receiver algorithms.

The KeyStone SoC multicore architecture and unmatched TCI6618 system, peripheral and accelerator

bandwidth and throughput bring LTE mobile broadband into affordable reality and enable cost-effective and

best-performance LTE solutions to the market.

The TCI6618 is a product of continuous innovation built on top of TI’s years of wireless base station system

knowledge and field-proven technology. TI’s KeyStone SoC architecture provides highest throughput and

future-proof architecture for LTE and its continuous technology evolution. Four high performance DSP cores

with integrated fixed- and floating-point capabilities deliver the most powerful cores for LTE PHY processing.

The rich set of hardware accelerators reduces the LTE system latency and frees up CPU resources to achieve

optimal LTE system capacity and competitive differentiation. The TMS320TCI6618 offers the most robust

hardware platform combined with a development ecosystem that includes fully-optimized LTE PHY library

software. Platform development software accelerates development efforts to enable best-in-class LTE PHY

solutions to customers.

For more information visit www.ti.com/tci6618

To equalizerDMRSDFTIDFT

Windowing and noise floor

removalPilot

demodulation Interpolation

Received demodulation reference signal

Fig. 8 – PUSCH channel estimation

11Texas Instruments

Conclusion

A042210

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