ZettaCore Molecular Technology

Stanford Computer Systems Colloquium, April 20, 2005

Dr. Ritu ShrivastavaVice President, Process and Manufacturing TechnologyZettaCore, Inc.

www.ZettaCore.com

OUTLINE

• Nanotechnology• Silicon Scaling• ZettaCore Markets• DRAM Approaches and Issues• ZettaCore Technology Overview• Testchip Results• Process Integration Path• Conclusion

Nanotechnology – The Vision

“It is a staggeringly small world that is below. In the year 2000, when they look back at this age, they will wonder why it was notuntil the year 1960 that anybody began seriously to move in this direction.”

“Why cannot we write the entire 24 volumes of the Encyclopedia Brittanica on the head of a pin? ”

“I am not afraid to consider the final question as to whether, ultimately --- in the great future --- we can arrange the atoms the way we want; the very atoms, all the way down!”

“What would the properties of materials be if we could really arrange the atoms the way we want them?”

Richard P. Feynman, Nobel Laureateat the meeting of the American Physical Society, “There is plenty of room at the bottom”, December 29, 1959 at California Institute of Technology (published Feb 1960 in Caltech’s Engineering and Science)

“There is plenty of room at the bottom”

What is Nanotechnology?

“Working at the atomic molecular and supramolecular levels, in the length scale of approximately 1 to 100 nanometer range, in order to understand and create materials, devices and systems with fundamentally new properties and functions because of their small structure”

Source: NSF

• Human hair: 20 ~ 150um• Red blood cells: 7um• Intel 286 processor: 5um• Viruses: 150nm• IBM PowerPC: 90nm• Silicon limit: 10 ~ 15nm• Infineon carbon nanotubes: 7nm• DNA research: 2nm• Single carbon nanotube: 1.5nm• Hydrogen atom: 0.1nm

Source: Business Week, April 18, 2005

• ZettaCore molecules: 0.1~ 5nm

Note: 1nm = 10A = 0.001um

Large Investment in Silicon Technology

Large Investment in Silicon Technology

Source: ftp://download.intel.com/research/silicon/Josh_Fab_24_061404.pdf

Silicon Technology will Continue

Silicon Technology will Continue Until…

From Sand to Green ?

Source: ftp://download.intel.com/research/silicon/Josh_Fab_24_061404.pdf

Sand to Silicon Chips

Porphyrins: Nature’s Pigments of Life

Heme• Fast electron-transfer reactions

• Stable radical cations

• Operate under real-world conditions

R = CH3R = CHO

Chlorophyll aChlorophyll b

The ZettaCore Approach: Porphyrins

• Enable memory cells below 90nm technology• No good alternative in sight

• Achieve or exceed Moore’s Law for memory• 1 Tbit / in2

• Significant cost advantage grows over time• Make memory profitable again

• Fully CMOS compatible: volatile and later non-volatile• Leverage existing facilities, people, processes

ZettaCore, Inc.

• ZettaCore is focused on molecular memory applications. Our technology will lead to significant advances in memory capability, playing a key role in new generations of electronic devices, both large and small.

• The ability to integrate ZettaCore molecular technology with state-of-the-art semiconductor technology allows accelerated development of hybrid chips that leverage both the advantages of molecular storage and the substantial capital investment in the semiconductor manufacturing industry.

• Our process uses specially-designed molecules that can store and utilize much more data than typical semiconductors. They can be scaled to very small sizes. They use less power. And they can be programmed to assemble themselves during the manufacturing process.

ZettaCore Team

• Subodh Toprani, President and CEO• Senior VP, Infineon; CEO, Catamaran; VP, Rambus

• Randolph Levine, Founder and Director• Clinical Micro Sensors (Motorola); DEC; Harvard University

• Craig Rhodine, VP of Engineering• COO, Ramtron International Corporation

• Ritu Shrivastava, VP of Process & Manufacturing Technology

• VP/GM Alliance Semiconductor• Director Technology, Cypress; Mostek

• Brian Cree, VP of Finance• CFO and COO experience at three start-ups

• Werner Kuhr, VP of Research• Founding scientist• Formerly Professor of Chemistry, UC Riverside

• Srinivas Nimmagadda, VP of Business Development• Formerly with Catamaran (Infineon) and Rambus

• Vinod Khosla• General Partner, Kleiner

Perkins• Les Vadasz

• Formerly head of Intel Capital

• Director Emeritus, Intel• Steve Jurvetson

• Draper Fisher Jurvetson• Herb Goronkin

• Formerly VP Motorola Labs• Jordan Davis

• Radius Ventures• Subodh Toprani

• President and CEO• Randolph Levine

• Founder

Board of DirectorsManagement Team

Other founders/R&D: Professors Jonathan S. Lindsay (founder), David F. Bocian (founder), Veena Misra, Richard L. McCreery

Conventional Capacitor Challenges

DielectricMaterial

SiliconSubstrate

Poly

DopedSilicon Metal or

Poly

Deep-trench Capacitor100:1 aspect ratio

Stacked CapacitorUses multiple layersIncreases cell sizeTopography challenges

Capacitor Issues• Scaling problems beyond 90nm• Limits overall yield• Logic process incompatibility• Inadequate Charge density• Soft-error rate problems• R&D costs ~$100M+/yr• Increasing device manufacturing costs• High leakage

DRAM Trench Cell Example: 70nm Technology

• Infineon deep trench (DT) DRAM cell• Trench aspect ratio > 70:1• HSG (hemispherical silicon grains).

Trench surface area increased by “wet etch bottle process”

• Al2O3 ALD (atomic layer deposition) high-k DT dielectric

J. Amon et. al., IEDM, 2004, pp. 73-76

DRAM Stacked Cell Example: ~70nm Technology

D. H. Kim et. al., IEDM, 2004, pp. 69-72

• Samsung MESH stacked DRAM cell• Previous HSG approaches cause

bridging, hence taller storage node (SN) approach

• Mechanical problems (leaning of SN) !• Mechanically Enhanced Storage node

for Height (MESH) using Si3N4 MESH supporters

• AHO (Al2O3-HfO2) dielectric ~23A SiO2• SN height 2.5um for 30fF/cell =>

aspect ratio: 20:1, surface area: 2um2

• 512Mb DRAM @ 80nm on left

TiN/HfO2/TiN Cylindrical Capacitor: 70nm Technology

• Samsung 70nm capacitor technology• Cylinder height vs. equivalent oxide

thickness• 52A ALD HfO2/ 19A Al2O3 used for 13A

equivalent oxide• Carbon contamination optimized by

HfO2 process/O2 plasma anneal conditions

S-H Oh, 2003 VLSI Technology Symposium

A Small DRAM Cell: 6F2 at 78nm Technology

• Micron Technology cell• 78nm 6F2 cell for 2~4Gb• F ~ 78nm• Cell size: 0.036um2

• HfO2/Al2O3 MIM capacitor• Polysilicon plugs

F. Fishburn et. al., 2004 VLSI Technology Symposium

Other Process Components Needed in DRAMs: Example - Vertical Transistor Scaling Path

IBM Trench Capacitor Cell Technology Roadmap

R. Divakaruni et. al., 2003 VLSI Technology Symposium

High-k Dielectrics

• Most very high-k dielectrics have issues (e.g., instability, etching problem etc.)

Cell Size Scaling: DRAMs vs. SRAMs

• DRAM still provides the smallest cell size• Can smaller DRAM cell be used in embedded SRAM applications?

SRAM Cell Size IEDM/VLSI Data points:• 130nm: 2.28um2 (Foundry)• 130nm: 0.562um2 (T-RAM, IEDM 2004)• 80nm: 0.16um2 (Samsung 512Mb S3) => 25F2• 65nm: 0.57um2 (Intel 70Mb w/o redundancy)• 45nm: 0.247um2 (Toshiba E-SRAM)• 45nm: 0.296um2 (TSMC)• 45nm: 0.314um2 (IMEC, IEDM 2004)• 32nm: 0.143um2 (IBM, IEDM 2004)

DRAM Cell Size IEDM/VLSI Data points:• 78nm: 0.036um2 (Micron) => 6F2• 45nm: 0.069um2 (Toshiba)

S. M. Jung et. al., IEDM, 2004, pp. 265-268

Embedded DRAM Examples

• NEC Electronics embedded DRAMs• Lower temperature capacitor processes

to avoid transistor degradation• MIS to MIM capacitors• Ta2O5 and ZrO2 used for cap dielectric

http://www.necel.com/en/process

Older generation commodity DRAMs: CUB (Capacitor Under Bit line)Higher temperature capacitor formation

0.13um Embedded DRAMs: COB (Capacitor Over Bit line)

Low temperature capacitor formation COB (Capacitor Over Bit line)

1T1C DRAM Scaling

• Capacitance • Keep ~25 fF

• Memory-cell transistor • Keep or improve low leakage current

ITRS 2004Tomoyuki Ishii, Hitachi, ISSCC 2005 – Memory Forum

Molecular Memory Value Proposition

Bottom Electrode (Metal i)

Molecular Mono-layerCharge Transfer Layer

Top Electrode (Metal j)

Silicon Substrate

• Planar process• Improvement in cost compared to

embedded DRAM• Compatible with CMOS processing• Increased density

• Up to 10X improvement in density compared to embedded SRAM

• Up to 10X improvement in cost compared to embedded SRAM

• Smaller footprint for Mobile/Handheld applications

• Improved data retention • Improvement in leakage/stand-by power• Longer Stand-by capacity for

Mobile/Handheld applications• Improved reliability

• Improvement in Soft-error-rate (SER)• Inherent redundancy in charge storage

Dielectric

Conventional Embedded RAM Challenges

• 6T embedded SRAMs are no longer practical for many applications• At 90nm, typical SRAM cell size is 150F2 and going up• RAM content in System LSI is growing to 70-90% within a few years

• 6T embedded SRAMs are difficult to scale due to • Increased Soft-error-rate (SER)• Increased leakage current

• Embedded DRAMs are expensive due to • Additional process steps; Incompatibility between Logic and DRAM• Typical cost adder is 40-60% over Logic process cost

• Embedded DRAMs are difficult to scale due to• Capacitor scaling limitations• Smaller capacitance requires on-chip error correction for soft errors

Cosmic-ray : Dominant for Soft Errors DRAMs Better than SRAMs

Memory Capacity (Mbits)

SER

Cro

ss S

ecti

on/c

hip

(cm

2)

0.1 1 10 100 1000

1E-5

1E-6

1E-7

1E-8

1E-9

1E-10

DRAM

SRAM

Troposphere Stratosphere

Ionosphere

Sea level

Heavy ions from center of the galaxy

Solar magnetic field

Earth magnetic field

Earth

Neutron shower

Soft error

Nuclear reaction in air

Neutron showerTokyo: 20 /h/cm2

@sea level

Neutron-induced soft errors have been recognized as a serious problem for logic LSI, even at sea level.

Alpha-ray

Nuclear reaction16

0 fC/

mµ

16 f C/

mµ

Cosmic-ray neutron

Takayuki Kawahara, Hitachi, ISSCC 2005 – Memory Forum

New Retention Mechanism Required

Viewpoint: “Read” and “Retention”

• Smaller storage charge requires smaller leakage current or frequent refresh

1

10

100

1,000

10,000

100,000

1,000,000

0.5 0.1 0.01 0.003

1T-1C DRAM

SRAM

Flash

Fabrication process (µm)

Num

ber o

f ele

ctro

ns fo

r 1 b

it

Req

uire

d le

akag

e cu

rrent

fo

r DR

AM

pas

s tra

nsis

tor (

A)

10-19

10-18

10-17

10-16

10-15

10-14

Scaling in number of stored electrons for 1 bit

Tomoyuki Ishii, Hitachi, ISSCC 2005 – Memory Forum

Embedded ZettaRAM Memory Benefits

Density – true DRAM density (>128Mb) in a Logic process

Power – up to 70% lower refresh current compared to DRAM

Fully CMOS compatible – leverages existing infrastructure

Cost – smaller effective cell size; less number of process steps

Scalability – roadmap to 90/65/45/22nm process nodes

Reliability – no ECC requirement; inherent built-in redundancy

ISSCC 2004 – Paper 27.3

Potential ZettaRAM Memory Benefits: Replacing eSRAM by eDRAM

L2 Cache

CPU Core

L3 Tag

BusLogic

L3 Cache

ISSCC’04 CPU CPU with DRAM

L2 Cache

CPU Core

L3 Tag

BusLogic L3

L3

Chip size

245mm2

(43% smaller)

*23mm

*14mm

(4x denser/2x slower)

* 39% decrease in wire delay to furthest L3-cache subarray

L3 Latency (normalized to 20 cycles)L3-Tag L3-Cache Wire Delay

432mm2

SRAMeDRAM

5 cyclesTotal

5 cycles5 cycles

10 cycles10 cycles6 cycles

20 cycles21 cycles

Replacing eSRAM by eDRAM

John Barth – IBM Systems and Technology Group, ISSCC 2005 – Memory Forum

Dynamic Random Access Memory (DRAM)

I/O

Vref (BGR)

Buffer

VDD

Charge Pumps

VDH/VBB

LevelShifter

Amp.

Decoder

DriverPeriphery

Array

Voltage Generators

VCC

VCC

WL

BLSub-1V

: Sub-1V : Boosted Voltage

Total dissipated charge of bit linesSub-1V DRAM

VBL +Vthmax+α

VBL

VW

Vthmax+α

BL

BL

WL

Vthmax

BLWL

BL

SA

K. Itoh et. al., “ Limitations and Challenges of Multigigabit DRAM Chip Design”, JSSC 1997, pp. 624-634.

nW

Effective cell area= cell area + overhead.vsig = VDD/2 x CS/(CD +CS)= 200 mV, CS = 25 fF,3 poly, without SAC

cell

WLDL

DL

SA

Power Supply, VDD (V)0.5 1 1.5 2 2.5 3

0

40

60

20

32

64128

256 512(nW)

16

Effe

ctiv

e C

ell A

rea

(F 2

)

80 Cell Cell

SA SA• Trust on the bit-line division to maintain the signal.• Results in increase in the effective cell area

Takayuki Kawahara, Hitachi, ISSCC 2005 – Memory Forum

DRAM Scaling Problem with Reduced Supply Voltage (1T-1C No Gain Cell)

DRAM Scaling Problem with Reduced Supply Voltage

• What if required Storage capacitance (Cs) is not achieved due to process complexity• Cs reduction results in large cell area overhead due to BL division• Non charge-sharing read approaches (e.g., 3T or 4T gain cells) may be required

• Need higher Cs to avoid area penalty with voltage scaling in 1T-1C cell

Supply voltage VDD (V)

Effe

ctiv

e ce

ll ar

ea (F

2 )

0

20

40

60

80

100

0 0.5 1 1.5 2 2.5 3

Cs=20fF 10fF 5fF

8F2

4T(~55F2)

3T(~40F2)

4cell/BL

8cell/BL

16cell/BL32cell/BL64cell/BL

Vsig=150mVFolded bit line

BL SA

Effective cell area=2F*(BL length +SA length)/(number of cells per BL)

Tomoyuki Ishii, Hitachi, ISSCC 2005 – Memory Forum

ZettaCore Technology Overview

Problems with Existing DRAM Chips

Semiconductor charge-storage element:

• Short charge retention times (frequent refresh rate)

• Low charge density (requires deep trench or stacked cell)

• Voltage of operation is not low

• Amount of stored charge depends on applied potential

• Physical properties change in going to small feature sizes (not scalable)

• Multiple bits hard to achieve

Why Molecular Memory?

• Flexible

• Scalable

• Compatible

• Engineered Characteristics• Multiple Markets

• Higher Density• Lower Cost

• Existing Facilities• Leverage Capital

“Engineerable” Molecule Properties

• Charge storage molecule• Composition determines charge

density, size, isolation, voltage, stability (thermal and electrical)

• Surface attachment group (tether)• Composition determines site of

attachment, stability (i.e., endurance), charge transfer rate, charge retention

“Engineerable” Molecule Properties

N NN N

Zn

Fe

SX

Surface = metal, Si, SiO2, others

• Charge storage molecule• Composition determines charge

density, size, isolation, voltage, stability (thermal and electrical)

• Molecules can be synthesized prior to attachment or stepwise added on the surface

• Surface attachment group (tether or linker)• Composition determines site of

attachment, stability (i.e., endurance), charge transfer rate, charge retention

Werner G. Kuhr, The Electrochemical Society Interface, Spring 2004

Molecular Memory

Array

How It Works (Overview)

“Molecular Storage Element”

Memory Cell

• Individual molecules store information as electric charge

• Engineered characteristics• Scalable• Multiple bit capability

• Multiple molecules per memory element • Defect tolerance• Selective self-assembly to chosen surface type

• Different device structures and architectures• Multiple products• Multiple markets

~ 1 nm

READWRITE

Conventional Memory Element

MemoryElement

Bit Line

Word LineOFFON

Molecular Memory Element

READWRITE(1)

WRITE(2)

MemoryElement

Bit Line

Word LineOFFON

Molecular Memory Cell Schematic

Enabling 90nm and Beyond

• ZettaCore™ technology does not require stack or trench

• 10-700 times charge storage efficiency of standard dielectric materials

• Our 1Mb chip already uses 1/10th the capacitor area of conventional technology

Trench Capacitor Design

Trench aspect ratio can be 100:1 now

Stacked Capacitor Design

Stacked design increases cell size and uses multiple layers

to overlap capacitors

• Capacitor requires ~1/3 of process steps now• Difficulty scaling beyond 90nm node

Capacitor vs. Electrochemical Cell

• Capacitive Charging Current• Q = V . C• i(t) =[Q/(R.C)] exp (-t / RC)

Capacitor Electrochemical Cell+ - + + - -+ - +- +-+ ++-+-+-+-+-+--+-+

X (nm)

V

V-

V+

X (nm)

V

V-

V+

• Faradaic Current (iEC) due to redoxprocesses used for charge storage

– Faradaic Charge (Q=n.F.A. Γsurface)– Rate of electron transfer

» keff = ko . exp [nF(V-Vo)/RT]– iEC(t) = Q.keff, usually limited by RC of

underlying electronics

E(x) = ∆V/∆x E(x) = (V+ -V-) exp(-κx)

Electrolyte

e.g., Electrochemical Methods : Fundamentals and Applications, by Allen J. Bard, Larry R. Faulkner, John Wiley & Sons

-1.5

-1

-0.5

0

0.5

1

1.5

2

0 5 10 15 20 25 30

0

0.2

0.4

0.6

0.8

1

1.2

1.4

1.6

0 5 10 15 20 25 30

-1.5

-1

-0.5

0

0.5

1

1.5

2

00.250.50.7511.251.5

Cyclic Voltammetry Basics

Input Waveform (Voltage) vs. Time Output Waveform (Current) vs. Time

Output Waveform Plotted as a Voltammogram (Current vs. Voltage)• Cyclic Voltammetry is a measurement

of the current response to a triangular input voltage waveform

• Typical values for slope range from about 100mV/s to about 100V/s

• Voltammograms are generally plotted with higher oxidizing potential on the left, oxidizing current flow on the bottom (axes reversed)

IdealResistorI=V/R

IdealCapacitorI=C dV/dt

IdealInductor

IdealResistor

IdealCapacitor

IdealInductor

I=1/L $V dt(IC: Io=0)

Cyclic Voltammetry Basics

CV of 2-state Porphyrin SAM

1.2 0.8 0.4 0.0-60

-40

-20

0

20

40

Curr

ent (

µA)

E (V vs. Ag/Ag+)

A

B

C

D

I

E

H

G

FJ

AB – Oxidation (removal of electron) of the first state of the molecule beginsB – Oxidation of the first state reaches peak charge removalBC – Oxidation of the first state of molecules complete. At this voltage (~1V), the molecule’s first state electron has been removed while the second state electron remainsABC – the area under this curve represents the total charge “dumped” by oxidizing the first stateCD - Oxidation of second state of molecules begins, etc.

Note:• Can use both states simultaneously to effectively double the charge stored in each cell • Writing a “1” to the cell is accomplished by applying ~1.4V potential across the cell and fully oxidizing the molecules in that cell. • Reading a “1” is accomplished by applying a pre-charged bit line voltage to the cell and sensing the delta between the cell voltage and a reference cell voltage.

Oxidation:Electron removed=> Positive charge

Cyclic Voltammetry Basics

CV of 2-state Porphyrin SAM

1.2 0.8 0.4 0.0-60

-40

-20

0

20

40

Curr

ent (

µA)

E (V vs. Ag/Ag+)

A

B

C

D

I

E

H

G

FJ

FG – Reduction (addition of electron) of the second state of molecule beginsG – Reduction of second state reaches peak charge additionGH – Reduction of second state of molecules complete. At this voltage (~1V), the molecule’s second state electron has been added while the first state remains vacantFGH – the area under this curve represents the total charge “transferred” by reducing the second stateHI - Reduction of the first state of molecules begins, etc.

Note:• Writing a “0” to the cell is accomplished by applying ~0V potential across the cell and fully reducing the molecules in that cell. • Reading a “0” is accomplished by applying a pre-charged bit line voltage to the cell and sensing the delta between the cell voltage and a reference cell voltage.

Reduction:Electron added

=> Neutral

ZettaCore Molecular Device Basics

• A standard parallel plate capacitor in parallel with the molecular structure which acts like a pseudo-battery

• A self-assembled monolayer (SAM) of ZC designed molecules physically connected to a working electrode (WE) via a chemical bond (can readily transfer electrons)

• A charge transfer layer (CTL), which not only acts as a standard capacitor dielectric, but also interacts with the SAM electrochemically to create the pseudo-battery charge storage device.

• The molecular device is charged when a positive voltage, greater than a well defined threshold value, is applied to the WE (with respect to control electrode, CE). The resulting current extracts electrons from the molecular layer (i.e. oxidizes the molecules) leaving it positively charged.

• To "read" out this charge, a low conduction path to a supply of available electrons must be supplied to allow the charge to flow out of (reduce) the molecules, thereby discharging the SAM “battery” to its original state.

+-+-+-+-+--+-+-+-+-+

Counter electrode (CE)

Working electrode (WE)

CTLSAM

+

-

e-

Criteria for Selection of Charge Storage Molecules for DRAM Applications

TD > 400o C.HighThermal stability

Endurance > 1015 cyclesHighEndurance

Selective formation of covalent bond

Formation of covalent bond

Long

Fast

High

Criterion

Depends on substrate and patterning material

Tether selection depends on substrate

t½ > 10 s

tR/W= 1/keff < 10 ns

Delocalized cationic charge

Implementation

Self-alignment

Self-assembly

Charge retention

Read/write speed

Chemical stability

Property

Porphyrin-Based Molecular Architectures(>250 synthesized and characterized to date)

S

ON N

N N

Eu

NN

NNN

N

NN

Eu

NN

NNN

N

NN

N NN N

Zn N NN N

Zn SO

tBu

tBu tBu

tBu

tButBu

tBu

tBu tBu tBu

N

N

N

N

Zn

FF

F

F

FF

N NN N

N

N

N

NZn

F

F

F

F

F

F

Zn

S

S

O

O

N NN N

Zn SH

1. Monomer

2. Ferrocene-porphyrin

3. Winged trimer

4. Direct-linked dimer

5. Triple-decker sandwich

N NN N

SZnNHEt

O

Fe

Clausen et. al. (2000) J. Org. Chem., 65, 7363-7370; ibid, 7371-7378.Gryko et. al. (2000). J. Org. Chem., 65, 7345-7355; ibid, 7356-7362.Li et. al. (2000). J. Org. Chem., 65, 7379-7390.

Molecular Memory

Array Memory Element

A memory element contains 1000s of molecules;

we are not attempting single-molecule electronics

Molecular Memory Using Charge Storage in Molecules

Redox-active molecule

Molecular Memory Element Design

Tether (linker and surface attachment group)Composition determines site of attachment, stability,

electron-transfer rate, charge retention

Charge-storage elementComposition determinescharge density, size, isolation, voltage, stability (thermal and electrical)

An electrochemical cell:

Porphyrin-based Information Storage Molecules

• S = Selenium• Ac = Acetate Group• PMn; n: # carbon; each

adds 1.5A• Different lengths affect

charge transfer and retention properties

Importance of SAM Formation for Device Applications

CV of Porphyrin SAM

1.2 0.8 0.4 0.0-60

-40

-20

0

20

40

Cur

rent

( µA

)

E (V vs. Ag/Ag+)

P

Silicon

O OO O O O O O

P P P P PP P

1.6 1.2 0.8 0.4 0.0

-2

-1

0

1

2

Curr

ent (µA

)

E (V vs. Ag/Ag+)

CV of Porphyrin Thin Film

Silicon

P

P

P

PP

P P

P

Surface Attachment Groups

Multi-state Storage

1.6 1.2 0.8 0.4 0.0

-3

-2

-1

0

Cur

rent

(µA

)Potential (V vs. Ag/Ag+)

N NN N

CeR1

R1

R1

NN

NN

N

NN

N NN N

Ce

R1

R1

R1

R1 R1

R1 = Tolyl(TTP)Ce[(t-Bu)4Pc]Ce(TTP)

E1/2 (v)State

+1.70+5/+6

+0.67+1/+2

+0.26 0/+1

+0.93+2/+3

+1.17+3/+4

+1.42+4/+5

Gryko et. al. (2001) J. Mat. Chem., 11, 1162-1180. Schweikart et. al. (2002) J. Mat. Chem., 12, 808-828.

Six quantized redox states

7.52x10-9

725197

5.6x10-9

540192

9.75x10-11

9.4184

5.29x10-11

5.1196

N/A201

Coverage (mol/cm2)Charge Density (µC/cm2)

CVStructureMolecule No.

Effect of Molecular Composition on Charge Storage

Charge Density of a standard Si/SiO2dielectric capacitor is roughly 1-2 µC/cm2

N NN N

Zn

1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0.0 -0.2-35

-30

-25

-20

-15

-10

-5

0

5

10

15

Cur

rent

(nA)

Potential (V vs. Ag/AgCl)

1 V/s

S

1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0.0 -0.2-0.6

-0.4

-0.2

0.0

0.2

0.4

1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0.0 -0.2

-800

-600

-400

-200

0

200

400

600

800100 V/s

1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0.0 -0.2

-400

-300

-200

-100

0

100

200

300

400

N NN N

Zn HH

1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0.0 -0.2-600

-400

-200

0

200

400

600

Cur

rent

(nA)

Potential (V vs. Ag/AgCl)

Zn

Zn

ZnN NN N

N NN N

N NN N

Charge-Retention Characteristics of Porphyrin SAMs

2.6 x 104890PM3

3.7 x 104650PM2

5.5 x 104170PM1

6.5 x 104120PM0

k0 (s–1)t1/2 (s)Molecule

Electron-transfer Rates of Porphyrin SAMs

4.4 x 1082.6 x 104PM3

6.3 x 1083.7 x 104PM2

9.3 x 1085.5 x 104PM1

1.1 x 1096.5 x 104PM0

keffcalc at E1/2 + 500 mV

k0 (s–1)meas at E1/2

Molecule

Rates can be driven faster at higher potentials

Stability of Porphyrins on Si Platforms

Voltammetric Response of Porphyrin Memory Element after Heating at 400 °C for 30 Minutes

1.6 1.4 1.2 1.0 0.8 0.6 0.4-0.8

-0.4

0.0

0.4

0.8

Cur

rent

(µA

)

Potential (V vs. Ag/Ag+)

100 V/s

Liu et al. Science 2003, 302, 1543-1545.

Response of Porphyrin Memory Element after Read/Write Cycling (100 ms pulses)

1.5 1.0 0.5 0.0-0.6

-0.4

-0.2

0.0

0.2

0.4

0.6Cycles

0 2.5 x 104

1.8 x 106

1.1 x 109

1.0 x 1010

Cur

rent

(µA

)

Potential (V vs. Ag/Ag+)

Liu et al. Science 2003, 302, 1543-1545.

0 2 4 6 8 10 1270

80

90

100

day 27day 21day 11day 1Cha

rge

(%)

Cycles (109)

Response of Porphyrin Memory Element after Read/Write Cycling (5 ms pulses)

1.5 1.0 0.5 0.0-0.6

-0.4

-0.2

0.0

0.2

0.4

0.6Cycles

0 3.0x104

3.0x106

4.5x108

6.0x1010

1.2x1011

Cur

rent

(µA

)

Potential (V vs. Ag/Ag+)

Liu et al. Science 2003, 302, 1543-1545.

104 105 106 107 108 109 1010 101160

70

80

90

100

min 15sec 30sec 1 day 3

day 13

day 1

Cha

rge

(%)

Cycles

Scalability of Porphyrin SAMs

CV (100 Vs-1) of ZnP SAM on Au microbands

1200 800 400 0

-0.15

-0.1

-0.05

0.0

0.05

0.1

0.15

Cur

rent

(nA

)

Potential (mV vs. Ag/Ag+)

1000 500 0

-10

-5

0

5

Cur

rent

(nA

)

Potential (mV vs. Ag/Ag+)

100 µm2 band

2 µm2 band

2

100

500

Area(µm2)

0.08122

1.940

1614

t1/2

(µs)σ

(µC/cm2)

• Response time depends on circuit RC time constant

• Charge density independent of area

0.0 2.0 4.0 6.0 8.0 10.050 µA

Time (µs)

Charge Retention after 100 s

Molecule Summary

• Charge storage properties of molecules are well understood, characterized and engineerable• High charge density facilitates fabrication of sub-100nm

memory cells

• Molecular properties are intrinsic and engineered into molecules• Voltage, charge density, density of states, charge transfer

and charge retention properties accessible via chemical synthesis

• Compatible with BEOL processing for CMOS devices

Status - Technology

December, 2002: The world’s first practical molecular memory chip, a fully addressable silicon-based prototype memory array.

June, 1999: A 4x4 array of gold electrodes on glass used to characterize molecules. The entire apparatus was immersed in a liquid electrolyte solution to make measurements.

NOW, the first full-scale engineering test chip, 1 MB Hybrid CMOS/Molecular DRAM array.

Werner G. Kuhr, The Electrochemical Society Interface, Spring 2004

• TC3 chips packaged for onboard DRAM row evaluation (SiO2capacitors; no molecules)

• Evaluations performed to confirm circuit functionality

• Write, read, addressing capability• Data generator and “Z-Form”

evaluation platform utilized and functionality confirmed

Test Results - Basic OperationFirst Samples Without Molecules

Test Results – Molecular Operation

• Liquid electrolyte probing• Bottom electrode deposition and patterning• Molecule attachment• Liquid electrolyte placement• Top electrode bias through probe

Memory cell

N+ - Source N+ - Drain

Memory cell

N+ - SourceN+ - Drain

M2

M1VIAS

Memory cell

N+ - Source N+ - Drain

Memory cell

N+ - SourceN+ - Drain

M2

M1

GATE

SiO2passivation

Liquid electrolyte

Top electrodeprobe

Molecular Operation

Silver probe

Electrolyte drop

• All banks tested demonstrated charge storage in molecules

• Bits pass only when functional molecules are present and in contact with electrolyte

• Bits pass with same voltage dependence as demonstrated electrochemically in single cells

Red - failing cellGreen - passing cellGray - untested

Molecular Integration in CMOS for Manufacturing

• Replace COB capacitor in a DRAM by ZC molecular device• Use compatible metal instead of Si as the bottom working electrode• Choose tether, molecules, and CTL layer to withstand backend

processing temperatures (no liquid electrolytes!)• Use compatible metal as the top working electrode• Compatibility with baseline logic CMOS roadmap• Process and molecule design for:

• High charge density• Fast switching response• High endurance• Good retention• Eliminate any contamination

• Equipment for molecule attachment

Technology Development Methodology

Topological Design Rules

KEYSTONE PRODUCT

Process Flow Design

Process Module Objective Specs Electrical Design Rules/Models

Process/Device/Circuit/Rel Simulation

Facility/Contamination Requirements

Equipment Requirements

Process Module Development

Process Modules with good Cp, Cpk

Process reviews with Manufacturing

Cell Design for Keystone Product

Test Chip Design w/ product

Process Integration/RunsheetDevice Design

Shortloops/Device Fabrication

Model Verification/Tweaking

Design of Exp/Module Characterization

Topology /Process Simulations

Yield/Manufacturing Requirements

Technology/Product Characterization: Device, Process, Circuit, Reliability

Yield Enhancement/Final Design Rules

Alpha Samples Full Rel Qual

Device Parameters w/ good Cp, Cpk

Final Specifications: Technology Released for New Products

Production Transfer Goal: Product w/ good Cp, Cpk wrt

Customer Requirements

Continuous Improvement Programs

Yield/Cost Models, Defect Densities

Design Offshoot Technologies

Shrivastava: 1991 VLSI Symposium Short Course

Learn from the Past Example: Issues in Cu Integration

Noguchi, IEEE IRPS Symposium 2001

Learn from the Past Example: Issues in Cu Integration

Learn from the Past Example: Issues in Cu Integration

Details of ZettaCore Molecular Integration

Partners

• Foundries

• Fabless semiconductor companies

• Semiconductor manufacturers

• Tool manufacturers

• Chemical supply companies

Conclusion: The ZettaCore Advantage

• Market – addresses a huge market• Density – DRAM density and beyond• Fab/equipment – use of standard CMOS process & equipment• Process complexity reduction – flatter topology• Cost – lower cost

• Smaller number of steps• Less equipment• Shorter fab cycle time, better inventory control

• Capability – one of the few good approaches below 65nm• Reliability

• Single molecule defect not a killer as in oxide weak spot• Lower defect density and SER

Conclusion: Challenges and Risk Management

• Like any new technology – needs to be proven out in volume• Limit new process modules – “only” one new process module• Lower backend temperature – consistent with CMOS process

trend• New “killer” application not needed (e.g., cell phones/Digital

cameras for Flash) – market exists• New materials (e.g., porphyrin) – new low-k materials in silicon

technologies have similar new materials

Some Memorable Quotes…

• “New technologies are like a new-born:• Need to feed him enough for sure• Hard to predict how much he may grow• May develop unknown strange habits”(Takasu, Rohm Corp., 1999 VLSI Symposium Panel Discussion)

• “Prediction is very difficult, especially about the future”(Niels Bohr, Nobel Laureate, Danish Physicist)

Nanotechnology Next: Good Science, Engineering and Hard Work!

“For successful technology, reality must take precedence over public relations, for Nature can not be fooled”

Richard P. Feynman, Nobel Laureate1988 quote from the appendix to the Rogers Commission Report on the Space Shuttle

Acknowledgement

• Data for this presentation came from many sources listed in the references, as well as work done by dedicated employees at ZettaCore, Inc.

• Special thanks to:• Werner Kuhr & R&D team• Craig Rhodine & Engineering team• Process development team

About the Speaker

Ritu Shrivastava is vice president of Process and Manufacturing Technology, at ZettaCore, Inc. He has over 24 years of semiconductor industry experience and is responsible for guiding the company’s molecular technology integration and manufacturing strategy. Before ZettaCore, he was vice president and general manager, technology development and operations at Alliance Semiconductor where he worked with numerous foundries and IDMs co-developing new technologies for volume manufacturing of SRAM, DRAM and Flash memories, as well as mixed signal products. Prior to Alliance, Shrivastava worked at Cypress Semiconductor for more than 10 years where he held various senior technology management positions during the company’s growth from a startup in 1983 to an established and well-respected company.

Shrivastava began his industry career at Mostek Corporation/United Technologies, after serving on the faculty at Louisiana State University. He earned a B.E. and an M.E. with distinction in electrical engineering from the Indian Institute of Science, Bangalore, and a Ph.D. in electrical engineering from Louisiana State University. He is a Fellow of IEEE, and an inventor with more than 20 patents related to semiconductor technologies. Shrivastava also serves as CMOS technology editor for IEEE Transactions on Electron Devices.

References

35. Integration of Molecular Components into Silicon Memory Devices, Interface, Spring, pp.34-38, (2004).34. A Scalable Synthesis of Meso-Substituted Dipyrromethanes, Organic Process Research & Development, 7(6), 799 – 812 (2004).33. Diverse Redox-Active Molecules Bearing Identical Thiol-Terminated Tripodal Tethers for Studies of Molecular Information, J. Org. Chem., 69(5); 1461-1469 (2004).32. Porphyrins Bearing Arylphosphonic Acid Tethers for Attachment to Oxide Surfaces, J. Org. Chem., 69(5); 1444-1452 (2004).31. Diverse Redox-Active Molecules Bearing O-, S-, or Se-Terminated Tethers for Attachment to Silicon in Studies of Molecular Information Storage, J. Org. Chem., 69(5); 1435-1443 (2004).30. Porphyrins Bearing Mono or Tripodal Benzylphosphonic Acid Tethers for Attachment to Oxide Surfaces, J. Org. Chem., 69(5); 1453-1460 (2004).29. A Tin-Complexation Strategy for Use with Diverse Acylation Methods in the Preparation of 1,9-Diacyldipyrromethanes, J. Org. Chem., 69(3); 765-777 (2004).28. Synthesis of Cyclic Hexameric Porphyrin Arrays Anchors for Surface Immobilization and Columnar Self-Assembly, J. Org. Chem., 68(21); 8199-8207 (2003).27. Hybrid Silicon/Molecular Memories: Co-Engineering for Novel Functionality, Technical Digest-IEEE Meeting on Electron Devices, 2003, 537-540 (2003).26. Molecular Memories that Survive Silicon Device Processing and Real-World Operation, Science, 302, 1543-45 (2003).25. Bis(S-acetylthio)-Derivatized Europium Triple-Decker Monomers and Oligomers, Inorg. Chem.42(23): 7431-7446 (2003).

References (Continued)

24. Modified carbon surfaces as "organic electrodes" that exhibit conductance switching, Anal. Chem.75(2): 296-305 (2003).23. Electrical Characterization of Redox-Active Molecular Monolayers on SiO2 for Memory Applications, Appl. Phys. Lett., 83(1), 198-200 (2003).22. Measurements of Electron-Transfer Rates of Charge-Storage Molecular Monolayers on Si(100). Towards Hybrid Molecular/Semiconductor Information Storage Devices, J. Amer. Chem. Soc., 125 (2): 505-517 (2003).21. Charge-Retention Characteristics of Self-Assembled Monolayers of "Molecular-Wire" Linked Porphyrins on Gold, A.C.S. Symposium Series, 844, 51-61 (2003).20. Mono- and Multilayer Formation by Diazonium Reduction on Carbon Surfaces Monitored with Atomic Force Microscopy ‘Scratching'," Anal. Chem., 75, 3837-3844 (2003). 19. Modified Carbon Surfaces as ‘Organic Electrodes' that Exhibit Conductance Switching," Anal. Chem., 75, 296-305 (2003).18. Characterization of Charge Storage in Redox SAMs, Langmuir, 18(10): 4030-4040 (2003).17.Design, Synthesis, and Characterization of Prototypical Multistate Counters in Three Distinct Architectures, J. Mat. Chem., 12 (4): 808-828 (2002).16. Comparison of Electron-Transfer and Charge-Retention Characteristics of Porphyrin-Containing Self-Assembled Monolayers Designed for Molecular Information Storage, J. Phys. Chem. B., 106, 8639-8648 (2002).15. Capacitance and Conductance Characterization of Ferrocene-Containing Self-Assembled Monolayerson Silicon Surfaces for Memory Applications, Applied Physics Letters, 81, 1494-1496 (2002). 14. Mechanism for Conductance Switching in Carbon-based Molecular Electronic Junctions," Electrochem. Solid State Letters, 5, E43- E46 (2002).

References (Continued)

13. Electronic conductance behavior of carbon-based molecular junctions with conjugated structures, J. Phys. Chem. B 106(40): 10355-10362 (2002). 12. A High Accuracy Current-Mode Sense Amplifier for Molecular Memory, 2002, CICC, pp. 103-106.11. In situ Raman spectroelectrochemistry of electron transfer between glassy carbon and a chemisorbed nitroazobenzene monolayer, J. Am. Chem. Soc. 124(36): 10894-10902 (2002). 10. Covalently bonded organic monolayers on a carbon substrate: A new paradigm for molecular electronics, Nano Letters 1(9): 491-494 (2001).9. Studies Related to the Design and Synthesis of a Molecular Octal Counter, J. Mat. Chem., 11(4), 1162-1180 (2001).8. Investigation of Rational Syntheses of Heteroleptic Porphyrinic Lanthanide (Europium, Cerium) Triple-Decker Sandwich Complexes, Inorg. Chem. 40, 4762–4774 (2001).7. Synthesis of Thiol-Derivatized Europium Porphyrinic Triple-Decker Sandwich Complexes for MultibitMolecular Information Storage. J. Org. Chem., 65, 7379-7390 (2000).6. Synthesis of Thiol-Derivatized Ferrocene-Porphyrins for Studies of Multibit Information Storage. J. Org. Chem., 65, 7356-7362 (2000).5. Synthesis of "Porphyrin-Linker-Thiol" Molecules with Diverse Linkers for Studies of Molecular-Based Information Storage. J. Org. Chem., 65, 7345-7355 (2000).4. Investigation of Tightly Coupled Porphyrin Arrays Comprised of Identical Monomers for MultibitInformation Storage. J. Org. Chem., 65, 7371-7378 (2000).3. Synthesis of Thiol-Derivatized Porphyrin Dimers and Trimers for Studies of Architectural Effects on Multibit Information Storage. J. Org. Chem., 65, 7363-7370 (2000).2. Molecular approach toward information storage based on the redox properties of porphyrins in self-assembled monolayers, J. Vac. Sci. Technol., B, 18, 2359-2364 (2000).1. Thiol-Derivatized Porphyrins for Attachment to Electroactive Surfaces, J. S. J. Org. Chem. 64, 8635–8647 (1999).